fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
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//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_byte_deserializer
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//
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// Description:
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// Slave interface of CtrlPort interface serialized as byte stream.
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// See description in ctrlport_byte_serializer module for more details.
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//
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`default_nettype none
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module ctrlport_byte_deserializer (
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Request
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [31:0] m_ctrlport_req_data,
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// Response
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data,
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// byte interface
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input wire [ 7:0] bytestream_data_in,
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input wire bytestream_valid_in,
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input wire bytestream_direction,
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output reg [ 7:0] bytestream_data_out = 8'b0,
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output reg bytestream_valid_out = 1'b0,
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output reg bytestream_output_enable = 1'b0
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);
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`include "../../../lib/rfnoc/core/ctrlport.vh"
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//---------------------------------------------------------------
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// transfer constants
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//---------------------------------------------------------------
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// derived from transaction specification
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localparam NUM_BYTES_RX_READ = 2;
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localparam NUM_BYTES_TX_READ = 5;
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localparam NUM_BYTES_RX_WRITE = 6;
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localparam NUM_BYTES_TX_WRITE = 1;
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localparam SPI_TRANSFER_ADDRESS_WIDTH = 15;
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//----------------------------------------------------------
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// handle transfer
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//----------------------------------------------------------
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localparam INIT_RX = 2'd0;
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localparam RECEIVE = 2'd1;
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localparam WAIT_RESPONSE = 2'd2;
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localparam SENDING = 2'd3;
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// internal registers
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reg [ 1:0] state = INIT_RX;
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reg [NUM_BYTES_RX_WRITE*8-1:0] request_cache = {NUM_BYTES_RX_WRITE*8 {1'b0}};
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reg [ NUM_BYTES_TX_READ*8-1:0] response_cache = {NUM_BYTES_TX_READ*8 {1'b0}};
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reg [ 2:0] byte_counter = 3'b0;
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reg transfer_complete = 1'b0;
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reg write_transfer = 1'b0;
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// input registers to relax input timing
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reg [7:0] bytestream_data_in_reg = 8'b0;
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reg bytestream_valid_in_reg = 1'b0;
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reg bytestream_direction_reg = 1'b0;
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always @ (posedge ctrlport_clk) begin
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bytestream_data_in_reg <= bytestream_data_in;
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bytestream_valid_in_reg <= bytestream_valid_in;
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bytestream_direction_reg <= bytestream_direction;
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end
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// state machine
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always @ (posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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state <= INIT_RX;
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byte_counter <= 3'b0;
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transfer_complete <= 1'b0;
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bytestream_output_enable <= 1'b0;
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end else begin
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// default assignments
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transfer_complete <= 1'b0;
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// direction defined by master
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bytestream_output_enable <= bytestream_direction;
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bytestream_valid_out <= 1'b0;
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case (state)
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// additional cycle for switching to make sure valid signal is driven
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// from master when being in RECEIVE state
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INIT_RX: begin
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byte_counter <= 3'b0;
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if (bytestream_direction_reg == 0) begin
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state <= RECEIVE;
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end
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end
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// wait for reception of request from master
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RECEIVE: begin
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if (bytestream_valid_in_reg) begin
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byte_counter <= byte_counter + 1'b1;
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request_cache <= {request_cache[NUM_BYTES_RX_WRITE*8-9:0], bytestream_data_in_reg};
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// capture write or read
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if (byte_counter == 0) begin
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write_transfer <= bytestream_data_in_reg[7];
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end
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// wait until request completes
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if ((write_transfer && byte_counter == NUM_BYTES_RX_WRITE-1) ||
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(~write_transfer && byte_counter == NUM_BYTES_RX_READ-1)) begin
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transfer_complete <= 1'b1;
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state <= WAIT_RESPONSE;
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end
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end
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// Workaround for missing pull down resistor:
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// Use pull up and schmitt trigger to detect FPGA reload by line going high unexpectedly
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if (bytestream_direction_reg == 1) begin
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state <= INIT_RX;
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end
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end
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WAIT_RESPONSE: begin
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byte_counter <= 3'b0;
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if (m_ctrlport_resp_ack) begin
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state <= SENDING;
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if (write_transfer) begin
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response_cache <= {5'b0, 1'b1, m_ctrlport_resp_status, 32'b0};
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end else begin
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response_cache <= {m_ctrlport_resp_data, 5'b0, 1'b1, m_ctrlport_resp_status};
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end
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end
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//abort by host
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if (bytestream_direction_reg == 0) begin
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state <= INIT_RX;
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end
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end
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SENDING: begin
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bytestream_valid_out <= 1'b1;
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bytestream_data_out <= response_cache[NUM_BYTES_TX_READ*8-8+:8];
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response_cache <= {response_cache[NUM_BYTES_TX_READ*8-9:0], 8'b0};
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byte_counter <= byte_counter + 1'b1;
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// wait until request completes
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if ((write_transfer && byte_counter == NUM_BYTES_TX_WRITE-1) ||
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(~write_transfer && byte_counter == NUM_BYTES_TX_READ-1)) begin
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state <= INIT_RX;
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end
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//abort by host
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if (bytestream_direction_reg == 0) begin
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state <= INIT_RX;
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end
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end
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default: begin
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state <= INIT_RX;
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end
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endcase
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end
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end
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//----------------------------------------------------------
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// assign request to ctrlport
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//----------------------------------------------------------
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assign m_ctrlport_req_wr = write_transfer & transfer_complete;
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assign m_ctrlport_req_rd = ~write_transfer & transfer_complete;
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assign m_ctrlport_req_data = request_cache[0+:CTRLPORT_DATA_W];
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assign m_ctrlport_req_addr = (write_transfer) ?
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// Skipping data in LSBs to get to the address for writes.
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{5'b0, request_cache[CTRLPORT_DATA_W+:SPI_TRANSFER_ADDRESS_WIDTH]} :
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// Full request = address of 2 bytes in LSBs.
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{5'b0, request_cache[0+:SPI_TRANSFER_ADDRESS_WIDTH]};
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endmodule
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`default_nettype wire
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@@ -0,0 +1,228 @@
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//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_byte_serializer
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//
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// Description:
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// Serializes CtrlPort requests into a byte stream.
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//
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// The serialized data is similar to an AXI4-Streaming interface with one byte
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// per clock cycle and a valid signal. Direction controls the current transmission
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// direction. 0 = Master to Slave, 1 = Slave to Master, where this module is the
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// master. Direction is always present in direction master to slave where the
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// other signals valid and data can be shared on a tri-state bus.
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//
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// The transmission is defined as described below. The bytes are transmitted MSB
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// first.
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// Write request:
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// 1'b1 = write, 15 bit address, 32 bit data (MOSI) = 6 bytes request
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// 5 bit padding, 1 bit ack, 2 bit status = 1 byte response
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// Read request:
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// 1'b0 = read, 15 bit address = 2 bytes request
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// 32 bit data, 5 bit padding, 1 bit ack, 2 bit status = 5 bytes response
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//
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// When sharing valid and data signal lines between master and slave the
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// timing is defined as:
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//
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// clk __/--\__/--\__/--\__/--\__/--\__/--\__/--\__/--\__/--\__/--\__/--\__
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// direction _______________________/-----------------\____________
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// master output enable _____/-----------------\______________________________
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// slave output enable _____________________________/-----------------\______
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// valid & data zzzzz| Master driven | zzz | Slave driven | zzzzz
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// transaction <--- Request ---><--- Response --->
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//
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// The slave should use the direction signal to derive it's own output enable
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// leaving the master the option to terminate the transaction.
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// On switch from slave to master the direction has to be changed at least
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// one clock cycle before enabling the master output enable to avoid driving the
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// bus from two sources.
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//
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`default_nettype none
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module ctrlport_byte_serializer (
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// Clock and Reset
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Request
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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// Response
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output reg s_ctrlport_resp_ack = 1'b0,
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output reg [ 1:0] s_ctrlport_resp_status = 2'b0,
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output reg [31:0] s_ctrlport_resp_data = 32'b0,
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// GPIO interface
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input wire [ 7:0] bytestream_data_in,
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input wire bytestream_valid_in,
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output reg [ 7:0] bytestream_data_out = 8'b0,
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output reg bytestream_valid_out = 1'b0,
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output reg bytestream_direction = 1'b0,
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output reg bytestream_output_enable = 1'b1
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);
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`include "../../../lib/rfnoc/core/ctrlport.vh"
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//---------------------------------------------------------------
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// transfer constants
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//---------------------------------------------------------------
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// derived from the transaction format (see description above)
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localparam NUM_BYTES_TX_READ = 2;
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localparam NUM_BYTES_RX_READ = 5;
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localparam NUM_BYTES_TX_WRITE = 6;
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localparam NUM_BYTES_RX_WRITE = 1;
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localparam TIMEOUT_COUNTER_WIDTH = 6;
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//----------------------------------------------------------
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// FSM to handle transfers
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//----------------------------------------------------------
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localparam IDLE = 3'd0;
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localparam SENDING = 3'd1;
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localparam INIT_RX = 3'd2;
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localparam DIR_SWITCH = 3'd3;
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localparam DIR_SWITCH_DLY = 3'd4;
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localparam RECEIVING = 3'd5;
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localparam ACK = 3'd6;
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localparam TIMEOUT = 3'd7;
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// input registers to relax input timing
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reg [7:0] bytestream_data_in_reg = 8'b0;
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reg bytestream_valid_in_reg = 1'b0;
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always @ (posedge ctrlport_clk) begin
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bytestream_data_in_reg <= bytestream_data_in;
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bytestream_valid_in_reg <= bytestream_valid_in;
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end
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// internal registers
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reg [ 2:0] state = IDLE;
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reg [NUM_BYTES_TX_WRITE*8-1:0] request_cache = {NUM_BYTES_TX_WRITE*8{1'b0}};
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reg [ NUM_BYTES_RX_READ*8-1:0] response_cache = {NUM_BYTES_RX_READ*8{1'b0}};
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reg [ 2:0] byte_counter = 3'b0;
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reg write_transfer = 1'b0;
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reg [TIMEOUT_COUNTER_WIDTH-1:0] timeout_counter = {TIMEOUT_COUNTER_WIDTH {1'b0}};
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always @ (posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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state <= IDLE;
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bytestream_valid_out <= 1'b0;
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byte_counter <= 3'b0;
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bytestream_direction <= 1'b0;
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bytestream_output_enable <= 1'b1;
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s_ctrlport_resp_ack <= 1'b0;
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end else begin
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case (state)
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IDLE: begin
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// reset values from previous states
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s_ctrlport_resp_ack <= 1'b0;
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bytestream_valid_out <= 1'b0;
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bytestream_output_enable <= 1'b1;
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byte_counter <= 3'b0;
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timeout_counter <= {TIMEOUT_COUNTER_WIDTH {1'b0}};
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// start transmission on read or write
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if (s_ctrlport_req_rd || s_ctrlport_req_wr) begin
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state <= SENDING;
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request_cache <= {s_ctrlport_req_wr, s_ctrlport_req_addr[14:0], s_ctrlport_req_data};
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write_transfer <= s_ctrlport_req_wr;
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end
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end
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// send as many bytes as required for read / write
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SENDING: begin
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bytestream_data_out <= request_cache[NUM_BYTES_TX_WRITE*8-8+:8];
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request_cache <= {request_cache[NUM_BYTES_TX_WRITE*8-9:0], 8'b0};
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bytestream_valid_out <= 1'b1;
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byte_counter <= byte_counter + 1'b1;
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if ((write_transfer && byte_counter == NUM_BYTES_TX_WRITE-1) ||
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(~write_transfer && byte_counter == NUM_BYTES_TX_READ-1)) begin
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state <= INIT_RX;
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end
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end
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// first cycle for switching to make sure valid signal is driven
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// from slave when being in RECEIVING state
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INIT_RX: begin
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state <= DIR_SWITCH;
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bytestream_direction <= 1'b1;
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bytestream_output_enable <= 1'b0;
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bytestream_valid_out <= 1'b0;
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byte_counter <= 3'b0;
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end
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// second switching cycle to let CPLD load the lines based on direction
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DIR_SWITCH: begin
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state <= DIR_SWITCH_DLY;
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end
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// third switching cycle to compensate data input register
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DIR_SWITCH_DLY: begin
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state <= RECEIVING;
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end
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// wait for response to be received
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// immediately change direction after successful reception to have one
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// clock cycle of pause to avoid double driving the bus
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RECEIVING: begin
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timeout_counter <= timeout_counter + 1;
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if (bytestream_valid_in_reg) begin
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byte_counter <= byte_counter + 1'b1;
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response_cache = {response_cache[NUM_BYTES_RX_READ*8-9:0], bytestream_data_in_reg};
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if ((write_transfer && byte_counter == NUM_BYTES_RX_WRITE-1) ||
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(~write_transfer && byte_counter == NUM_BYTES_RX_READ-1)) begin
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state <= ACK;
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bytestream_direction <= 1'b0;
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end
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end
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if (timeout_counter == {TIMEOUT_COUNTER_WIDTH {1'b1}}) begin
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state <= TIMEOUT;
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bytestream_direction <= 1'b0;
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end
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end
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// issue ctrlport response
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ACK: begin
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state <= IDLE;
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s_ctrlport_resp_ack <= 1'b1;
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// status based on received ack
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s_ctrlport_resp_status <= response_cache[2] ? response_cache[1:0] : CTRL_STS_CMDERR;
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if (write_transfer) begin
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s_ctrlport_resp_data <= 32'b0;
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end else begin
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s_ctrlport_resp_data <= response_cache[39:8];
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end
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end
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TIMEOUT: begin
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state <= IDLE;
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_status <= CTRL_STS_CMDERR;
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s_ctrlport_resp_data <= 32'b0;
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end
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default: begin
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state <= IDLE;
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end
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endcase
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end
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end
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endmodule
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`default_nettype wire
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@@ -0,0 +1,323 @@
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//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: db_gpio_interface
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//
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// Description:
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// Interface for GPIO interface towards daughterboards.
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//
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// A ControlPort interface is serialized into bytes along with a valid signal.
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// The ControlPort supports write requests only. Byte enables are not supported.
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// There is support for timed commands.
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// Furthermore there are 4 state wires towards the DB. Ensure an appropriate
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// hold time on the states as the transmission happens in pll_ref_clk, which is
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// slower than radio_clk. Pulses of e.g. just a single clock cycle may not get
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// transferred to the DB.
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//
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// The 20 available GPIO lines are assigned with
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// - 5x empty
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// - bytestream direction
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// - bytestream valid
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// - bytestream data (8 bits)
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// - 1x empty
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// - db_state (4 bits)
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//
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`default_nettype none
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module db_gpio_interface (
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// Clocks and reset
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input wire radio_clk,
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input wire pll_ref_clk,
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||||
|
||||
// DB state lines (domain: radio_clk)
|
||||
input wire [ 3:0] db_state,
|
||||
|
||||
// time interfaces (domain: radio_clk)
|
||||
input wire [63:0] radio_time,
|
||||
input wire radio_time_stb,
|
||||
input wire [ 3:0] time_ignore_bits,
|
||||
|
||||
// Request (domain: radio_clk)
|
||||
input wire ctrlport_rst,
|
||||
input wire s_ctrlport_req_wr,
|
||||
input wire s_ctrlport_req_rd,
|
||||
input wire [19:0] s_ctrlport_req_addr,
|
||||
input wire [31:0] s_ctrlport_req_data,
|
||||
input wire [ 3:0] s_ctrlport_req_byte_en,
|
||||
input wire s_ctrlport_req_has_time,
|
||||
input wire [63:0] s_ctrlport_req_time,
|
||||
|
||||
// Response (domain: radio_clk)
|
||||
output wire s_ctrlport_resp_ack,
|
||||
output wire [ 1:0] s_ctrlport_resp_status,
|
||||
output wire [31:0] s_ctrlport_resp_data,
|
||||
|
||||
// GPIO interface (domain: pll_ref_clk)
|
||||
input wire [19:0] gpio_in,
|
||||
output wire [19:0] gpio_out,
|
||||
output wire [19:0] gpio_out_en,
|
||||
|
||||
// Version (Constant)
|
||||
output wire [95:0] version_info
|
||||
);
|
||||
|
||||
`include "../regmap/versioning_regs_regmap_utils.vh"
|
||||
`include "../regmap/versioning_utils.vh"
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Timed command processing
|
||||
//----------------------------------------------------------------------------
|
||||
wire [19:0] ctrlport_timed_req_addr;
|
||||
wire [31:0] ctrlport_timed_req_data;
|
||||
wire ctrlport_timed_req_rd;
|
||||
wire ctrlport_timed_req_wr;
|
||||
wire ctrlport_timed_resp_ack;
|
||||
reg [31:0] ctrlport_timed_resp_data = 0;
|
||||
reg [ 1:0] ctrlport_timed_resp_status = 0;
|
||||
|
||||
ctrlport_timer #(
|
||||
.EXEC_LATE_CMDS(1)
|
||||
) ctrlport_timer_i (
|
||||
.clk (radio_clk),
|
||||
.rst (ctrlport_rst),
|
||||
.time_now (radio_time),
|
||||
.time_now_stb (radio_time_stb),
|
||||
.time_ignore_bits (time_ignore_bits),
|
||||
.s_ctrlport_req_wr (s_ctrlport_req_wr),
|
||||
.s_ctrlport_req_rd (s_ctrlport_req_rd),
|
||||
.s_ctrlport_req_addr (s_ctrlport_req_addr),
|
||||
.s_ctrlport_req_data (s_ctrlport_req_data),
|
||||
.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en),
|
||||
.s_ctrlport_req_has_time (s_ctrlport_req_has_time),
|
||||
.s_ctrlport_req_time (s_ctrlport_req_time),
|
||||
.s_ctrlport_resp_ack (s_ctrlport_resp_ack),
|
||||
.s_ctrlport_resp_status (s_ctrlport_resp_status),
|
||||
.s_ctrlport_resp_data (s_ctrlport_resp_data),
|
||||
.m_ctrlport_req_wr (ctrlport_timed_req_wr),
|
||||
.m_ctrlport_req_rd (ctrlport_timed_req_rd),
|
||||
.m_ctrlport_req_addr (ctrlport_timed_req_addr),
|
||||
.m_ctrlport_req_data (ctrlport_timed_req_data),
|
||||
.m_ctrlport_req_byte_en (),
|
||||
.m_ctrlport_resp_ack (ctrlport_timed_resp_ack),
|
||||
.m_ctrlport_resp_status (ctrlport_timed_resp_status),
|
||||
.m_ctrlport_resp_data (ctrlport_timed_resp_data)
|
||||
);
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Clock domain crossing (radio_clk -> pll_ref_clk)
|
||||
//----------------------------------------------------------------------------
|
||||
// Radio_clk is derived from pll_ref_clk by an integer multiplier and
|
||||
// originate from the same PLL.
|
||||
// Therefore the clock crossing can be achieved by using simple registers.
|
||||
// Static timing analysis will be able to meet setup and hold requirements on
|
||||
// them.
|
||||
|
||||
// holding read and write flags for multiple radio_clk cycles
|
||||
reg ctrlport_timed_req_wr_hold = 1'b0;
|
||||
reg ctrlport_timed_req_rd_hold = 1'b0;
|
||||
|
||||
reg [19:0] ctrlport_req_addr_prc = 20'b0;
|
||||
reg [31:0] ctrlport_req_data_prc = 32'b0;
|
||||
reg ctrlport_req_rd_prc = 1'b0;
|
||||
reg ctrlport_req_wr_prc = 1'b0;
|
||||
|
||||
wire ctrlport_resp_ack_prc;
|
||||
wire [31:0] ctrlport_resp_data_prc;
|
||||
wire [ 1:0] ctrlport_resp_status_prc;
|
||||
|
||||
reg ctrlport_req_rd_fall = 1'b0;
|
||||
reg ctrlport_req_wr_fall = 1'b0;
|
||||
reg [31:0] ctrlport_resp_data_fall = 32'b0;
|
||||
reg [ 1:0] ctrlport_resp_status_fall = 2'b0;
|
||||
reg ctrlport_resp_ack_fall = 1'b0;
|
||||
|
||||
// Retime signals to falling edge of radio_clk.
|
||||
// Because radio_clk is more heavily loaded than pll_ref_clk, it arrives at
|
||||
// the FF's later, which leads to hold time violations when moving signals
|
||||
// from pll_ref_clk to radio_clk. By sampling on the falling edge of
|
||||
// radio_clk, we provide (nominally) half a radio_clk period of hold, while
|
||||
// reducing setup time by half. The late arrival of radio_clk adds back some
|
||||
// of the lost setup margin.
|
||||
always @(negedge radio_clk) begin
|
||||
ctrlport_req_rd_fall <= ctrlport_req_rd_prc;
|
||||
ctrlport_req_wr_fall <= ctrlport_req_wr_prc;
|
||||
ctrlport_resp_ack_fall <= ctrlport_resp_ack_prc;
|
||||
ctrlport_resp_status_fall <= ctrlport_resp_status_prc;
|
||||
ctrlport_resp_data_fall <= ctrlport_resp_data_prc;
|
||||
end
|
||||
|
||||
always @(posedge radio_clk) begin
|
||||
if (ctrlport_req_wr_fall) begin
|
||||
ctrlport_timed_req_wr_hold <= 1'b0;
|
||||
end else if (ctrlport_timed_req_wr) begin
|
||||
ctrlport_timed_req_wr_hold <= 1'b1;
|
||||
end
|
||||
if (ctrlport_req_rd_fall) begin
|
||||
ctrlport_timed_req_rd_hold <= 1'b0;
|
||||
end else if (ctrlport_timed_req_rd) begin
|
||||
ctrlport_timed_req_rd_hold <= 1'b1;
|
||||
end
|
||||
|
||||
// capture request address and data
|
||||
if (ctrlport_timed_req_wr || ctrlport_timed_req_rd) begin
|
||||
ctrlport_req_addr_prc <= ctrlport_timed_req_addr;
|
||||
ctrlport_req_data_prc <= ctrlport_timed_req_data;
|
||||
end
|
||||
end
|
||||
|
||||
// capture extended flags in pll_ref_clk domain
|
||||
always @(posedge pll_ref_clk) begin
|
||||
ctrlport_req_wr_prc <= ctrlport_timed_req_wr_hold;
|
||||
ctrlport_req_rd_prc <= ctrlport_timed_req_rd_hold;
|
||||
end
|
||||
|
||||
// search for rising edge in response
|
||||
reg [1:0] ctrlport_timed_ack_reg = 2'b0;
|
||||
always @(posedge radio_clk) begin
|
||||
ctrlport_timed_ack_reg = {ctrlport_timed_ack_reg[0], ctrlport_resp_ack_fall};
|
||||
end
|
||||
assign ctrlport_timed_resp_ack = ctrlport_timed_ack_reg[0] & ~ctrlport_timed_ack_reg[1];
|
||||
|
||||
// capture response data
|
||||
always @(posedge radio_clk) begin
|
||||
if (ctrlport_resp_ack_fall) begin
|
||||
ctrlport_timed_resp_status <= ctrlport_resp_status_fall;
|
||||
ctrlport_timed_resp_data <= ctrlport_resp_data_fall;
|
||||
end
|
||||
end
|
||||
|
||||
// transfer state lines
|
||||
reg [3:0] db_state_prc = 4'b0;
|
||||
reg [3:0] db_state_prc_fe = 4'b0;
|
||||
always @(posedge pll_ref_clk) begin
|
||||
db_state_prc <= db_state;
|
||||
end
|
||||
always @(negedge pll_ref_clk) begin
|
||||
db_state_prc_fe <= db_state_prc;
|
||||
end
|
||||
|
||||
// transfer reset
|
||||
reg ctrlport_rst_hold = 1'b0;
|
||||
reg ctrlport_rst_prc = 1'b0;
|
||||
reg ctrlport_rst_fall = 1'b0;
|
||||
always @(posedge radio_clk) begin
|
||||
if (ctrlport_rst) begin
|
||||
ctrlport_rst_hold <= 1'b1;
|
||||
end else if (ctrlport_rst_fall) begin
|
||||
ctrlport_rst_hold <= 1'b0;
|
||||
end
|
||||
end
|
||||
always @(posedge pll_ref_clk) begin
|
||||
ctrlport_rst_prc <= ctrlport_rst_hold;
|
||||
end
|
||||
always @(negedge radio_clk) begin
|
||||
ctrlport_rst_fall <= ctrlport_rst_prc;
|
||||
end
|
||||
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// Ctrlport serializer
|
||||
//----------------------------------------------------------------------------
|
||||
wire [7:0] bytestream_data_in;
|
||||
wire [7:0] bytestream_data_out;
|
||||
wire bytestream_direction;
|
||||
wire bytestream_output_enable;
|
||||
wire bytestream_valid_in;
|
||||
wire bytestream_valid_out;
|
||||
|
||||
ctrlport_byte_serializer serializer_i (
|
||||
.ctrlport_clk (pll_ref_clk),
|
||||
.ctrlport_rst (ctrlport_rst_prc),
|
||||
.s_ctrlport_req_wr (ctrlport_req_wr_prc),
|
||||
.s_ctrlport_req_rd (ctrlport_req_rd_prc),
|
||||
.s_ctrlport_req_addr (ctrlport_req_addr_prc),
|
||||
.s_ctrlport_req_data (ctrlport_req_data_prc),
|
||||
.s_ctrlport_resp_ack (ctrlport_resp_ack_prc),
|
||||
.s_ctrlport_resp_status (ctrlport_resp_status_prc),
|
||||
.s_ctrlport_resp_data (ctrlport_resp_data_prc),
|
||||
.bytestream_data_in (bytestream_data_in),
|
||||
.bytestream_valid_in (bytestream_valid_in),
|
||||
.bytestream_data_out (bytestream_data_out),
|
||||
.bytestream_valid_out (bytestream_valid_out),
|
||||
.bytestream_direction (bytestream_direction),
|
||||
.bytestream_output_enable (bytestream_output_enable)
|
||||
);
|
||||
|
||||
// IOB registers to drive data on the falling edge
|
||||
reg [7:0] bytestream_data_out_fe;
|
||||
reg bytestream_direction_fe;
|
||||
reg bytestream_output_enable_fe;
|
||||
reg bytestream_valid_out_fe;
|
||||
|
||||
// Signals are shifted into a falling edge domain to help meet
|
||||
// hold requirements at CPLD
|
||||
always @(negedge pll_ref_clk) begin
|
||||
if (ctrlport_rst_prc) begin
|
||||
bytestream_data_out_fe <= 8'b0;
|
||||
bytestream_valid_out_fe <= 1'b0;
|
||||
bytestream_direction_fe <= 1'b0;
|
||||
bytestream_output_enable_fe <= 1'b1;
|
||||
end else begin
|
||||
bytestream_data_out_fe <= bytestream_data_out;
|
||||
bytestream_valid_out_fe <= bytestream_valid_out;
|
||||
bytestream_direction_fe <= bytestream_direction;
|
||||
bytestream_output_enable_fe <= bytestream_output_enable;
|
||||
end
|
||||
end
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// wire assignment
|
||||
//----------------------------------------------------------------------------
|
||||
// 5 unused, 10 used, 1 unused and 4 used signals
|
||||
assign gpio_out = {5'b0, bytestream_direction_fe, bytestream_valid_out_fe, bytestream_data_out_fe, 1'b0, db_state_prc_fe};
|
||||
assign gpio_out_en = {5'b0, 1'b1, {9 {bytestream_output_enable_fe}}, 1'b0, {4 {1'b1}} };
|
||||
|
||||
assign bytestream_valid_in = gpio_in[13];
|
||||
assign bytestream_data_in = gpio_in[12:5];
|
||||
|
||||
//----------------------------------------------------------------------------
|
||||
// version_info
|
||||
//----------------------------------------------------------------------------
|
||||
|
||||
// Version metadata, constants come from auto-generated versioning_regs_regmap_utils.vh
|
||||
assign version_info = build_component_versions(
|
||||
DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME,
|
||||
build_version(
|
||||
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR,
|
||||
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR,
|
||||
DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD),
|
||||
build_version(
|
||||
DB_GPIO_IFC_CURRENT_VERSION_MAJOR,
|
||||
DB_GPIO_IFC_CURRENT_VERSION_MINOR,
|
||||
DB_GPIO_IFC_CURRENT_VERSION_BUILD));
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="VERSIONING_REGS_REGMAP">
|
||||
// <group name="VERSIONING_CONSTANTS">
|
||||
// <enumeratedtype name="DB_GPIO_IFC_VERSION" showhex="true">
|
||||
// <info>
|
||||
// Daughterboard GPIO interface.{BR/}
|
||||
// For guidance on when to update these revision numbers,
|
||||
// please refer to the register map documentation accordingly:
|
||||
// <li> Current version: @.VERSIONING_REGS_REGMAP..CURRENT_VERSION
|
||||
// <li> Oldest compatible version: @.VERSIONING_REGS_REGMAP..OLDEST_COMPATIBLE_VERSION
|
||||
// <li> Version last modified: @.VERSIONING_REGS_REGMAP..VERSION_LAST_MODIFIED
|
||||
// </info>
|
||||
// <value name="DB_GPIO_IFC_CURRENT_VERSION_MAJOR" integer="1"/>
|
||||
// <value name="DB_GPIO_IFC_CURRENT_VERSION_MINOR" integer="0"/>
|
||||
// <value name="DB_GPIO_IFC_CURRENT_VERSION_BUILD" integer="0"/>
|
||||
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MAJOR" integer="1"/>
|
||||
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_MINOR" integer="0"/>
|
||||
// <value name="DB_GPIO_IFC_OLDEST_COMPATIBLE_VERSION_BUILD" integer="0"/>
|
||||
// <value name="DB_GPIO_IFC_VERSION_LAST_MODIFIED_TIME" integer="0x20110616"/>
|
||||
// </enumeratedtype>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
@@ -0,0 +1,108 @@
|
||||
//
|
||||
// Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: db_gpio_reordering
|
||||
//
|
||||
// Description:
|
||||
// Reorders the GPIO wires towards the DB CPLDs in a common way for DB 0 and 1.
|
||||
//
|
||||
// The digital daughterboard connector has 120 pins [A-F][1-20].
|
||||
// The numbering on the motherboard traces do not match for daughterboard 0 and 1.
|
||||
// This module orders the FPGA outputs MSB first and connects it to the DB
|
||||
// connection with increasing letter and increasing number.
|
||||
// For DB 0 this results in:
|
||||
// FPGA Bit 19 = A7 (trace: DB0/1_GPIO[19])
|
||||
// FPGA Bit 18 = A8 (trace: DB0/1_GPIO[17])
|
||||
// ...
|
||||
// FPGA Bit 0 = C19 (trace: DB0/1_GPIO[12])
|
||||
// This enables usages of the same daughterboard CPLD image on both connectors.
|
||||
//
|
||||
|
||||
`default_nettype none
|
||||
|
||||
module db_gpio_reordering (
|
||||
// 20 bit internal interface
|
||||
output wire [19:0] db0_gpio_in_int,
|
||||
input wire [19:0] db0_gpio_out_int,
|
||||
input wire [19:0] db0_gpio_out_en_int,
|
||||
output wire [19:0] db1_gpio_in_int,
|
||||
input wire [19:0] db1_gpio_out_int,
|
||||
input wire [19:0] db1_gpio_out_en_int,
|
||||
|
||||
// 20 bit external interface
|
||||
input wire [19:0] db0_gpio_in_ext,
|
||||
output wire [19:0] db0_gpio_out_ext,
|
||||
output wire [19:0] db0_gpio_out_en_ext,
|
||||
input wire [19:0] db1_gpio_in_ext,
|
||||
output wire [19:0] db1_gpio_out_ext,
|
||||
output wire [19:0] db1_gpio_out_en_ext
|
||||
);
|
||||
|
||||
//port indexes
|
||||
localparam ENTRY_BITWIDTH = 5;
|
||||
localparam NUM_ENTRIES = 20;
|
||||
localparam [ENTRY_BITWIDTH*NUM_ENTRIES-1:0] PORT0_MAPPING = {
|
||||
5'd 19,
|
||||
5'd 17,
|
||||
5'd 0,
|
||||
5'd 14,
|
||||
5'd 15,
|
||||
5'd 10,
|
||||
5'd 4,
|
||||
5'd 5,
|
||||
5'd 16,
|
||||
5'd 18,
|
||||
5'd 8,
|
||||
5'd 6,
|
||||
5'd 1,
|
||||
5'd 9,
|
||||
5'd 2,
|
||||
5'd 3,
|
||||
5'd 11,
|
||||
5'd 7,
|
||||
5'd 13,
|
||||
5'd 12 };
|
||||
localparam [ENTRY_BITWIDTH*NUM_ENTRIES-1:0] PORT1_MAPPING = {
|
||||
5'd 10,
|
||||
5'd 6,
|
||||
5'd 7,
|
||||
5'd 2,
|
||||
5'd 3,
|
||||
5'd 0,
|
||||
5'd 1,
|
||||
5'd 4,
|
||||
5'd 8,
|
||||
5'd 9,
|
||||
5'd 11,
|
||||
5'd 5,
|
||||
5'd 13,
|
||||
5'd 12,
|
||||
5'd 15,
|
||||
5'd 14,
|
||||
5'd 19,
|
||||
5'd 18,
|
||||
5'd 17,
|
||||
5'd 16 };
|
||||
|
||||
// reordering assignments
|
||||
generate
|
||||
genvar i;
|
||||
for (i=0; i<NUM_ENTRIES; i=i+1) begin : reordering_gen
|
||||
// input data
|
||||
assign db0_gpio_in_int[i] = db0_gpio_in_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]];
|
||||
assign db1_gpio_in_int[i] = db1_gpio_in_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]];
|
||||
|
||||
// output data
|
||||
assign db0_gpio_out_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db0_gpio_out_int[i];
|
||||
assign db1_gpio_out_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db1_gpio_out_int[i];
|
||||
|
||||
// output enable
|
||||
assign db0_gpio_out_en_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db0_gpio_out_en_int[i];
|
||||
assign db1_gpio_out_en_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db1_gpio_out_en_int[i];
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
Reference in new issue
Block a user