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fpga: x400: Add support for X410 motherboard FPGA

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Co-authored-by: Andrew Moch <Andrew.Moch@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>
Co-authored-by: Hector Rubio <hrubio@ni.com>


Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
2021-06-10 11:56:58 -05:00
committed by Aaron Rossetto
co-authored by Andrew Moch Daniel Jepson Javier Valenzuela Joerg Hofrichter Kumaran Subramoniam Max Köhler Michael Auchter Paul Butler Hector Rubio
parent bfef20ea45
commit 61782b02d7
205 changed files with 299634 additions and 0 deletions
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top/x400/constraints/pins/qsfp0_0.xdc
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#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# QSFP28 Port 0 (Lane 0) pin constraints for X410.
#
###############################################################################
# Pin constraints for the MGTs (QSFP28 ports)
###############################################################################
# Bank 131 (Quad X0Y4, Lanes X0Y16-X0Y19)
# Lane 0 (X0Y16)
set_property PACKAGE_PIN E38 [get_ports {QSFP0_0_RX_P}]
set_property PACKAGE_PIN E39 [get_ports {QSFP0_0_RX_N}]
set_property PACKAGE_PIN D31 [get_ports {QSFP0_0_TX_P}]
set_property PACKAGE_PIN D32 [get_ports {QSFP0_0_TX_N}]