fpga: x400: Add support for X410 motherboard FPGA
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
co-authored by
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
Andrew Moch
Daniel Jepson
Javier Valenzuela
Joerg Hofrichter
Kumaran Subramoniam
Max Köhler
Michael Auchter
Paul Butler
Hector Rubio
parent
bfef20ea45
commit
61782b02d7
@@ -0,0 +1,192 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP X4XX FPGA Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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##
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##Output:
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## build/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
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## build/usrp_<product>_fpga_<image_type>.dts: Device tree source file
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## build/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
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# Definitions
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# MGT Types from x4xx_mgt_type.vh
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MGT_100GbE = 5
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MGT_Aurora = 3
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MGT_10GbE = 2
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MGT_Disabled = 0
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# For a 4-lane MGT like 100GBE set QSFPx_0=MGT_100GbE and all others to
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# MGT_Disabled. For a 1-lane MGT like 10GbE do not set anything for unused
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# lanes. This ensures something is defined only for the lanes that are used, so
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# that the TX/RX signals are connected. The presence of a define causes TX/RX
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# to be declared, whereas declaring TX/RX on an unused lane will cause an error
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# in bitgen for unconstrained pins after it is optimized out.
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QSFP0_10GBE = QSFP0_0=$(MGT_10GbE)
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QSFP0_4X10GBE = QSFP0_0=$(MGT_10GbE) QSFP0_1=$(MGT_10GbE) QSFP0_2=$(MGT_10GbE) QSFP0_3=$(MGT_10GbE)
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QSFP0_100GBE = QSFP0_0=$(MGT_100GbE) QSFP0_1=$(MGT_Disabled) QSFP0_2=$(MGT_Disabled) QSFP0_3=$(MGT_Disabled)
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QSFP1_10GBE = QSFP1_0=$(MGT_10GbE)
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QSFP1_4X10GBE = QSFP1_0=$(MGT_10GbE) QSFP1_1=$(MGT_10GbE) QSFP1_2=$(MGT_10GbE) QSFP1_3=$(MGT_10GbE)
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QSFP1_100GBE = QSFP1_0=$(MGT_100GbE) QSFP1_1=$(MGT_Disabled) QSFP1_2=$(MGT_Disabled) QSFP1_3=$(MGT_Disabled)
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# Target specific variables
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X410_IP: DEFS = $(QSFP0_10GBE) RFBW_100M=1
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X410_X1_100: DEFS = $(QSFP0_10GBE) RFBW_100M=1
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X410_XG_100: DEFS = $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_100M=1
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X410_X4_100: DEFS = $(QSFP0_4X10GBE) RFBW_100M=1
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X410_X4C_100: DEFS = $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_100M=1 USE_100GBE=1
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X410_CG_100: DEFS = $(QSFP0_100GBE) RFBW_100M=1 USE_100GBE=1
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X410_CG_200: DEFS = $(QSFP0_100GBE) RFBW_200M=1 USE_100GBE=1
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X410_XG_200: DEFS = $(QSFP0_10GBE) $(QSFP1_10GBE) RFBW_200M=1
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X410_X4_200: DEFS = $(QSFP0_4X10GBE) RFBW_200M=1
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X410_X4C_200: DEFS = $(QSFP0_4X10GBE) $(QSFP1_100GBE) RFBW_200M=1 USE_100GBE=1
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X410_C1_400: DEFS = $(QSFP0_100GBE) RFBW_400M=1 USE_100GBE=1
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X410_CG_400: DEFS = $(QSFP0_100GBE) $(QSFP1_100GBE) RFBW_400M=1 USE_100GBE=1
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DEFS += $(OPTIONS)
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# Defaults specific to the various targets:
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X410_100_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_100_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_100_static_router.hex)
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X410_200_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_200_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_200_static_router.hex)
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X410_400_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=x410_400_rfnoc_image_core.v DEFAULT_EDGE_FILE=$(abspath x410_400_static_router.hex)
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# Option to stop after RTL elaboration. Use this flag as a synthesis check.
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ifndef TARGET
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ifdef CHECK
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TARGET = rtl
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else ifdef SYNTH
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TARGET = synth
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else
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TARGET = bin
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endif
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endif
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TOP ?= x4xx
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# vivado_build($1=Device, $2=Definitions)
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vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" $3
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# vivado_build($1=Device, $2=Option)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p build; \
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echo "Exporting bitstream file..."; \
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cp build-$(1)_$(2)/x4xx.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
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echo "Exporting build report..."; \
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cp build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
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echo "Build DONE ... $(1)_$(2)";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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# vivado_ip($1=Device, $2=Definitions)
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vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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##
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##Supported Targets
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##-----------------
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all: X410_X4_200 ##(Default target)
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##X410_X1_100: 10GbE on QSFP0 (Lane 0), 100MHz Bandwidth
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X410_X1_100: build/usrp_x410_fpga_X1_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
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$(call post_build,X410,X1_100)
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##X410_XG_100: 10GbE on QSFP0 (Lane 0) and QSFP1 (Lane 0), 100MHz Bandwidth
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X410_XG_100: build/usrp_x410_fpga_XG_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
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$(call post_build,X410,XG_100)
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##X410_X4_100: 4x10GbE on QSFP0, 100MHz Bandwidth
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X410_X4_100: build/usrp_x410_fpga_X4_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_100_DEFAULTS))
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$(call post_build,X410,X4_100)
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##X410_X4C_100: (EXPERIMENTAL) 4x10GbE on QSFP0, 100GbE on QSFP1, 100MHz Bandwidth
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X410_X4C_100: build/usrp_x410_fpga_X4C_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,X4C_100)
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##X410_CG_100: (EXPERIMENTAL) 100GbE on QSFP0, 100MHz Bandwidth
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X410_CG_100: build/usrp_x410_fpga_CG_100.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,CG_100)
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##X410_XG_200: 10GbE on QSFP0 (Lane 0) and QSFP1 (Lane 0), 200MHz Bandwidth
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X410_XG_200: build/usrp_x410_fpga_XG_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,XG_200)
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##X410_X4_200: 4x10GbE on QSFP0, 200MHz Bandwidth
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X410_X4_200: build/usrp_x410_fpga_X4_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
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$(call post_build,X410,X4_200)
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##X410_X4C_200: (EXPERIMENTAL) 4x10GbE on QSFP0, 100GbE on QSFP1, 200MHz Bandwidth
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X410_X4C_200: build/usrp_x410_fpga_X4C_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,X4C_200)
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##X410_CG_200: (EXPERIMENTAL) 100GbE on QSFP0, 200MHz Bandwidth
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X410_CG_200: build/usrp_x410_fpga_CG_200.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,CG_200)
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##X410_C1_400: (EXPERIMENTAL) 100GbE on QSFP0, 400MHz Bandwidth
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X410_C1_400: build/usrp_x410_fpga_C1_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,C1_400)
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##X410_CG_400: (EXPERIMENTAL) 100GbE on QSFP0 and QSFP1, 400MHz Bandwidth
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X410_CG_400: build/usrp_x410_fpga_CG_400.dts
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$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
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$(call post_build,X410,CG_400)
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X410_IP: ##Build IPs only
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$(call vivado_ip,X410,$(DEFS) X410=1)
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build/%.dts: dts/*.dts dts/*.dtsi
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-mkdir -p build
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tools/parse_versions_for_dts.py \
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--input regmap/versioning_regs_regmap_utils.vh \
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--output dts/x410-version-info.dtsi \
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--components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m
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${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
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$$(python3 tools/get_dts_input.py --target $@)
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf build-X4*
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@rm -rf build
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cleanall: ##Clean up all target and ip build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf build-X4*
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@rm -rf build
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help: ##Show this help message.
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@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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##
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##Supported Options
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##-----------------
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##GUI=1 Launch the build in the Vivado GUI.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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##SYNTH=1 Launch the build but stop after synthesis.
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##TOP=<module> Specify a top module for syntax checking. (Optional. Default is the bitfile top)
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.PHONY: all clean cleanall help
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