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fpga: Add option to build IP only

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Original-commit: adcca0acd995a75fb2dede4d6a86641821e49e3d
This commit is contained in:
Wade Fife
2024-03-15 20:07:28 -05:00
parent a82a2d122e
commit 600df8752c
5 changed files with 25 additions and 10 deletions
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top/x400/Makefile
+5 -2
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@@ -99,10 +99,12 @@ X440_1600_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_d_rfnoc_image_c
# Option to stop after RTL elaboration. Use this flag as a synthesis check.
ifndef TARGET
ifdef CHECK
ifeq ($(CHECK), 1)
TARGET = rtl
else ifdef SYNTH
else ifeq ($(SYNTH), 1)
TARGET = synth
else ifeq ($(IP_ONLY), 1)
TARGET = viv_ip
else
TARGET = bin
endif
@@ -333,6 +335,7 @@ help: ##Show this help message.
##GUI=1 Launch the build in the Vivado GUI.
##PROJECT=1 Save Vivado project file, otherwise it's created in memory.
##CHECK=1 Launch the syntax checker instead of building a bitfile.
##IP_ONLY=1 Launch the build but stop after IP generation.
##SYNTH=1 Launch the build but stop after synthesis.
##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)