From 600df8752c6902dc24e9943c9873e8082553adff Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 6 Mar 2024 15:53:34 -0600 Subject: [PATCH] fpga: Add option to build IP only Original-commit: adcca0acd995a75fb2dede4d6a86641821e49e3d --- top/e31x/Makefile | 7 +++++-- top/e320/Makefile | 7 +++++-- top/n3xx/Makefile | 7 +++++-- top/x300/Makefile | 7 +++++-- top/x400/Makefile | 7 +++++-- 5 files changed, 25 insertions(+), 10 deletions(-) diff --git a/top/e31x/Makefile b/top/e31x/Makefile index 83257a3..ee29661 100644 --- a/top/e31x/Makefile +++ b/top/e31x/Makefile @@ -23,10 +23,12 @@ DEFS += BUILD_SEED=$(BUILD_SEED) # Set build option (check RTL, run synthesis, or do a full build) ifndef TARGET - ifdef CHECK + ifeq ($(CHECK), 1) TARGET = rtl - else ifdef SYNTH + else ifeq ($(SYNTH), 1) TARGET = synth + else ifeq ($(IP_ONLY), 1) + TARGET = viv_ip else TARGET = bin endif @@ -114,6 +116,7 @@ help: ##Show this help message. ##GUI=1 Launch the build in the Vivado GUI. ##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. +##IP_ONLY=1 Launch the build but stop after IP generation. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED= Build seed to used to affect build results. (Default is 0) ##TOP= Specify a top module for syntax checking. (Default is the bitfile top) diff --git a/top/e320/Makefile b/top/e320/Makefile index cf22938..f120456 100644 --- a/top/e320/Makefile +++ b/top/e320/Makefile @@ -26,10 +26,12 @@ AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED) # Set build option (check RTL, run synthesis, or do a full build) ifndef TARGET - ifdef CHECK + ifeq ($(CHECK), 1) TARGET = rtl - else ifdef SYNTH + else ifeq ($(SYNTH), 1) TARGET = synth + else ifeq ($(IP_ONLY), 1) + TARGET = viv_ip else TARGET = bin endif @@ -106,6 +108,7 @@ help: ##Show this help message. ##GUI=1 Launch the build in the Vivado GUI. ##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. +##IP_ONLY=1 Launch the build but stop after IP generation. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED= Build seed to used to affect build results. (Default is 0) ##TOP= Specify a top module for syntax checking. (Default is the bitfile top) diff --git a/top/n3xx/Makefile b/top/n3xx/Makefile index 62b85c3..5525af8 100644 --- a/top/n3xx/Makefile +++ b/top/n3xx/Makefile @@ -49,10 +49,12 @@ N320AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n320_bist_image_core.v) # Set build option (check RTL, run synthesis, or do a full build) ifndef TARGET - ifdef CHECK + ifeq ($(CHECK), 1) TARGET = rtl - else ifdef SYNTH + else ifeq ($(SYNTH), 1) TARGET = synth + else ifeq ($(IP_ONLY), 1) + TARGET = viv_ip else TARGET = bin endif @@ -209,6 +211,7 @@ help: ##Show this help message. ##GUI=1 Launch the build in the Vivado GUI. ##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. +##IP_ONLY=1 Launch the build but stop after IP generation. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED= Build seed to used to affect build results. (Default is 0) ##TOP= Specify a top module for syntax checking. (Default is the bitfile top) diff --git a/top/x300/Makefile b/top/x300/Makefile index 3d974a8..82e1d77 100644 --- a/top/x300/Makefile +++ b/top/x300/Makefile @@ -35,10 +35,12 @@ XA_DEFS=BUILD_10G=1 BUILD_AURORA=1 SFP0_10GBE=1 SFP1_AURORA=1 $(OPTIONS) BUILD_S # Set build option (check RTL, run synthesis, or do a full build) ifndef TARGET - ifdef CHECK + ifeq ($(CHECK), 1) TARGET = rtl - else ifdef SYNTH + else ifeq ($(SYNTH), 1) TARGET = synth + else ifeq ($(IP_ONLY), 1) + TARGET = viv_ip else TARGET = bin endif @@ -155,6 +157,7 @@ help: ##Show this help message. ##GUI=1 Launch the build in the Vivado GUI. ##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. +##IP_ONLY=1 Launch the build but stop after IP generation. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED= Build seed to used to affect build results. (Default is 0) ##TOP= Specify a top module for syntax checking. (Default is the bitfile top) diff --git a/top/x400/Makefile b/top/x400/Makefile index 1bf0d3f..81ea87b 100644 --- a/top/x400/Makefile +++ b/top/x400/Makefile @@ -99,10 +99,12 @@ X440_1600_D_DEFAULTS := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_d_rfnoc_image_c # Option to stop after RTL elaboration. Use this flag as a synthesis check. ifndef TARGET - ifdef CHECK + ifeq ($(CHECK), 1) TARGET = rtl - else ifdef SYNTH + else ifeq ($(SYNTH), 1) TARGET = synth + else ifeq ($(IP_ONLY), 1) + TARGET = viv_ip else TARGET = bin endif @@ -333,6 +335,7 @@ help: ##Show this help message. ##GUI=1 Launch the build in the Vivado GUI. ##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. +##IP_ONLY=1 Launch the build but stop after IP generation. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED= Build seed to used to affect build results. (Default is 0) ##TOP= Specify a top module for syntax checking. (Default is the bitfile top)