fpga: updating b200 and x300 FPGA source code for latest images
Original-commit: 00711ba213dde8aa0a099d2b18d3da0a33e6af79
This commit is contained in:
Ben Hilburn
@@ -16,4 +16,5 @@ IOPORT2_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/io_port2/, \
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./pcie_basic_regs.v \
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./pcie_dma_ctrl.v \
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./data_swapper_64.v \
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./pcie_lossy_samp_gate.v \
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))
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@@ -3,7 +3,10 @@
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//
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module pcie_basic_regs (
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module pcie_basic_regs #(
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parameter SIGNATURE = 32'h0,
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parameter CLK_FREQ = 32'h0
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) (
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input clk,
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input reset,
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@@ -16,8 +19,8 @@ module pcie_basic_regs (
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input [31:0] misc_status
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);
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localparam PCIE_FPGA_SIG_VAL = 32'h58333030; //X300 (ASCII)
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localparam PCIE_FPGA_COUNTER_FREQ = 32'h0A6E49C0; //175MHz
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localparam PCIE_FPGA_SIG_VAL = SIGNATURE;
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localparam PCIE_FPGA_COUNTER_FREQ = CLK_FREQ;
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localparam PCIE_REG_ADDR_MASK = 20'h001FF;
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@@ -35,12 +35,14 @@ module pcie_dma_ctrl #(
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output rego_tvalid,
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input rego_tready,
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output reg [NUM_STREAMS-1:0] set_enabled,
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output reg [NUM_STREAMS-1:0] set_clear,
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output [(NUM_STREAMS*FRAME_SIZE_W)-1:0] set_frame_size,
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output [(NUM_STREAMS*3)-1:0] swap_lanes,
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input [NUM_STREAMS-1:0] packet_stb,
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input [NUM_STREAMS-1:0] sample_stb,
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input [NUM_STREAMS-1:0] stream_busy,
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input [NUM_STREAMS-1:0] stream_err,
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input [ROUTER_SID_W-1:0] rtr_sid,
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@@ -48,7 +50,7 @@ module pcie_dma_ctrl #(
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);
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localparam DMA_REG_GRP_W = 4;
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localparam DMA_CTRL_STATUS_REG = 4'h0; //[RW] R: Stream Error, W: Reset stream
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localparam DMA_CTRL_STATUS_REG = 4'h0; //[RW] R: Stream Status, W: Stream Control
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localparam DMA_FSIZE_REG = 4'h4; //[RW] R: Frame Size, W: Frame Size
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localparam DMA_SAMP_CNT_REG = 4'h8; //[RW] R: Sample Count, W: Reset Count to 0
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localparam DMA_PKT_CNT_REG = 4'hC; //[RW] R: Packet Count, W: Reset Count to 0
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@@ -92,14 +94,15 @@ module pcie_dma_ctrl #(
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if (reset) begin
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frame_size_mem[i] <= DEFAULT_FSIZE;
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set_clear[i] <= 0;
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set_enabled[i] <= 0;
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sw_buf_width_mem[i] <= 1;
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end else if (regi_tready & regi_tvalid & regi_wr) begin
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if (regi_addr == `GET_REG_OFFSET(DMA_CTRL_STATUS_REG, i)) begin
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set_clear[i] <= regi_payload[0]; //DMA_CTRL_STATUS_REG[0] == Clear DMA queues
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set_enabled[i] <= regi_payload[1]; //DMA_CTRL_STATUS_REG[1] == Enable DMA channel
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sw_buf_width_mem[i] <= regi_payload[4]; //DMA_CTRL_STATUS_REG[5:4] == SW Buffer Size (See note above)
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end else if (regi_addr == `GET_REG_OFFSET(DMA_FSIZE_REG, i)) begin
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frame_size_mem[i] <= regi_payload[FRAME_SIZE_W-1:0]; //DMA_FSIZE_REG[14:0] == DMA Frame size
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set_clear[i] <= 1;
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end
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end else begin
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set_clear[i] <= 0; //set_clear should be "self-clearing"
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@@ -131,14 +134,14 @@ module pcie_dma_ctrl #(
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(regi_addr[DMA_REG_GRP_W-1:0] == DMA_PKT_CNT_REG) ? pkt_count_mem[`EXTRACT_CHAN_NUM(regi_addr)] : (
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(regi_addr[DMA_REG_GRP_W-1:0] == DMA_SAMP_CNT_REG) ? samp_count_mem[`EXTRACT_CHAN_NUM(regi_addr)] : (
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(regi_addr[DMA_REG_GRP_W-1:0] == DMA_FSIZE_REG) ? frame_size_mem[`EXTRACT_CHAN_NUM(regi_addr)] : (
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(regi_addr[DMA_REG_GRP_W-1:0] == DMA_CTRL_STATUS_REG) ? {31'h0, stream_err[`EXTRACT_CHAN_NUM(regi_addr)]} : (
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(regi_addr[DMA_REG_GRP_W-1:0] == DMA_CTRL_STATUS_REG) ? {30'h0, stream_busy[`EXTRACT_CHAN_NUM(regi_addr)], stream_err[`EXTRACT_CHAN_NUM(regi_addr)]} : (
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32'hFFFFFFFF))));
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assign rego_tvalid = regi_tvalid && regi_rd;
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assign regi_tready = rego_tready || (regi_tvalid && regi_wr);
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//Optional router
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if (ENABLE_ROUTER == 1) begin
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generate if (ENABLE_ROUTER == 1) begin
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pcie_pkt_route_specifier #(
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.BASE_ADDR((1<<ROUTER_SID_W) + REG_BASE_ADDR), .ADDR_MASK(20'hFFFFF^((1<<ROUTER_SID_W)-1)),
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.SID_WIDTH(ROUTER_SID_W), .DST_WIDTH(ROUTER_DST_W)
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@@ -147,7 +150,7 @@ module pcie_dma_ctrl #(
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.regi_tdata(regi_tdata), .regi_tvalid(regi_tvalid), .regi_tready(),
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.local_sid(rtr_sid), .fifo_dst(rtr_dst)
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);
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end
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end endgenerate
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endmodule
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@@ -0,0 +1,26 @@
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//
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// Copyright 2013 Ettus Research LLC
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//
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module pcie_lossy_samp_gate
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(
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input [63:0] i_tdata,
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input i_tvalid,
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output i_tready,
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output [63:0] o_tdata,
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output o_tvalid,
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input o_tready,
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input drop,
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output dropping
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);
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assign o_tdata = i_tdata;
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assign o_tvalid = i_tvalid & ~drop;
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assign i_tready = o_tready | drop;
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assign dropping = drop & i_tvalid;
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endmodule // pcie_lossy_samp_gate
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@@ -344,9 +344,9 @@ module eth_dispatch
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is_icmp_no_fwd <= 0;
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is_chdr <= 1'b0;
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// space_in_fifo <= 0;
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// is_there_fifo_space <= 1;
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// packet_length <= 0;
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//space_in_fifo <= 0;
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//is_there_fifo_space <= 1;
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//packet_length <= 0;
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end else if (in_tvalid && in_tready) begin // if (reset || clear)
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in_tdata_reg <= in_tdata;
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@@ -446,7 +446,6 @@ module eth_dispatch
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assign in_tready = (state == WAIT_PACKET) ||
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(state == READ_HEADER) ||
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(state == DROP_PACKET) ||
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(out_tready && fwd_input);
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@@ -58,14 +58,14 @@ module new_tx_control
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localparam ST_ERROR = 3;
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localparam ST_WAIT = 4;
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reg [11:0] expected_seqnum;
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wire [63:0] CODE_EOB_ACK = {32'd1,20'd0,seqnum};
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wire [63:0] CODE_UNDERRUN = {32'd2,20'd0,seqnum};
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wire [63:0] CODE_SEQ_ERROR = {32'd4,20'd0,seqnum};
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wire [63:0] CODE_SEQ_ERROR = {32'd4,4'd0,expected_seqnum,4'd0,seqnum};
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wire [63:0] CODE_TIME_ERROR = {32'd8,20'd0,seqnum};
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wire [63:0] CODE_UNDERRUN_MIDPKT = {32'd16,20'd0,seqnum};
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wire [63:0] CODE_SEQ_ERROR_MIDBURST = {32'd32,20'd0,seqnum};
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reg [11:0] expected_seqnum;
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wire [63:0] CODE_SEQ_ERROR_MIDBURST = {32'd32,4'd0,expected_seqnum,4'd0,seqnum};
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always @(posedge clk)
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if(reset | clear | clear_seqnum)
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,25 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<DARoots Version="1" Minor="26">
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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<Filter Type="Constrs"/>
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<File Path="$PSRCDIR/constrs_1/imports/b200/b200.ucf">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../b200.ucf"/>
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<Attr Name="ImportTime" Val="1358988004"/>
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<Attr Name="UsedInSynthesis" Val="1"/>
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<Attr Name="UsedInImplementation" Val="1"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/constrs_1/imports/b200/timing.ucf">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../timing.ucf"/>
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<Attr Name="ImportTime" Val="1359506480"/>
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<Attr Name="UsedInSynthesis" Val="1"/>
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<Attr Name="UsedInImplementation" Val="1"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="ConstrsType" Val="UCF"/>
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</Config>
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</FileSet>
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</DARoots>
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@@ -0,0 +1,20 @@
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<?xml version="1.0"?>
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<Strategy Version="1" Minor="2">
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<StratHandle Name="ISE Defaults" Flow="ISE14">
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<Desc>ISE Defaults, including packing registers in IOs off</Desc>
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</StratHandle>
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<Step Id="ngdbuild">
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</Step>
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<Step Id="map">
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<Option Id="FFPackEnum">3</Option>
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</Step>
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<Step Id="par">
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</Step>
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<Step Id="trce">
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</Step>
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<Step Id="xdl">
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</Step>
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<Step Id="bitgen">
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</Step>
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</Strategy>
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@@ -0,0 +1,25 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<DARoots Version="1" Minor="26">
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<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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<Filter Type="Constrs"/>
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<File Path="$PSRCDIR/constrs_1/imports/b200/b200.ucf">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../b200.ucf"/>
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<Attr Name="ImportTime" Val="1358988004"/>
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<Attr Name="UsedInSynthesis" Val="1"/>
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<Attr Name="UsedInImplementation" Val="1"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/constrs_1/imports/b200/timing.ucf">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../timing.ucf"/>
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||||
<Attr Name="ImportTime" Val="1359506480"/>
|
||||
<Attr Name="UsedInSynthesis" Val="1"/>
|
||||
<Attr Name="UsedInImplementation" Val="1"/>
|
||||
</FileInfo>
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</File>
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<Config>
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<Option Name="ConstrsType" Val="UCF"/>
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</Config>
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</FileSet>
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</DARoots>
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@@ -0,0 +1,20 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<DARoots Version="1" Minor="26">
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<FileSet Name="constrs_out" Type="Constrs" RelSrcDir="$PRUNDIR/impl_1/.constrs">
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<File Path="$PRUNDIR/impl_1/.constrs/b200.ucf">
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<FileInfo>
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<Attr Name="UsedInSynthesis" Val="1"/>
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<Attr Name="UsedInImplementation" Val="1"/>
|
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</FileInfo>
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</File>
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<File Path="$PRUNDIR/impl_1/.constrs/timing.ucf">
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<FileInfo>
|
||||
<Attr Name="UsedInSynthesis" Val="1"/>
|
||||
<Attr Name="UsedInImplementation" Val="1"/>
|
||||
</FileInfo>
|
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</File>
|
||||
<Config>
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<Option Name="ConstrsType" Val="UCF"/>
|
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</Config>
|
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</FileSet>
|
||||
</DARoots>
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@@ -0,0 +1,20 @@
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<?xml version="1.0"?>
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<Strategy Version="1" Minor="2">
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||||
<StratHandle Name="ISE Defaults" Flow="ISE14">
|
||||
<Desc>ISE Defaults, including packing registers in IOs off</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="ngdbuild">
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</Step>
|
||||
<Step Id="map">
|
||||
<Option Id="FFPackEnum">3</Option>
|
||||
</Step>
|
||||
<Step Id="par">
|
||||
</Step>
|
||||
<Step Id="trce">
|
||||
</Step>
|
||||
<Step Id="xdl">
|
||||
</Step>
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||||
<Step Id="bitgen">
|
||||
</Step>
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</Strategy>
|
||||
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@@ -0,0 +1,18 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<DARoots Version="1" Minor="26">
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/imports/build/b200.ngc">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../build/b200.ngc"/>
|
||||
<Attr Name="ImportTime" Val="1359508205"/>
|
||||
<Attr Name="UsedInSynthesis" Val="1"/>
|
||||
<Attr Name="UsedInImplementation" Val="1"/>
|
||||
</FileInfo>
|
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="b200"/>
|
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</Config>
|
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</FileSet>
|
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</DARoots>
|
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@@ -0,0 +1,30 @@
|
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<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="8">
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx75fgg484-3" LaunchPart="xc6slx75fgg484-3" ConstrsSet="constrs_1" Description="Imported on Tue Jan 29 17:25:57 2013" State="current" Dir="$PRUNDIR/impl_1" LaunchTime="1359509156" Reconstructed="TRUE">
|
||||
<File Type="MAP-PSR" Name="b200.psr"/>
|
||||
<File Type="PA-EDIF" Name="b200.edf"/>
|
||||
<File Type="PAR-NCD" Name="b200.ncd"/>
|
||||
<File Type="PA-UCF" Name="b200.ucf"/>
|
||||
<File Type="PAR-PAD" Name="b200_routed_pad.txt"/>
|
||||
<File Type="PAR-PAR" Name="b200_routed.par"/>
|
||||
<File Type="PAR-UNR" Name="b200_routed.unroutes"/>
|
||||
<File Type="BG-BIT" Name="b200.bit"/>
|
||||
<File Type="BG-DRC" Name="b200.drc"/>
|
||||
<File Type="PA-CONSTRSDIR" Name=".constrs"/>
|
||||
<File Type="BG-BGN" Name="b200.bgn"/>
|
||||
<File Type="TRCE-TWR" Name="b200.twr"/>
|
||||
<File Type="TRCE-TWX" Name="b200.twx"/>
|
||||
<File Type="XDL-XDL" Name="b200.xdl"/>
|
||||
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
|
||||
<File Type="WBT-LOG" Name="webtalk.log"/>
|
||||
<File Type="RUN-SRCS" Name="$PDATADIR/runs/impl_1/sources.xml"/>
|
||||
<File Type="RUN-CONSTRS" Name="$PDATADIR/runs/impl_1/constrs_in.xml"/>
|
||||
<File Type="RUN-STRAT" Name="$PDATADIR/runs/impl_1/impl_1.psg"/>
|
||||
<File Type="NGDB-NGD" Name="b200.ngd"/>
|
||||
<File Type="NGDB-BLD" Name="b200.bld"/>
|
||||
<File Type="MAP-NCD" Name="b200.ncd"/>
|
||||
<File Type="MAP-MRP" Name="b200.mrp"/>
|
||||
<File Type="MAP-MAP" Name="b200.map"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DARoots Version="1" Minor="26">
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</DARoots>
|
||||
@@ -0,0 +1,26 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DARoots Version="1" Minor="26">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/imports/build/b200.ngc">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../build/b200.ngc"/>
|
||||
<Attr Name="ImportTime" Val="1359508205"/>
|
||||
<Attr Name="UsedInSynthesis" Val="1"/>
|
||||
<Attr Name="UsedInImplementation" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/imports/coregen/fifo_4k_2clk.ngc">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../coregen/fifo_4k_2clk.ngc"/>
|
||||
<Attr Name="ImportTime" Val="1359144134"/>
|
||||
<Attr Name="UsedInSynthesis" Val="1"/>
|
||||
<Attr Name="UsedInImplementation" Val="1"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="GateLvl"/>
|
||||
<Option Name="TopModule" Val="b200"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</DARoots>
|
||||
@@ -0,0 +1,12 @@
|
||||
version:1
|
||||
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464737263:31:00:00
|
||||
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697466696e64:32:00:00
|
||||
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697470726f70657274696573:31:00:00
|
||||
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:66696c6565786974:31:00:00
|
||||
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00
|
||||
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f67676c657a6f6f6d617265616d6f6465:32:00:00
|
||||
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:766965777461736b696d706c656d656e746174696f6e:31:00:00
|
||||
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d666974:31:00:00
|
||||
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d696e:3133:00:00
|
||||
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d6f7574:3137:00:00
|
||||
eof:1108508211
|
||||
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:1
|
||||
eof:
|
||||
@@ -0,0 +1,38 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Tue Jan 29 17:42:17 2013">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="a2486f6b8cdf4e77be535de080ad1097" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="GateLvl" type="DesignMode"/>
|
||||
<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddSrc" value="1" type="JavaHandler"/>
|
||||
<property name="EditFind" value="2" type="JavaHandler"/>
|
||||
<property name="EditProperties" value="1" type="JavaHandler"/>
|
||||
<property name="FileExit" value="1" type="JavaHandler"/>
|
||||
<property name="NewProject" value="1" type="JavaHandler"/>
|
||||
<property name="ToggleZoomAreaMode" value="2" type="JavaHandler"/>
|
||||
<property name="ViewTaskImplementation" value="1" type="JavaHandler"/>
|
||||
<property name="ZoomFit" value="1" type="JavaHandler"/>
|
||||
<property name="ZoomIn" value="13" type="JavaHandler"/>
|
||||
<property name="ZoomOut" value="17" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="1" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="0" type="TclMode"/>
|
||||
<property name="ISEMode" value="0" type="ISEMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
@@ -0,0 +1,28 @@
|
||||
<?xml version="1.0"?>
|
||||
<!--Product Version: PlanAhead v14.4 (64-bit)-->
|
||||
<Project Version="4" Minor="36">
|
||||
<FileSet Dir="sources_1" File="fileset.xml"/>
|
||||
<FileSet Dir="constrs_1" File="fileset.xml"/>
|
||||
<FileSet Dir="sim_1" File="fileset.xml"/>
|
||||
<RunSet Dir="runs" File="runs.xml"/>
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<DefaultPromote Dir="$PROMOTEDIR"/>
|
||||
<Config>
|
||||
<Option Name="Id" Val="0f51201731ac4b37b508a9b552ac0aac"/>
|
||||
<Option Name="Part" Val="xc6slx75fgg484-3"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="TargetLanguage" Val="Verilog"/>
|
||||
<Option Name="TargetSimulator" Val="ISim"/>
|
||||
<Option Name="Board" Val=""/>
|
||||
<Option Name="SourceMgmtMode" Val="All"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="CxlOverwriteLibs" Val="1"/>
|
||||
<Option Name="CxlFuncsim" Val="1"/>
|
||||
<Option Name="CxlTimesim" Val="1"/>
|
||||
<Option Name="CxlCore" Val="1"/>
|
||||
<Option Name="CxlEdk" Val="0"/>
|
||||
<Option Name="CxlExcludeCores" Val="1"/>
|
||||
<Option Name="CxlExcludeSubLibs" Val="0"/>
|
||||
</Config>
|
||||
</Project>
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
@echo off
|
||||
|
||||
rem PlanAhead(TM)
|
||||
rem launch.bat: a PlanAhead-generated ExploreAhead Script
|
||||
rem Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
setlocal
|
||||
|
||||
set HD_LDIR=%~dp0
|
||||
|
||||
rem *** Create Queue Clues
|
||||
set HD_RUNDIR=%HD_LDIR%\../impl_1
|
||||
if exist "%HD_RUNDIR%" echo. > "%HD_RUNDIR%/.ISE.queue.rst"
|
||||
|
||||
|
||||
rem *** Launch Runs (one at a time)
|
||||
set HD_RUNBAT=%HD_LDIR%\../impl_1\runme.bat
|
||||
if exist "%HD_RUNBAT%" call "%HD_RUNBAT%" %*
|
||||
|
||||
|
||||
+26
@@ -0,0 +1,26 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# PlanAhead(TM)
|
||||
# launch.sh: a PlanAhead-generated ExploreAhead Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LDIR=`dirname "$0"`
|
||||
|
||||
# *** Create Queue Clues
|
||||
HD_RUNDIR="$HD_LDIR/../impl_1"
|
||||
if [ -d "$HD_RUNDIR" ]
|
||||
then
|
||||
/bin/touch "$HD_RUNDIR/.ISE.queue.rst"
|
||||
fi
|
||||
|
||||
|
||||
# *** Launch Runs (one at a time)
|
||||
HD_RUNSH="$HD_LDIR/../impl_1/runme.sh"
|
||||
if [ -f "$HD_RUNSH" ]
|
||||
then
|
||||
"$HD_RUNSH"
|
||||
fi
|
||||
|
||||
|
||||
@@ -0,0 +1,317 @@
|
||||
## SPI Nets
|
||||
|
||||
NET "cat_ce" LOC = Y1;
|
||||
NET "cat_ce" IOSTANDARD = LVCMOS18;
|
||||
NET "cat_miso" LOC = V1;
|
||||
NET "cat_miso" IOSTANDARD = LVCMOS18;
|
||||
NET "cat_mosi" LOC = T4;
|
||||
NET "cat_mosi" IOSTANDARD = LVCMOS18;
|
||||
NET "cat_sclk" LOC = P7;
|
||||
NET "cat_sclk" IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "fx3_ce" LOC = H20;
|
||||
NET "fx3_miso" LOC = G20;
|
||||
NET "fx3_mosi" LOC = AA20;
|
||||
NET "fx3_sclk" LOC = Y21;
|
||||
|
||||
NET "pll_ce" LOC = W11;
|
||||
NET "pll_mosi" LOC = AB11;
|
||||
NET "pll_sclk" LOC = Y12;
|
||||
|
||||
NET "FPGA_RXD0" LOC = AB8;
|
||||
NET "FPGA_TXD0" LOC = AB7;
|
||||
|
||||
NET "SCL_FPGA" LOC = P21;
|
||||
NET "SDA_FPGA" LOC = W22;
|
||||
|
||||
## Catalina Controls
|
||||
|
||||
NET "codec_enable" LOC = J6;
|
||||
NET "codec_enable" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_en_agc" LOC = P6;
|
||||
NET "codec_en_agc" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_reset" LOC = Y2;
|
||||
NET "codec_reset" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_sync" LOC = M3;
|
||||
NET "codec_sync" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_txrx" LOC = M7;
|
||||
NET "codec_txrx" IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "codec_ctrl_in[0]" LOC = E3;
|
||||
NET "codec_ctrl_in[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in[1]" LOC = F2;
|
||||
NET "codec_ctrl_in[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in[2]" LOC = F1;
|
||||
NET "codec_ctrl_in[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in[3]" LOC = E1;
|
||||
NET "codec_ctrl_in[3]" IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "codec_ctrl_out[0]" LOC = D1;
|
||||
NET "codec_ctrl_out[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[1]" LOC = C1;
|
||||
NET "codec_ctrl_out[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[2]" LOC = H3;
|
||||
NET "codec_ctrl_out[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[3]" LOC = F3;
|
||||
NET "codec_ctrl_out[3]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[4]" LOC = P1;
|
||||
NET "codec_ctrl_out[4]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[5]" LOC = J1;
|
||||
NET "codec_ctrl_out[5]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[6]" LOC = B1;
|
||||
NET "codec_ctrl_out[6]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[7]" LOC = H2;
|
||||
NET "codec_ctrl_out[7]" IOSTANDARD = LVCMOS18;
|
||||
|
||||
## Catalina Data RX
|
||||
|
||||
NET "rx_codec_d[0]" LOC = T2;
|
||||
NET "rx_codec_d[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[0]" DRIVE = 4;
|
||||
NET "rx_codec_d[1]" LOC = R1;
|
||||
NET "rx_codec_d[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[1]" DRIVE = 4;
|
||||
NET "rx_codec_d[2]" LOC = V2;
|
||||
NET "rx_codec_d[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[2]" DRIVE = 4;
|
||||
NET "rx_codec_d[3]" LOC = N1;
|
||||
NET "rx_codec_d[3]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[3]" DRIVE = 4;
|
||||
NET "rx_codec_d[4]" LOC = V3;
|
||||
NET "rx_codec_d[4]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[4]" DRIVE = 4;
|
||||
NET "rx_codec_d[5]" LOC = T1;
|
||||
NET "rx_codec_d[5]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[5]" DRIVE = 4;
|
||||
NET "rx_codec_d[6]" LOC = W1;
|
||||
NET "rx_codec_d[6]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[6]" DRIVE = 4;
|
||||
NET "rx_codec_d[7]" LOC = U1;
|
||||
NET "rx_codec_d[7]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[7]" DRIVE = 4;
|
||||
NET "rx_codec_d[8]" LOC = W3;
|
||||
NET "rx_codec_d[8]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[8]" DRIVE = 4;
|
||||
NET "rx_codec_d[9]" LOC = U3;
|
||||
NET "rx_codec_d[9]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[9]" DRIVE = 4;
|
||||
NET "rx_codec_d[10]" LOC = P2;
|
||||
NET "rx_codec_d[10]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[10]" DRIVE = 4;
|
||||
NET "rx_codec_d[11]" LOC = R3;
|
||||
NET "rx_codec_d[11]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[11]" DRIVE = 4;
|
||||
|
||||
## Catalina Data TX
|
||||
|
||||
NET "tx_codec_d[0]" LOC = M1;
|
||||
NET "tx_codec_d[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[0]" DRIVE = 4;
|
||||
NET "tx_codec_d[1]" LOC = K1;
|
||||
NET "tx_codec_d[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[1]" DRIVE = 4;
|
||||
NET "tx_codec_d[2]" LOC = L3;
|
||||
NET "tx_codec_d[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[2]" DRIVE = 4;
|
||||
NET "tx_codec_d[3]" LOC = K2;
|
||||
NET "tx_codec_d[3]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[3]" DRIVE = 4;
|
||||
NET "tx_codec_d[4]" LOC = M4;
|
||||
NET "tx_codec_d[4]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[4]" DRIVE = 4;
|
||||
NET "tx_codec_d[5]" LOC = J4;
|
||||
NET "tx_codec_d[5]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[5]" DRIVE = 4;
|
||||
NET "tx_codec_d[6]" LOC = L4;
|
||||
NET "tx_codec_d[6]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[6]" DRIVE = 4;
|
||||
NET "tx_codec_d[7]" LOC = H1;
|
||||
NET "tx_codec_d[7]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[7]" DRIVE = 4;
|
||||
NET "tx_codec_d[8]" LOC = M2;
|
||||
NET "tx_codec_d[8]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[8]" DRIVE = 4;
|
||||
NET "tx_codec_d[9]" LOC = G1;
|
||||
NET "tx_codec_d[9]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[9]" DRIVE = 4;
|
||||
NET "tx_codec_d[10]" LOC = N3;
|
||||
NET "tx_codec_d[10]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[10]" DRIVE = 4;
|
||||
NET "tx_codec_d[11]" LOC = G3;
|
||||
NET "tx_codec_d[11]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[11]" DRIVE = 4;
|
||||
|
||||
## Catalina Clocks
|
||||
|
||||
NET "cat_clkout_fpga" LOC = J3;
|
||||
NET "cat_clkout_fpga" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_data_clk_p" LOC = K3;
|
||||
NET "codec_data_clk_p" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_fb_clk_p" LOC = P3;
|
||||
NET "codec_fb_clk_p" IOSTANDARD = LVCMOS18;
|
||||
# | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_main_clk_p" LOC = K5;
|
||||
# | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_main_clk_n" LOC = K4;
|
||||
|
||||
NET "rx_frame_p" LOC = U4;
|
||||
NET "rx_frame_p" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_frame_p" LOC = T3;
|
||||
NET "tx_frame_p" IOSTANDARD = LVCMOS18;
|
||||
|
||||
## Debug Bus
|
||||
|
||||
NET "debug[0]" LOC = C14;
|
||||
NET "debug[1]" LOC = F15;
|
||||
NET "debug[2]" LOC = A18;
|
||||
NET "debug[3]" LOC = A17;
|
||||
NET "debug[4]" LOC = E14;
|
||||
NET "debug[5]" LOC = G13;
|
||||
NET "debug[6]" LOC = D13;
|
||||
NET "debug[7]" LOC = F13;
|
||||
NET "debug[8]" LOC = D8;
|
||||
NET "debug[9]" LOC = A6;
|
||||
NET "debug[10]" LOC = D7;
|
||||
NET "debug[11]" LOC = A5;
|
||||
NET "debug[12]" LOC = B6;
|
||||
NET "debug[13]" LOC = A3;
|
||||
NET "debug[14]" LOC = A7;
|
||||
NET "debug[15]" LOC = A8;
|
||||
NET "debug[16]" LOC = B18;
|
||||
NET "debug[17]" LOC = C17;
|
||||
NET "debug[18]" LOC = H13;
|
||||
NET "debug[19]" LOC = D12;
|
||||
NET "debug[20]" LOC = H14;
|
||||
NET "debug[21]" LOC = C10;
|
||||
NET "debug[22]" LOC = D10;
|
||||
NET "debug[23]" LOC = C8;
|
||||
NET "debug[24]" LOC = D9;
|
||||
NET "debug[25]" LOC = C5;
|
||||
NET "debug[26]" LOC = A9;
|
||||
NET "debug[27]" LOC = B8;
|
||||
NET "debug[28]" LOC = A4;
|
||||
NET "debug[29]" LOC = C7;
|
||||
NET "debug[30]" LOC = C6;
|
||||
NET "debug[31]" LOC = D6;
|
||||
|
||||
NET "debug_clk[0]" LOC = A12;
|
||||
NET "debug_clk[1]" LOC = C12;
|
||||
|
||||
## GPIF
|
||||
|
||||
NET "IFCLK" LOC = H21;
|
||||
NET "FX3_EXTINT" LOC = U20;
|
||||
|
||||
NET "GPIF_CTL0" LOC = V20;
|
||||
NET "GPIF_CTL1" LOC = T22;
|
||||
NET "GPIF_CTL2" LOC = R22;
|
||||
NET "GPIF_CTL3" LOC = U22;
|
||||
NET "GPIF_CTL4" LOC = P19;
|
||||
NET "GPIF_CTL5" LOC = N22;
|
||||
NET "GPIF_CTL6" LOC = T21;
|
||||
NET "GPIF_CTL7" LOC = V21;
|
||||
NET "GPIF_CTL8" LOC = K18;
|
||||
NET "GPIF_CTL9" LOC = R20;
|
||||
##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
|
||||
NET "GPIF_CTL11" LOC = P22;
|
||||
NET "GPIF_CTL12" LOC = M20;
|
||||
|
||||
NET "GPIF_D[0]" LOC = T17;
|
||||
NET "GPIF_D[1]" LOC = U14;
|
||||
NET "GPIF_D[2]" LOC = U13;
|
||||
NET "GPIF_D[3]" LOC = AA6;
|
||||
NET "GPIF_D[4]" LOC = AB6;
|
||||
NET "GPIF_D[5]" LOC = Y3;
|
||||
NET "GPIF_D[6]" LOC = AB3;
|
||||
NET "GPIF_D[7]" LOC = AA4;
|
||||
NET "GPIF_D[8]" LOC = AA2;
|
||||
NET "GPIF_D[9]" LOC = AB2;
|
||||
NET "GPIF_D[10]" LOC = AB19;
|
||||
NET "GPIF_D[11]" LOC = AA18;
|
||||
NET "GPIF_D[12]" LOC = AB18;
|
||||
NET "GPIF_D[13]" LOC = Y13;
|
||||
NET "GPIF_D[14]" LOC = AA12;
|
||||
NET "GPIF_D[15]" LOC = AB12;
|
||||
NET "GPIF_D[16]" LOC = N20;
|
||||
NET "GPIF_D[17]" LOC = L20;
|
||||
NET "GPIF_D[18]" LOC = N19;
|
||||
NET "GPIF_D[19]" LOC = M22;
|
||||
NET "GPIF_D[20]" LOC = L19;
|
||||
NET "GPIF_D[21]" LOC = M21;
|
||||
NET "GPIF_D[22]" LOC = M19;
|
||||
NET "GPIF_D[23]" LOC = K22;
|
||||
NET "GPIF_D[24]" LOC = J20;
|
||||
NET "GPIF_D[25]" LOC = L22;
|
||||
NET "GPIF_D[26]" LOC = K19;
|
||||
NET "GPIF_D[27]" LOC = H22;
|
||||
NET "GPIF_D[28]" LOC = J22;
|
||||
NET "GPIF_D[29]" LOC = K20;
|
||||
NET "GPIF_D[30]" LOC = G22;
|
||||
NET "GPIF_D[31]" LOC = F22;
|
||||
|
||||
## GPS
|
||||
|
||||
NET "gps_lock" LOC = Y17;
|
||||
NET "gps_out_enable" LOC = V22;
|
||||
NET "gps_ref_enable" LOC = AB13;
|
||||
NET "gps_rxd" LOC = AB14;
|
||||
NET "gps_txd" LOC = W12;
|
||||
NET "gps_txd_nmea" LOC = AA14;
|
||||
|
||||
## LEDS
|
||||
|
||||
NET "LED_RX1" LOC = C22;
|
||||
NET "LED_RX2" LOC = L15;
|
||||
NET "LED_TXRX1_TX" LOC = C20;
|
||||
NET "LED_TXRX2_RX" LOC = D21;
|
||||
NET "LED_TXRX1_RX" LOC = K16;
|
||||
NET "LED_TXRX2_TX" LOC = D22;
|
||||
|
||||
## Misc Hardware Control
|
||||
|
||||
NET "ext_ref_enable" LOC = Y15;
|
||||
NET "pll_lock" LOC = AB10;
|
||||
NET "AUX_PWR_ON" LOC = AA21;
|
||||
#NET "RFUSE" LOC = "P15" ;
|
||||
|
||||
## PPS
|
||||
|
||||
NET "pps_fpga_out_enable" LOC = AB15;
|
||||
NET "PPS_IN_EXT" LOC = AB16;
|
||||
NET "PPS_IN_INT" LOC = AB21;
|
||||
NET "pps_out" LOC = AB17;
|
||||
|
||||
## RF Hardware Control
|
||||
|
||||
NET "SFDX1_RX" LOC = W4;
|
||||
NET "SFDX1_TX" LOC = T18;
|
||||
NET "SFDX2_RX" LOC = F18;
|
||||
NET "SFDX2_TX" LOC = H17;
|
||||
NET "SRX1_RX" LOC = Y7;
|
||||
NET "SRX1_TX" LOC = AA8;
|
||||
NET "SRX2_RX" LOC = J17;
|
||||
NET "SRX2_TX" LOC = F19;
|
||||
NET "tx_bandsel_a" LOC = N16;
|
||||
NET "tx_bandsel_b" LOC = M16;
|
||||
NET "tx_enable1" LOC = Y4;
|
||||
NET "tx_enable2" LOC = R19;
|
||||
NET "rx_bandsel_a" LOC = T20;
|
||||
NET "rx_bandsel_b" LOC = U19;
|
||||
NET "rx_bandsel_c" LOC = P20;
|
||||
|
||||
## FPGA Config Pins
|
||||
|
||||
#NET "FPGA_CFG_INIT_B" LOC = "T6" ;
|
||||
#NET "FPGA_CFG_DONE" LOC = "Y22" ;
|
||||
#NET "FPGA_CFG_M0" LOC = "AA22" ;
|
||||
#NET "FPGA_CFG_M1" LOC = "U15" ;
|
||||
#NET "FPGA_CFG_PROG_B" LOC = "AA1" ;
|
||||
|
||||
## Special Pins
|
||||
|
||||
#NET "VFS" LOC = "P16" ;
|
||||
#NET "TMS" LOC = "C18" ;
|
||||
#NET "TDO" LOC = "A19" ;
|
||||
#NET "TDI" LOC = "E18" ;
|
||||
#NET "TCK" LOC = "G15" ;
|
||||
#NET "GND" LOC = "N15" ;
|
||||
@@ -0,0 +1,85 @@
|
||||
|
||||
# codec_main_clk is 40 MHz main tcxo clock
|
||||
NET "codec_main_clk*" TNM_NET = "codec_main_clk";
|
||||
TIMESPEC TS_codec_main_clk = PERIOD "codec_main_clk" 25000 ps HIGH 50 %;
|
||||
|
||||
|
||||
# IFCLK is 100 MHz GPIF clock
|
||||
NET "IFCLK" TNM_NET = "IFCLK";
|
||||
TIMESPEC TS_IFCLK = PERIOD "IFCLK" 10000 ps HIGH 50 %;
|
||||
|
||||
|
||||
# codec_data_clk is the data clock from catalina, sample rate dependent
|
||||
# this clock equals sample rate in CMOS DDR 1R1T mode
|
||||
# this clock is double the sample rate in CMOS DDR 2R2T mode
|
||||
# Max clock rate is 61.44 MHz
|
||||
NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p";
|
||||
TIMESPEC TS_codec_data_clk_p = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
|
||||
|
||||
|
||||
#always use IOB for GPIF pins for awesome timing
|
||||
INST "GPIF_D_9_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_8_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_7_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_6_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_5_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_4_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_3_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_31_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_30_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_2_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_29_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_28_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_27_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_26_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_25_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_24_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_23_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_22_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_21_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_20_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_1_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL0_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL11_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL12_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL1_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL2_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL3_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL4_IBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL5_IBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL7_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL9_IBUF" IOB =TRUE;
|
||||
INST "GPIF_D_0_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_10_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_11_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_12_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_13_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_14_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_15_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_16_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_17_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_18_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_19_IOBUF" IOB =TRUE;
|
||||
|
||||
# TODO not working... constraints ignored
|
||||
|
||||
#constrain FX3 IO
|
||||
INST "GPIF_D[*]" TNM = "gpif_net_out";
|
||||
INST "GPIF_D[*]" TNM = "gpif_net_in";
|
||||
INST "GPIF_CTL0" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL1" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL2" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL3" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL4" TNM = "gpif_net_in";
|
||||
INST "GPIF_CTL5" TNM = "gpif_net_in";
|
||||
INST "GPIF_CTL6" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL7" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL8" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL11" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL12" TNM = "gpif_net_out";
|
||||
|
||||
#NET "gpif_clk" TNM_NET = "TNM_gpif_clk";
|
||||
#OFFSET = OUT 5 ns AFTER "gpif_clk";
|
||||
#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %;
|
||||
#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING;
|
||||
#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING;
|
||||
@@ -0,0 +1,196 @@
|
||||
//
|
||||
// PlanAhead(TM)
|
||||
// ISEWrap.js: ExploreAhead Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2010 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
return ISEFileSys.OpenTextFile( ISEFullPath, 8, true );
|
||||
}
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# PlanAhead(TM)
|
||||
# ISEWrap.sh: ExploreAhead Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2010 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -0,0 +1,341 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE twReport [
|
||||
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
|
||||
twDebug*, twFoot?, twClientInfo?)>
|
||||
<!ATTLIST twReport version CDATA "10,4">
|
||||
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
|
||||
<!ELEMENT twExecVer (#PCDATA)>
|
||||
<!ELEMENT twCopyright (#PCDATA)>
|
||||
<!ELEMENT twCmdLine (#PCDATA)>
|
||||
<!ELEMENT twDesign (#PCDATA)>
|
||||
<!ELEMENT twPCF (#PCDATA)>
|
||||
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
|
||||
<!ELEMENT twDevName (#PCDATA)>
|
||||
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
|
||||
<!ELEMENT twSpeedGrade (#PCDATA)>
|
||||
<!ELEMENT twSpeedVer (#PCDATA)>
|
||||
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
|
||||
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
|
||||
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
|
||||
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
|
||||
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
|
||||
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twItemLimit (#PCDATA)>
|
||||
<!ELEMENT twUnconst EMPTY>
|
||||
<!ELEMENT twUnconstLimit (#PCDATA)>
|
||||
<!ELEMENT twEnvVar EMPTY>
|
||||
<!ATTLIST twEnvVar name CDATA #REQUIRED>
|
||||
<!ATTLIST twEnvVar description CDATA #REQUIRED>
|
||||
<!ELEMENT twWarn (#PCDATA)>
|
||||
<!ELEMENT twInfo (#PCDATA)>
|
||||
<!ELEMENT twDebug (#PCDATA)>
|
||||
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
|
||||
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
|
||||
<!ELEMENT twProc (#PCDATA)>
|
||||
<!ELEMENT twTemp (#PCDATA)>
|
||||
<!ELEMENT twVolt (#PCDATA)>
|
||||
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
|
||||
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
|
||||
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twCycles (twSigConn+)>
|
||||
<!ATTLIST twCycles twNum CDATA #REQUIRED>
|
||||
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
|
||||
<!ELEMENT twSig (#PCDATA)>
|
||||
<!ELEMENT twDriver (#PCDATA)>
|
||||
<!ELEMENT twLoad (#PCDATA)>
|
||||
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
|
||||
<!ATTLIST twConst twConstType (NET |
|
||||
NETDELAY |
|
||||
NETSKEW |
|
||||
PATH |
|
||||
DEFPERIOD |
|
||||
UNCONSTPATH |
|
||||
DEFPATH |
|
||||
PATH2SETUP |
|
||||
UNCONSTPATH2SETUP |
|
||||
PATHCLASS |
|
||||
PATHDELAY |
|
||||
PERIOD |
|
||||
FREQUENCY |
|
||||
PATHBLOCK |
|
||||
OFFSET |
|
||||
OFFSETIN |
|
||||
OFFSETINCLOCK |
|
||||
UNCONSTOFFSETINCLOCK |
|
||||
OFFSETINDELAY |
|
||||
OFFSETINMOD |
|
||||
OFFSETOUT |
|
||||
OFFSETOUTCLOCK |
|
||||
UNCONSTOFFSETOUTCLOCK |
|
||||
OFFSETOUTDELAY |
|
||||
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
|
||||
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
|
||||
twEndPtCnt?,
|
||||
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
|
||||
<!ELEMENT twConstName (#PCDATA)>
|
||||
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
|
||||
<!ATTLIST twConstHead uID CDATA #IMPLIED>
|
||||
<!ELEMENT twItemCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCntEndPt (#PCDATA)>
|
||||
<!ELEMENT twErrCntSetup (#PCDATA)>
|
||||
<!ELEMENT twErrCntHold (#PCDATA)>
|
||||
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twEndPtCnt (#PCDATA)>
|
||||
<!ELEMENT twPathErrCnt (#PCDATA)>
|
||||
<!ELEMENT twMinPer (#PCDATA) >
|
||||
<!ELEMENT twFootnote EMPTY>
|
||||
<!ATTLIST twFootnote number CDATA #REQUIRED>
|
||||
<!ELEMENT twMaxDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFreq (#PCDATA)>
|
||||
<!ELEMENT twMinOff (#PCDATA)>
|
||||
<!ELEMENT twMaxOff (#PCDATA)>
|
||||
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
|
||||
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
|
||||
<!ELEMENT twTIGName (#PCDATA)>
|
||||
<!ELEMENT twInstantiated (#PCDATA)>
|
||||
<!ELEMENT twBlocked (#PCDATA)>
|
||||
<!ELEMENT twRacePathRpt (twRacePath+)>
|
||||
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
|
||||
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
|
||||
twSimpleMinPath CDATA #IMPLIED>
|
||||
<!ELEMENT twTotDel (#PCDATA)>
|
||||
<!ELEMENT twSrc (#PCDATA)>
|
||||
<!ATTLIST twSrc BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDest (#PCDATA)>
|
||||
<!ATTLIST twDest BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDel (#PCDATA)>
|
||||
<!ELEMENT twSUTime (#PCDATA)>
|
||||
<!ELEMENT twTotPathDel (#PCDATA)>
|
||||
<!ELEMENT twClkSkew (#PCDATA)>
|
||||
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
|
||||
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
|
||||
<!ELEMENT twSlack (#PCDATA)>
|
||||
<!ELEMENT twDelConst (#PCDATA)>
|
||||
<!ELEMENT tw2Phase EMPTY>
|
||||
<!ELEMENT twClkUncert (#PCDATA)>
|
||||
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
|
||||
fDCMJit CDATA #IMPLIED
|
||||
fPhaseErr CDATA #IMPLIED
|
||||
sEqu CDATA #IMPLIED>
|
||||
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
|
||||
<!ELEMENT twPathRptBanner (#PCDATA)>
|
||||
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twOff (#PCDATA)>
|
||||
<!ELEMENT twGuaranteed EMPTY>
|
||||
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
|
||||
<!ELEMENT twClkDel (#PCDATA)>
|
||||
<!ELEMENT twClkSrc (#PCDATA)>
|
||||
<!ELEMENT twClkDest (#PCDATA)>
|
||||
<!ELEMENT twGuarInSetup (#PCDATA)>
|
||||
<!ELEMENT twOffSrc (#PCDATA)>
|
||||
<!ELEMENT twOffDest (#PCDATA)>
|
||||
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ELEMENT twDataDel (#PCDATA)>
|
||||
<!ELEMENT twDataSrc (#PCDATA)>
|
||||
<!ELEMENT twDataDest (#PCDATA)>
|
||||
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
|
||||
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twLogLvls (#PCDATA)>
|
||||
<!ELEMENT twSrcSite (#PCDATA)>
|
||||
<!ELEMENT twSrcClk (#PCDATA)>
|
||||
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
|
||||
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twDelInfo (#PCDATA)>
|
||||
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twSite (#PCDATA)>
|
||||
<!ELEMENT twDelType (#PCDATA)>
|
||||
<!ELEMENT twFanCnt (#PCDATA)>
|
||||
<!ELEMENT twComp (#PCDATA)>
|
||||
<!ELEMENT twNet (#PCDATA)>
|
||||
<!ELEMENT twBEL (#PCDATA)>
|
||||
<!ELEMENT twLogDel (#PCDATA)>
|
||||
<!ELEMENT twRouteDel (#PCDATA)>
|
||||
<!ELEMENT twDestClk (#PCDATA)>
|
||||
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPctLog (#PCDATA)>
|
||||
<!ELEMENT twPctRoute (#PCDATA)>
|
||||
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
|
||||
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
|
||||
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
|
||||
<!ELEMENT twTimeConst (#PCDATA)>
|
||||
<!ELEMENT twAbsSlack (#PCDATA)>
|
||||
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
|
||||
<!ELEMENT twSkew (#PCDATA)>
|
||||
<!ELEMENT twDetNet (twNetDel*)>
|
||||
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
|
||||
<!ELEMENT twNetDelInfo (#PCDATA)>
|
||||
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twDetSkewNet (twNetSkew*)>
|
||||
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
|
||||
<!ELEMENT twClkSkewLimit EMPTY>
|
||||
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
|
||||
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollupTable (twConstRollup*)>
|
||||
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollup EMPTY>
|
||||
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
|
||||
<!ELEMENT twConstList (twConstListItem)*>
|
||||
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
|
||||
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
|
||||
<!ELEMENT twNotMet EMPTY>
|
||||
<!ELEMENT twReqVal (#PCDATA)>
|
||||
<!ELEMENT twActVal (#PCDATA)>
|
||||
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
|
||||
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
|
||||
<!ELEMENT twConstStats (twConstName)>
|
||||
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
|
||||
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
|
||||
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
|
||||
<!ELEMENT twConstData EMPTY>
|
||||
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
|
||||
best CDATA #IMPLIED requested CDATA #IMPLIED
|
||||
errors CDATA #IMPLIED
|
||||
score CDATA #IMPLIED>
|
||||
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
|
||||
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
|
||||
<!ELEMENT twTimeGrpName (#PCDATA)>
|
||||
<!ELEMENT twCompList (twCompName+)>
|
||||
<!ELEMENT twCompName (#PCDATA)>
|
||||
<!ELEMENT twSigList (twSigName+)>
|
||||
<!ELEMENT twSigName (#PCDATA)>
|
||||
<!ELEMENT twBELList (twBELName+)>
|
||||
<!ELEMENT twBELName (#PCDATA)>
|
||||
<!ELEMENT twBlockList (twBlockName+)>
|
||||
<!ELEMENT twBlockName (#PCDATA)>
|
||||
<!ELEMENT twMacList (twMacName+)>
|
||||
<!ELEMENT twMacName (#PCDATA)>
|
||||
<!ELEMENT twPinList (twPinName+)>
|
||||
<!ELEMENT twPinName (#PCDATA)>
|
||||
<!ELEMENT twUnmetConstCnt (#PCDATA)>
|
||||
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
|
||||
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
|
||||
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
|
||||
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
|
||||
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
|
||||
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
|
||||
<!ELEMENT twSU2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twH2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
|
||||
<!ELEMENT twClk2Pad (twDest, twTime)>
|
||||
<!ELEMENT twTime (#PCDATA)>
|
||||
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
|
||||
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2Out EMPTY>
|
||||
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
|
||||
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
|
||||
<!ELEMENT twRiseRise (#PCDATA)>
|
||||
<!ELEMENT twFallRise (#PCDATA)>
|
||||
<!ELEMENT twRiseFall (#PCDATA)>
|
||||
<!ELEMENT twFallFall (#PCDATA)>
|
||||
<!ELEMENT twPad2PadList (twPad2Pad+)>
|
||||
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
|
||||
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
|
||||
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
|
||||
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
|
||||
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
|
||||
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffOutTblRow EMPTY>
|
||||
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
|
||||
<!ELEMENT twNonDedClk (#PCDATA)>
|
||||
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
|
||||
<!ELEMENT twScore (#PCDATA)>
|
||||
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
|
||||
<!ELEMENT twPathCnt (#PCDATA)>
|
||||
<!ELEMENT twNetCnt (#PCDATA)>
|
||||
<!ELEMENT twConnCnt (#PCDATA)>
|
||||
<!ELEMENT twPct (#PCDATA)>
|
||||
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
|
||||
<!ELEMENT twMaxCombDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFromToDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetSkew (#PCDATA)>
|
||||
<!ELEMENT twMaxInAfterClk (#PCDATA)>
|
||||
<!ELEMENT twMinInBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMinOutAfterClk (#PCDATA)>
|
||||
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
|
||||
<!ELEMENT twTimestamp (#PCDATA)>
|
||||
<!ELEMENT twFootnoteExplanation EMPTY>
|
||||
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
|
||||
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
|
||||
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
|
||||
<!ELEMENT twClientName (#PCDATA)>
|
||||
<!ELEMENT twAttrList (twAttrListItem)*>
|
||||
<!ELEMENT twAttrListItem (twName, twValue*)>
|
||||
<!ELEMENT twName (#PCDATA)>
|
||||
<!ELEMENT twValue (#PCDATA)>
|
||||
]>
|
||||
<twReport><twHead anchorID="1"><twExecVer>Release 14.1 Trace (lin64)</twExecVer><twCopyright>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>/opt/Xilinx/14.1/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -e 10 -s 3
|
||||
-n 3 -fastpaths -xml b200.twx b200.ncd -o b200.twr b200.pcf
|
||||
|
||||
</twCmdLine><twDesign>b200.ncd</twDesign><twDesignPath>b200.ncd</twDesignPath><twPCF>b200.pcf</twPCF><twPcfPath>b200.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg484"><twDevName>xc6slx75</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.21 2012-04-23</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twErr" twReportMinPaths="true" dlyHyperLnks="t" ><twItemLimit>10</twItemLimit><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twErrRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="" ScopeName="">TS_codec_main_clk = PERIOD TIMEGRP "codec_main_clk" 25 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>16.000</twMinPer></twConstHead><twPinLimitRpt anchorID="6"><twPinLimitBanner>Component Switching Limit Checks: TS_codec_main_clk = PERIOD TIMEGRP "codec_main_clk" 25 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="7" twConstType="PERIOD" ><twConstHead uID="2"><twConstName UCFConstName="" ScopeName="">TS_IFCLK = PERIOD TIMEGRP "IFCLK" 10 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt></twConstHead><twPinLimitRpt anchorID="8"><twPinLimitBanner>Component Switching Limit Checks: TS_IFCLK = PERIOD TIMEGRP "IFCLK" 10 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="9" twConstType="PERIOD" ><twConstHead uID="3"><twConstName UCFConstName="" ScopeName="">TS_codec_data_clk_p = PERIOD TIMEGRP "codec_data_clk_p" 16.276 ns HIGH 50%;</twConstName><twItemCnt>0</twItemCnt><twErrCntSetup>0</twErrCntSetup><twErrCntEndPt>0</twErrCntEndPt><twErrCntHold twRaceChecked="FALSE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>0</twEndPtCnt><twPathErrCnt>0</twPathErrCnt><twMinPer>1.639</twMinPer></twConstHead><twPinLimitRpt anchorID="10"><twPinLimitBanner>Component Switching Limit Checks: TS_codec_data_clk_p = PERIOD TIMEGRP "codec_data_clk_p" 16.276 ns HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConst anchorID="11" twConstType="PERIOD" ><twConstHead uID="4"><twConstName UCFConstName="" ScopeName="">TS_gen_clks_clkfx = PERIOD TIMEGRP "gen_clks_clkfx" TS_codec_main_clk / 2.5 HIGH 50%;</twConstName><twItemCnt>48903</twItemCnt><twErrCntSetup>2</twErrCntSetup><twErrCntEndPt>2</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>9931</twEndPtCnt><twPathErrCnt>2</twPathErrCnt><twMinPer>12.189</twMinPer></twConstHead><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point slave_fifo32/EP_READY1 (OLOGIC_X4Y173.D1), 1 path
|
||||
</twPathRptBanner><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-2.189</twSlack><twSrc BELType="FF">slave_fifo32/EP_READY</twSrc><twDest BELType="FF">slave_fifo32/EP_READY1</twDest><twTotPathDel>12.263</twTotPathDel><twClkSkew dest = "1.637" src = "1.328">-0.309</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.400" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.235</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>slave_fifo32/EP_READY</twSrc><twDest BELType='FF'>slave_fifo32/EP_READY1</twDest><twLogLvls>0</twLogLvls><twSrcSite>ILOGIC_X17Y55.CLK0</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gpif_clk</twSrcClk><twPathDel><twSite>ILOGIC_X17Y55.Q4</twSite><twDelType>Tickq</twDelType><twDelInfo twEdge="twRising">0.992</twDelInfo><twComp>slave_fifo32/EP_READY</twComp><twBEL>slave_fifo32/EP_READY</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X4Y173.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">10.468</twDelInfo><twComp>slave_fifo32/EP_READY</twComp></twPathDel><twPathDel><twSite>OLOGIC_X4Y173.CLK0</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.803</twDelInfo><twComp>slave_fifo32/EP_READY1</twComp><twBEL>slave_fifo32/EP_READY1</twBEL></twPathDel><twLogDel>1.795</twLogDel><twRouteDel>10.468</twRouteDel><twTotDel>12.263</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">gpif_clk</twDestClk><twPctLog>14.6</twPctLog><twPctRoute>85.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="1" sType="EndPoint">Paths for end point slave_fifo32/EP_WMARK1 (OLOGIC_X2Y175.D1), 1 path
|
||||
</twPathRptBanner><twPathRpt anchorID="14"><twConstPath anchorID="15" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-1.341</twSlack><twSrc BELType="FF">slave_fifo32/EP_WMARK</twSrc><twDest BELType="FF">slave_fifo32/EP_WMARK1</twDest><twTotPathDel>11.029</twTotPathDel><twClkSkew dest = "1.642" src = "1.719">0.077</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.400" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.235</twClkUncert><twDetPath maxSiteLen="18" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>slave_fifo32/EP_WMARK</twSrc><twDest BELType='FF'>slave_fifo32/EP_WMARK1</twDest><twLogLvls>0</twLogLvls><twSrcSite>ILOGIC_X17Y78.CLK0</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">gpif_clk</twSrcClk><twPathDel><twSite>ILOGIC_X17Y78.Q4</twSite><twDelType>Tickq</twDelType><twDelInfo twEdge="twRising">0.992</twDelInfo><twComp>slave_fifo32/EP_WMARK</twComp><twBEL>slave_fifo32/EP_WMARK</twBEL></twPathDel><twPathDel><twSite>OLOGIC_X2Y175.D1</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">9.234</twDelInfo><twComp>slave_fifo32/EP_WMARK</twComp></twPathDel><twPathDel><twSite>OLOGIC_X2Y175.CLK0</twSite><twDelType>Todck</twDelType><twDelInfo twEdge="twRising">0.803</twDelInfo><twComp>slave_fifo32/EP_WMARK1</twComp><twBEL>slave_fifo32/EP_WMARK1</twBEL></twPathDel><twLogDel>1.795</twLogDel><twRouteDel>9.234</twRouteDel><twTotDel>11.029</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">gpif_clk</twDestClk><twPctLog>16.3</twPctLog><twPctRoute>83.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="16"><twPinLimitBanner>Component Switching Limit Checks: TS_gen_clks_clkfx = PERIOD TIMEGRP "gen_clks_clkfx" TS_codec_main_clk / 2.5
|
||||
HIGH 50%;</twPinLimitBanner></twPinLimitRpt></twConst><twConstRollupTable uID="1" anchorID="17"><twConstRollup name="TS_codec_main_clk" fullName="TS_codec_main_clk = PERIOD TIMEGRP "codec_main_clk" 25 ns HIGH 50%;" type="origin" depth="0" requirement="25.000" prefType="period" actual="16.000" actualRollup="30.473" errors="0" errorRollup="2" items="0" itemsRollup="48903"/><twConstRollup name="TS_gen_clks_clkfx" fullName="TS_gen_clks_clkfx = PERIOD TIMEGRP "gen_clks_clkfx" TS_codec_main_clk / 2.5 HIGH 50%;" type="child" depth="1" requirement="10.000" prefType="period" actual="12.189" actualRollup="N/A" errors="2" errorRollup="0" items="48903" itemsRollup="0"/></twConstRollupTable><twUnmetConstCnt anchorID="18">1</twUnmetConstCnt><twDataSheet anchorID="19" twNameLen="16"><twClk2SUList anchorID="20" twDestWidth="16"><twDest>codec_main_clk_n</twDest><twClk2SU><twSrc>codec_main_clk_n</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU><twClk2SU><twSrc>codec_main_clk_p</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="21" twDestWidth="16"><twDest>codec_main_clk_p</twDest><twClk2SU><twSrc>codec_main_clk_n</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU><twClk2SU><twSrc>codec_main_clk_p</twSrc><twRiseRise>12.189</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twErrRpt></twBody><twSum anchorID="22"><twErrCnt>2</twErrCnt><twScore>3530</twScore><twSetupScore>3530</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>48903</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>12388</twConnCnt></twConstCov><twStats anchorID="23"><twMinPer>16.000</twMinPer><twMaxFreq>62.500</twMaxFreq></twStats></twSum><twFoot><twTimestamp>Tue Jan 29 17:12:06 2013 </twTimestamp></twFoot><twClientInfo anchorID="24"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
|
||||
|
||||
Peak Memory Usage: 536 MB
|
||||
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
|
||||
@@ -0,0 +1,415 @@
|
||||
|
||||
####################################################################################
|
||||
# Generated by PlanAhead 14.4 built on 'Tue Dec 18 05:17:28 MST 2012' by 'xbuild'
|
||||
####################################################################################
|
||||
|
||||
|
||||
####################################################################################
|
||||
# Constraints from file : 'b200.ucf'
|
||||
####################################################################################
|
||||
|
||||
## SPI Nets
|
||||
|
||||
NET "cat_ce" LOC = Y1;
|
||||
NET "cat_ce" IOSTANDARD = LVCMOS18;
|
||||
NET "cat_miso" LOC = V1;
|
||||
NET "cat_miso" IOSTANDARD = LVCMOS18;
|
||||
NET "cat_mosi" LOC = T4;
|
||||
NET "cat_mosi" IOSTANDARD = LVCMOS18;
|
||||
NET "cat_sclk" LOC = P7;
|
||||
NET "cat_sclk" IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "fx3_ce" LOC = H20;
|
||||
NET "fx3_miso" LOC = G20;
|
||||
NET "fx3_mosi" LOC = AA20;
|
||||
NET "fx3_sclk" LOC = Y21;
|
||||
|
||||
NET "pll_ce" LOC = W11;
|
||||
NET "pll_mosi" LOC = AB11;
|
||||
NET "pll_sclk" LOC = Y12;
|
||||
|
||||
NET "FPGA_RXD0" LOC = AB8;
|
||||
NET "FPGA_TXD0" LOC = AB7;
|
||||
|
||||
NET "SCL_FPGA" LOC = P21;
|
||||
NET "SDA_FPGA" LOC = W22;
|
||||
|
||||
## Catalina Controls
|
||||
|
||||
NET "codec_enable" LOC = J6;
|
||||
NET "codec_enable" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_en_agc" LOC = P6;
|
||||
NET "codec_en_agc" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_reset" LOC = Y2;
|
||||
NET "codec_reset" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_sync" LOC = M3;
|
||||
NET "codec_sync" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_txrx" LOC = M7;
|
||||
NET "codec_txrx" IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "codec_ctrl_in[0]" LOC = E3;
|
||||
NET "codec_ctrl_in[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in[1]" LOC = F2;
|
||||
NET "codec_ctrl_in[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in[2]" LOC = F1;
|
||||
NET "codec_ctrl_in[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in[3]" LOC = E1;
|
||||
NET "codec_ctrl_in[3]" IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "codec_ctrl_out[0]" LOC = D1;
|
||||
NET "codec_ctrl_out[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[1]" LOC = C1;
|
||||
NET "codec_ctrl_out[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[2]" LOC = H3;
|
||||
NET "codec_ctrl_out[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[3]" LOC = F3;
|
||||
NET "codec_ctrl_out[3]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[4]" LOC = P1;
|
||||
NET "codec_ctrl_out[4]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[5]" LOC = J1;
|
||||
NET "codec_ctrl_out[5]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[6]" LOC = B1;
|
||||
NET "codec_ctrl_out[6]" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out[7]" LOC = H2;
|
||||
NET "codec_ctrl_out[7]" IOSTANDARD = LVCMOS18;
|
||||
|
||||
## Catalina Data RX
|
||||
|
||||
NET "rx_codec_d[0]" LOC = T2;
|
||||
NET "rx_codec_d[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[0]" DRIVE = 4;
|
||||
NET "rx_codec_d[1]" LOC = R1;
|
||||
NET "rx_codec_d[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[1]" DRIVE = 4;
|
||||
NET "rx_codec_d[2]" LOC = V2;
|
||||
NET "rx_codec_d[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[2]" DRIVE = 4;
|
||||
NET "rx_codec_d[3]" LOC = N1;
|
||||
NET "rx_codec_d[3]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[3]" DRIVE = 4;
|
||||
NET "rx_codec_d[4]" LOC = V3;
|
||||
NET "rx_codec_d[4]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[4]" DRIVE = 4;
|
||||
NET "rx_codec_d[5]" LOC = T1;
|
||||
NET "rx_codec_d[5]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[5]" DRIVE = 4;
|
||||
NET "rx_codec_d[6]" LOC = W1;
|
||||
NET "rx_codec_d[6]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[6]" DRIVE = 4;
|
||||
NET "rx_codec_d[7]" LOC = U1;
|
||||
NET "rx_codec_d[7]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[7]" DRIVE = 4;
|
||||
NET "rx_codec_d[8]" LOC = W3;
|
||||
NET "rx_codec_d[8]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[8]" DRIVE = 4;
|
||||
NET "rx_codec_d[9]" LOC = U3;
|
||||
NET "rx_codec_d[9]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[9]" DRIVE = 4;
|
||||
NET "rx_codec_d[10]" LOC = P2;
|
||||
NET "rx_codec_d[10]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[10]" DRIVE = 4;
|
||||
NET "rx_codec_d[11]" LOC = R3;
|
||||
NET "rx_codec_d[11]" IOSTANDARD = LVCMOS18;
|
||||
NET "rx_codec_d[11]" DRIVE = 4;
|
||||
|
||||
## Catalina Data TX
|
||||
|
||||
NET "tx_codec_d[0]" LOC = M1;
|
||||
NET "tx_codec_d[0]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[0]" DRIVE = 4;
|
||||
NET "tx_codec_d[1]" LOC = K1;
|
||||
NET "tx_codec_d[1]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[1]" DRIVE = 4;
|
||||
NET "tx_codec_d[2]" LOC = L3;
|
||||
NET "tx_codec_d[2]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[2]" DRIVE = 4;
|
||||
NET "tx_codec_d[3]" LOC = K2;
|
||||
NET "tx_codec_d[3]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[3]" DRIVE = 4;
|
||||
NET "tx_codec_d[4]" LOC = M4;
|
||||
NET "tx_codec_d[4]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[4]" DRIVE = 4;
|
||||
NET "tx_codec_d[5]" LOC = J4;
|
||||
NET "tx_codec_d[5]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[5]" DRIVE = 4;
|
||||
NET "tx_codec_d[6]" LOC = L4;
|
||||
NET "tx_codec_d[6]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[6]" DRIVE = 4;
|
||||
NET "tx_codec_d[7]" LOC = H1;
|
||||
NET "tx_codec_d[7]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[7]" DRIVE = 4;
|
||||
NET "tx_codec_d[8]" LOC = M2;
|
||||
NET "tx_codec_d[8]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[8]" DRIVE = 4;
|
||||
NET "tx_codec_d[9]" LOC = G1;
|
||||
NET "tx_codec_d[9]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[9]" DRIVE = 4;
|
||||
NET "tx_codec_d[10]" LOC = N3;
|
||||
NET "tx_codec_d[10]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[10]" DRIVE = 4;
|
||||
NET "tx_codec_d[11]" LOC = G3;
|
||||
NET "tx_codec_d[11]" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_codec_d[11]" DRIVE = 4;
|
||||
|
||||
## Catalina Clocks
|
||||
|
||||
NET "cat_clkout_fpga" LOC = J3;
|
||||
NET "cat_clkout_fpga" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_data_clk_p" LOC = K3;
|
||||
NET "codec_data_clk_p" IOSTANDARD = LVCMOS18;
|
||||
NET "codec_fb_clk_p" LOC = P3;
|
||||
NET "codec_fb_clk_p" IOSTANDARD = LVCMOS18;
|
||||
# | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_main_clk_p" LOC = K5;
|
||||
# | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_main_clk_n" LOC = K4;
|
||||
|
||||
NET "rx_frame_p" LOC = U4;
|
||||
NET "rx_frame_p" IOSTANDARD = LVCMOS18;
|
||||
NET "tx_frame_p" LOC = T3;
|
||||
NET "tx_frame_p" IOSTANDARD = LVCMOS18;
|
||||
|
||||
## Debug Bus
|
||||
|
||||
NET "debug[0]" LOC = C14;
|
||||
NET "debug[1]" LOC = F15;
|
||||
NET "debug[2]" LOC = A18;
|
||||
NET "debug[3]" LOC = A17;
|
||||
NET "debug[4]" LOC = E14;
|
||||
NET "debug[5]" LOC = G13;
|
||||
NET "debug[6]" LOC = D13;
|
||||
NET "debug[7]" LOC = F13;
|
||||
NET "debug[8]" LOC = D8;
|
||||
NET "debug[9]" LOC = A6;
|
||||
NET "debug[10]" LOC = D7;
|
||||
NET "debug[11]" LOC = A5;
|
||||
NET "debug[12]" LOC = B6;
|
||||
NET "debug[13]" LOC = A3;
|
||||
NET "debug[14]" LOC = A7;
|
||||
NET "debug[15]" LOC = A8;
|
||||
NET "debug[16]" LOC = B18;
|
||||
NET "debug[17]" LOC = C17;
|
||||
NET "debug[18]" LOC = H13;
|
||||
NET "debug[19]" LOC = D12;
|
||||
NET "debug[20]" LOC = H14;
|
||||
NET "debug[21]" LOC = C10;
|
||||
NET "debug[22]" LOC = D10;
|
||||
NET "debug[23]" LOC = C8;
|
||||
NET "debug[24]" LOC = D9;
|
||||
NET "debug[25]" LOC = C5;
|
||||
NET "debug[26]" LOC = A9;
|
||||
NET "debug[27]" LOC = B8;
|
||||
NET "debug[28]" LOC = A4;
|
||||
NET "debug[29]" LOC = C7;
|
||||
NET "debug[30]" LOC = C6;
|
||||
NET "debug[31]" LOC = D6;
|
||||
|
||||
NET "debug_clk[0]" LOC = A12;
|
||||
NET "debug_clk[1]" LOC = C12;
|
||||
|
||||
## GPIF
|
||||
|
||||
NET "IFCLK" LOC = H21;
|
||||
NET "FX3_EXTINT" LOC = U20;
|
||||
|
||||
NET "GPIF_CTL0" LOC = V20;
|
||||
NET "GPIF_CTL1" LOC = T22;
|
||||
NET "GPIF_CTL2" LOC = R22;
|
||||
NET "GPIF_CTL3" LOC = U22;
|
||||
NET "GPIF_CTL4" LOC = P19;
|
||||
NET "GPIF_CTL5" LOC = N22;
|
||||
NET "GPIF_CTL6" LOC = T21;
|
||||
NET "GPIF_CTL7" LOC = V21;
|
||||
NET "GPIF_CTL8" LOC = K18;
|
||||
NET "GPIF_CTL9" LOC = R20;
|
||||
##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
|
||||
NET "GPIF_CTL11" LOC = P22;
|
||||
NET "GPIF_CTL12" LOC = M20;
|
||||
|
||||
NET "GPIF_D[0]" LOC = T17;
|
||||
NET "GPIF_D[1]" LOC = U14;
|
||||
NET "GPIF_D[2]" LOC = U13;
|
||||
NET "GPIF_D[3]" LOC = AA6;
|
||||
NET "GPIF_D[4]" LOC = AB6;
|
||||
NET "GPIF_D[5]" LOC = Y3;
|
||||
NET "GPIF_D[6]" LOC = AB3;
|
||||
NET "GPIF_D[7]" LOC = AA4;
|
||||
NET "GPIF_D[8]" LOC = AA2;
|
||||
NET "GPIF_D[9]" LOC = AB2;
|
||||
NET "GPIF_D[10]" LOC = AB19;
|
||||
NET "GPIF_D[11]" LOC = AA18;
|
||||
NET "GPIF_D[12]" LOC = AB18;
|
||||
NET "GPIF_D[13]" LOC = Y13;
|
||||
NET "GPIF_D[14]" LOC = AA12;
|
||||
NET "GPIF_D[15]" LOC = AB12;
|
||||
NET "GPIF_D[16]" LOC = N20;
|
||||
NET "GPIF_D[17]" LOC = L20;
|
||||
NET "GPIF_D[18]" LOC = N19;
|
||||
NET "GPIF_D[19]" LOC = M22;
|
||||
NET "GPIF_D[20]" LOC = L19;
|
||||
NET "GPIF_D[21]" LOC = M21;
|
||||
NET "GPIF_D[22]" LOC = M19;
|
||||
NET "GPIF_D[23]" LOC = K22;
|
||||
NET "GPIF_D[24]" LOC = J20;
|
||||
NET "GPIF_D[25]" LOC = L22;
|
||||
NET "GPIF_D[26]" LOC = K19;
|
||||
NET "GPIF_D[27]" LOC = H22;
|
||||
NET "GPIF_D[28]" LOC = J22;
|
||||
NET "GPIF_D[29]" LOC = K20;
|
||||
NET "GPIF_D[30]" LOC = G22;
|
||||
NET "GPIF_D[31]" LOC = F22;
|
||||
|
||||
## GPS
|
||||
|
||||
NET "gps_lock" LOC = Y17;
|
||||
NET "gps_out_enable" LOC = V22;
|
||||
NET "gps_ref_enable" LOC = AB13;
|
||||
NET "gps_rxd" LOC = AB14;
|
||||
NET "gps_txd" LOC = W12;
|
||||
NET "gps_txd_nmea" LOC = AA14;
|
||||
|
||||
## LEDS
|
||||
|
||||
NET "LED_RX1" LOC = C22;
|
||||
NET "LED_RX2" LOC = L15;
|
||||
NET "LED_TXRX1_TX" LOC = C20;
|
||||
NET "LED_TXRX2_RX" LOC = D21;
|
||||
NET "LED_TXRX1_RX" LOC = K16;
|
||||
NET "LED_TXRX2_TX" LOC = D22;
|
||||
|
||||
## Misc Hardware Control
|
||||
|
||||
NET "ext_ref_enable" LOC = Y15;
|
||||
NET "pll_lock" LOC = AB10;
|
||||
NET "AUX_PWR_ON" LOC = AA21;
|
||||
#NET "RFUSE" LOC = "P15" ;
|
||||
|
||||
## PPS
|
||||
|
||||
NET "pps_fpga_out_enable" LOC = AB15;
|
||||
NET "PPS_IN_EXT" LOC = AB16;
|
||||
NET "PPS_IN_INT" LOC = AB21;
|
||||
NET "pps_out" LOC = AB17;
|
||||
|
||||
## RF Hardware Control
|
||||
|
||||
NET "SFDX1_RX" LOC = W4;
|
||||
NET "SFDX1_TX" LOC = T18;
|
||||
NET "SFDX2_RX" LOC = F18;
|
||||
NET "SFDX2_TX" LOC = H17;
|
||||
NET "SRX1_RX" LOC = Y7;
|
||||
NET "SRX1_TX" LOC = AA8;
|
||||
NET "SRX2_RX" LOC = J17;
|
||||
NET "SRX2_TX" LOC = F19;
|
||||
NET "tx_bandsel_a" LOC = N16;
|
||||
NET "tx_bandsel_b" LOC = M16;
|
||||
NET "tx_enable1" LOC = Y4;
|
||||
NET "tx_enable2" LOC = R19;
|
||||
NET "rx_bandsel_a" LOC = T20;
|
||||
NET "rx_bandsel_b" LOC = U19;
|
||||
NET "rx_bandsel_c" LOC = P20;
|
||||
|
||||
## FPGA Config Pins
|
||||
|
||||
#NET "FPGA_CFG_INIT_B" LOC = "T6" ;
|
||||
#NET "FPGA_CFG_DONE" LOC = "Y22" ;
|
||||
#NET "FPGA_CFG_M0" LOC = "AA22" ;
|
||||
#NET "FPGA_CFG_M1" LOC = "U15" ;
|
||||
#NET "FPGA_CFG_PROG_B" LOC = "AA1" ;
|
||||
|
||||
## Special Pins
|
||||
|
||||
#NET "VFS" LOC = "P16" ;
|
||||
#NET "TMS" LOC = "C18" ;
|
||||
#NET "TDO" LOC = "A19" ;
|
||||
#NET "TDI" LOC = "E18" ;
|
||||
#NET "TCK" LOC = "G15" ;
|
||||
#NET "GND" LOC = "N15" ;
|
||||
|
||||
####################################################################################
|
||||
# Constraints from file : 'timing.ucf'
|
||||
####################################################################################
|
||||
|
||||
|
||||
# codec_main_clk is 40 MHz main tcxo clock
|
||||
NET "codec_main_clk*" TNM_NET = "codec_main_clk";
|
||||
TIMESPEC TS_codec_main_clk = PERIOD "codec_main_clk" 25000 ps HIGH 50 %;
|
||||
|
||||
|
||||
# IFCLK is 100 MHz GPIF clock
|
||||
NET "IFCLK" TNM_NET = "IFCLK";
|
||||
TIMESPEC TS_IFCLK = PERIOD "IFCLK" 10000 ps HIGH 50 %;
|
||||
|
||||
|
||||
# codec_data_clk is the data clock from catalina, sample rate dependent
|
||||
# this clock equals sample rate in CMOS DDR 1R1T mode
|
||||
# this clock is double the sample rate in CMOS DDR 2R2T mode
|
||||
# Max clock rate is 61.44 MHz
|
||||
NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p";
|
||||
TIMESPEC TS_codec_data_clk_p = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
|
||||
|
||||
|
||||
#always use IOB for GPIF pins for awesome timing
|
||||
INST "GPIF_D_9_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_8_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_7_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_6_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_5_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_4_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_3_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_31_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_30_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_2_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_29_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_28_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_27_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_26_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_25_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_24_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_23_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_22_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_21_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_20_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_1_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL0_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL11_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL12_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL1_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL2_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL3_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL4_IBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL5_IBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL7_OBUF" IOB =TRUE;
|
||||
INST "GPIF_CTL9_IBUF" IOB =TRUE;
|
||||
INST "GPIF_D_0_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_10_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_11_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_12_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_13_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_14_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_15_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_16_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_17_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_18_IOBUF" IOB =TRUE;
|
||||
INST "GPIF_D_19_IOBUF" IOB =TRUE;
|
||||
|
||||
# TODO not working... constraints ignored
|
||||
|
||||
#constrain FX3 IO
|
||||
INST "GPIF_D[*]" TNM = "gpif_net_out";
|
||||
INST "GPIF_D[*]" TNM = "gpif_net_in";
|
||||
INST "GPIF_CTL0" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL1" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL2" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL3" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL4" TNM = "gpif_net_in";
|
||||
INST "GPIF_CTL5" TNM = "gpif_net_in";
|
||||
INST "GPIF_CTL7" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL11" TNM = "gpif_net_out";
|
||||
INST "GPIF_CTL12" TNM = "gpif_net_out";
|
||||
|
||||
#NET "gpif_clk" TNM_NET = "TNM_gpif_clk";
|
||||
#OFFSET = OUT 5 ns AFTER "gpif_clk";
|
||||
#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %;
|
||||
#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING;
|
||||
#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING;
|
||||
Binary file not shown.
@@ -0,0 +1,13 @@
|
||||
#
|
||||
# PlanAhead(TM)
|
||||
# htr.txt: a PlanAhead-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for PlanAhead to track run status.
|
||||
# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
ngdbuild -intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc "b200.ucf" "b200.edf"
|
||||
map -intstyle pa -w "b200.ngd"
|
||||
par -intstyle pa "b200.ncd" -w "b200_routed.ncd"
|
||||
trce -intstyle ise -o "b200.twr" -v 30 -l 30 "b200_routed.ncd" "b200.pcf"
|
||||
xdl -secure -ncd2xdl -nopips "b200_routed.ncd" "b200_routed.xdl"
|
||||
@@ -0,0 +1,48 @@
|
||||
//
|
||||
// PlanAhead(TM)
|
||||
// rundef.js: a PlanAhead-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64;/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64;/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin;";
|
||||
} else {
|
||||
PathVal = "/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64;/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64;/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "ngdbuild",
|
||||
"-intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc \"b200.ucf\" \"b200.edf\"" );
|
||||
ISEStep( "map",
|
||||
"-intstyle pa -w \"b200.ngd\"" );
|
||||
ISEStep( "par",
|
||||
"-intstyle pa \"b200.ncd\" -w \"b200_routed.ncd\"" );
|
||||
ISEStep( "trce",
|
||||
"-intstyle ise -o \"b200.twr\" -v 30 -l 30 \"b200_routed.ncd\" \"b200.pcf\"" );
|
||||
ISEStep( "xdl",
|
||||
"-secure -ncd2xdl -nopips \"b200_routed.ncd\" \"b200_routed.xdl\"" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
@echo off
|
||||
|
||||
rem PlanAhead (TM)
|
||||
rem runme.bat: a PlanAhead-generated Script
|
||||
rem Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
@@ -0,0 +1,4 @@
|
||||
*** PLEASE NOTE: this run was imported on Tue Jan 29 17:25:57 2013
|
||||
from ISE results generated outside of PlanAhead.
|
||||
Original messages and reports have not been imported
|
||||
but you can launch bitgen on this run if desired...
|
||||
+43
@@ -0,0 +1,43 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# PlanAhead(TM)
|
||||
# runme.sh: a PlanAhead-generated Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2012 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64:/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin
|
||||
else
|
||||
PATH=/opt/Xilinx/14.4/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.4/ISE_DS/common/bin/lin64:/opt/Xilinx/14.4/ISE_DS/PlanAhead/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64
|
||||
else
|
||||
LD_LIBRARY_PATH=/opt/Xilinx/14.4/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.4/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.4/ISE_DS/common/lib/lin64:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD=`dirname "$0"`
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep ngdbuild -intstyle ise -p xc6slx75fgg484-3 -dd _ngo -uc "b200.ucf" "b200.edf"
|
||||
EAStep map -intstyle pa -w "b200.ngd"
|
||||
EAStep par -intstyle pa "b200.ncd" -w "b200_routed.ncd"
|
||||
EAStep trce -intstyle ise -o "b200.twr" -v 30 -l 30 "b200_routed.ncd" "b200.pcf"
|
||||
EAStep xdl -secure -ncd2xdl -nopips "b200_routed.ncd" "b200_routed.xdl"
|
||||
@@ -0,0 +1,241 @@
|
||||
## SPI Nets
|
||||
|
||||
NET "cat_ce" LOC = "Y1" | IOSTANDARD = LVCMOS18;
|
||||
NET "cat_miso" LOC = "V1" | IOSTANDARD = LVCMOS18;
|
||||
NET "cat_mosi" LOC = "T4" | IOSTANDARD = LVCMOS18;
|
||||
NET "cat_sclk" LOC = "P7" | IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "fx3_ce" LOC = "H20" ;
|
||||
NET "fx3_miso" LOC = "G20" ;
|
||||
NET "fx3_mosi" LOC = "AA20" ;
|
||||
NET "fx3_sclk" LOC = "Y21" ;
|
||||
|
||||
NET "pll_ce" LOC = "W11" ;
|
||||
NET "pll_mosi" LOC = "AB11" ;
|
||||
NET "pll_sclk" LOC = "Y12" ;
|
||||
|
||||
NET "FPGA_RXD0" LOC = "AB8" ;
|
||||
NET "FPGA_TXD0" LOC = "AB7" ;
|
||||
|
||||
NET "SCL_FPGA" LOC = "P21" ;
|
||||
NET "SDA_FPGA" LOC = "W22" ;
|
||||
|
||||
## Catalina Controls
|
||||
|
||||
NET "codec_enable" LOC = "J6" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_en_agc" LOC = "P6" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_reset" LOC = "Y2" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_sync" LOC = "M3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_txrx" LOC = "M7" | IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "codec_ctrl_in<0>" LOC = "E3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in<1>" LOC = "F2" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in<2>" LOC = "F1" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_in<3>" LOC = "E1" | IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "codec_ctrl_out<0>" LOC = "D1" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<1>" LOC = "C1" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<2>" LOC = "H3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<3>" LOC = "F3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<4>" LOC = "P1" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<5>" LOC = "J1" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<6>" LOC = "B1" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_ctrl_out<7>" LOC = "H2" | IOSTANDARD = LVCMOS18;
|
||||
|
||||
## Catalina Data RX
|
||||
|
||||
NET "rx_codec_d<0>" LOC = "T2" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<1>" LOC = "R1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<2>" LOC = "V2" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<3>" LOC = "N1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<4>" LOC = "V3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<5>" LOC = "T1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<6>" LOC = "W1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<7>" LOC = "U1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<8>" LOC = "W3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<9>" LOC = "U3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<10>" LOC = "P2" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "rx_codec_d<11>" LOC = "R3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
|
||||
## Catalina Data TX
|
||||
|
||||
NET "tx_codec_d<0>" LOC = "M1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<1>" LOC = "K1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<2>" LOC = "L3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<3>" LOC = "K2" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<4>" LOC = "M4" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<5>" LOC = "J4" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<6>" LOC = "L4" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<7>" LOC = "H1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<8>" LOC = "M2" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<9>" LOC = "G1" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<10>" LOC = "N3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
NET "tx_codec_d<11>" LOC = "G3" | IOSTANDARD = LVCMOS18 | DRIVE = 4;
|
||||
|
||||
## Catalina Clocks
|
||||
|
||||
NET "cat_clkout_fpga" LOC = "J3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_data_clk_p" LOC = "K3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_fb_clk_p" LOC = "P3" | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_main_clk_p" LOC = "K5" ;# | IOSTANDARD = LVCMOS18;
|
||||
NET "codec_main_clk_n" LOC = "K4" ;# | IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "rx_frame_p" LOC = "U4" | IOSTANDARD = LVCMOS18;
|
||||
NET "tx_frame_p" LOC = "T3" | IOSTANDARD = LVCMOS18;
|
||||
|
||||
## Debug Bus
|
||||
|
||||
NET "debug<0>" LOC = "C14" ;
|
||||
NET "debug<1>" LOC = "F15" ;
|
||||
NET "debug<2>" LOC = "A18" ;
|
||||
NET "debug<3>" LOC = "A17" ;
|
||||
NET "debug<4>" LOC = "E14" ;
|
||||
NET "debug<5>" LOC = "G13" ;
|
||||
NET "debug<6>" LOC = "D13" ;
|
||||
NET "debug<7>" LOC = "F13" ;
|
||||
NET "debug<8>" LOC = "D8" ;
|
||||
NET "debug<9>" LOC = "A6" ;
|
||||
NET "debug<10>" LOC = "D7" ;
|
||||
NET "debug<11>" LOC = "A5" ;
|
||||
NET "debug<12>" LOC = "B6" ;
|
||||
NET "debug<13>" LOC = "A3" ;
|
||||
NET "debug<14>" LOC = "A7" ;
|
||||
NET "debug<15>" LOC = "A8" ;
|
||||
NET "debug<16>" LOC = "B18" ;
|
||||
NET "debug<17>" LOC = "C17" ;
|
||||
NET "debug<18>" LOC = "H13" ;
|
||||
NET "debug<19>" LOC = "D12" ;
|
||||
NET "debug<20>" LOC = "H14" ;
|
||||
NET "debug<21>" LOC = "C10" ;
|
||||
NET "debug<22>" LOC = "D10" ;
|
||||
NET "debug<23>" LOC = "C8" ;
|
||||
NET "debug<24>" LOC = "D9" ;
|
||||
NET "debug<25>" LOC = "C5" ;
|
||||
NET "debug<26>" LOC = "A9" ;
|
||||
NET "debug<27>" LOC = "B8" ;
|
||||
NET "debug<28>" LOC = "A4" ;
|
||||
NET "debug<29>" LOC = "C7" ;
|
||||
NET "debug<30>" LOC = "C6" ;
|
||||
NET "debug<31>" LOC = "D6" ;
|
||||
|
||||
NET "debug_clk<0>" LOC = "A12" ;
|
||||
NET "debug_clk<1>" LOC = "C12" ;
|
||||
|
||||
## GPIF
|
||||
|
||||
NET "IFCLK" LOC = "H21" ;
|
||||
NET "FX3_EXTINT" LOC = "U20" ;
|
||||
|
||||
NET "GPIF_CTL0" LOC = "V20" ;
|
||||
NET "GPIF_CTL1" LOC = "T22" ;
|
||||
NET "GPIF_CTL2" LOC = "R22" ;
|
||||
NET "GPIF_CTL3" LOC = "U22" ;
|
||||
NET "GPIF_CTL4" LOC = "P19" ;
|
||||
NET "GPIF_CTL5" LOC = "N22" ;
|
||||
NET "GPIF_CTL6" LOC = "T21" ;
|
||||
NET "GPIF_CTL7" LOC = "V21" ;
|
||||
NET "GPIF_CTL8" LOC = "K18" ;
|
||||
NET "GPIF_CTL9" LOC = "R20" ;
|
||||
##GPIF_CTL10 is "FPGA_CFG_DONE", defined later.
|
||||
NET "GPIF_CTL11" LOC = "P22" ;
|
||||
NET "GPIF_CTL12" LOC = "M20" ;
|
||||
|
||||
NET "GPIF_D<0>" LOC = "T17" ;
|
||||
NET "GPIF_D<1>" LOC = "U14" ;
|
||||
NET "GPIF_D<2>" LOC = "U13" ;
|
||||
NET "GPIF_D<3>" LOC = "AA6" ;
|
||||
NET "GPIF_D<4>" LOC = "AB6" ;
|
||||
NET "GPIF_D<5>" LOC = "Y3" ;
|
||||
NET "GPIF_D<6>" LOC = "AB3" ;
|
||||
NET "GPIF_D<7>" LOC = "AA4" ;
|
||||
NET "GPIF_D<8>" LOC = "AA2" ;
|
||||
NET "GPIF_D<9>" LOC = "AB2" ;
|
||||
NET "GPIF_D<10>" LOC = "AB19" ;
|
||||
NET "GPIF_D<11>" LOC = "AA18" ;
|
||||
NET "GPIF_D<12>" LOC = "AB18" ;
|
||||
NET "GPIF_D<13>" LOC = "Y13" ;
|
||||
NET "GPIF_D<14>" LOC = "AA12" ;
|
||||
NET "GPIF_D<15>" LOC = "AB12" ;
|
||||
NET "GPIF_D<16>" LOC = "N20" ;
|
||||
NET "GPIF_D<17>" LOC = "L20" ;
|
||||
NET "GPIF_D<18>" LOC = "N19" ;
|
||||
NET "GPIF_D<19>" LOC = "M22" ;
|
||||
NET "GPIF_D<20>" LOC = "L19" ;
|
||||
NET "GPIF_D<21>" LOC = "M21" ;
|
||||
NET "GPIF_D<22>" LOC = "M19" ;
|
||||
NET "GPIF_D<23>" LOC = "K22" ;
|
||||
NET "GPIF_D<24>" LOC = "J20" ;
|
||||
NET "GPIF_D<25>" LOC = "L22" ;
|
||||
NET "GPIF_D<26>" LOC = "K19" ;
|
||||
NET "GPIF_D<27>" LOC = "H22" ;
|
||||
NET "GPIF_D<28>" LOC = "J22" ;
|
||||
NET "GPIF_D<29>" LOC = "K20" ;
|
||||
NET "GPIF_D<30>" LOC = "G22" ;
|
||||
NET "GPIF_D<31>" LOC = "F22" ;
|
||||
|
||||
## GPS
|
||||
|
||||
NET "gps_lock" LOC = "Y17" ;
|
||||
NET "gps_out_enable" LOC = "V22" ;
|
||||
NET "gps_ref_enable" LOC = "AB13" ;
|
||||
NET "gps_rxd" LOC = "AB14" ;
|
||||
NET "gps_txd" LOC = "W12" ;
|
||||
NET "gps_txd_nmea" LOC = "AA14" ;
|
||||
|
||||
## LEDS
|
||||
|
||||
NET "LED_RX1" LOC = "C22" ;
|
||||
NET "LED_RX2" LOC = "L15" ;
|
||||
NET "LED_TXRX1_TX" LOC = "C20" ;
|
||||
NET "LED_TXRX2_RX" LOC = "D21" ;
|
||||
NET "LED_TXRX1_RX" LOC = "K16" ;
|
||||
NET "LED_TXRX2_TX" LOC = "D22" ;
|
||||
|
||||
## Misc Hardware Control
|
||||
|
||||
NET "ext_ref_enable" LOC = "Y15" ;
|
||||
NET "pll_lock" LOC = "AB10" ;
|
||||
NET "AUX_PWR_ON" LOC = "AA21" ;
|
||||
#NET "RFUSE" LOC = "P15" ;
|
||||
|
||||
## PPS
|
||||
|
||||
NET "pps_fpga_out_enable" LOC = "AB15" ;
|
||||
NET "PPS_IN_EXT" LOC = "AB16" ;
|
||||
NET "PPS_IN_INT" LOC = "AB21" ;
|
||||
NET "pps_out" LOC = "AB17" ;
|
||||
|
||||
## RF Hardware Control
|
||||
|
||||
NET "SFDX1_RX" LOC = "W4" ;
|
||||
NET "SFDX1_TX" LOC = "T18" ;
|
||||
NET "SFDX2_RX" LOC = "F18" ;
|
||||
NET "SFDX2_TX" LOC = "H17" ;
|
||||
NET "SRX1_RX" LOC = "Y7" ;
|
||||
NET "SRX1_TX" LOC = "AA8" ;
|
||||
NET "SRX2_RX" LOC = "J17" ;
|
||||
NET "SRX2_TX" LOC = "F19" ;
|
||||
NET "tx_bandsel_a" LOC = "N16" ;
|
||||
NET "tx_bandsel_b" LOC = "M16" ;
|
||||
NET "tx_enable1" LOC = "Y4" ;
|
||||
NET "tx_enable2" LOC = "R19" ;
|
||||
NET "rx_bandsel_a" LOC = "T20" ;
|
||||
NET "rx_bandsel_b" LOC = "U19" ;
|
||||
NET "rx_bandsel_c" LOC = "P20" ;
|
||||
|
||||
## FPGA Config Pins
|
||||
|
||||
#NET "FPGA_CFG_INIT_B" LOC = "T6" ;
|
||||
#NET "FPGA_CFG_DONE" LOC = "Y22" ;
|
||||
#NET "FPGA_CFG_M0" LOC = "AA22" ;
|
||||
#NET "FPGA_CFG_M1" LOC = "U15" ;
|
||||
#NET "FPGA_CFG_PROG_B" LOC = "AA1" ;
|
||||
|
||||
## Special Pins
|
||||
|
||||
#NET "VFS" LOC = "P16" ;
|
||||
#NET "TMS" LOC = "C18" ;
|
||||
#NET "TDO" LOC = "A19" ;
|
||||
#NET "TDI" LOC = "E18" ;
|
||||
#NET "TCK" LOC = "G15" ;
|
||||
#NET "GND" LOC = "N15" ;
|
||||
@@ -0,0 +1,44 @@
|
||||
|
||||
# codec_main_clk is 40 MHz main tcxo clock
|
||||
NET "codec_main_clk*" TNM_NET = "codec_main_clk";
|
||||
TIMESPEC "TS_codec_main_clk" = PERIOD "codec_main_clk" 25000 ps HIGH 50 %;
|
||||
|
||||
|
||||
# IFCLK is 100 MHz GPIF clock
|
||||
NET "IFCLK" TNM_NET = "IFCLK";
|
||||
TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 10000 ps HIGH 50 %;
|
||||
|
||||
|
||||
# codec_data_clk is the data clock from catalina, sample rate dependent
|
||||
# this clock equals sample rate in CMOS DDR 1R1T mode
|
||||
# this clock is double the sample rate in CMOS DDR 2R2T mode
|
||||
# Max clock rate is 61.44 MHz
|
||||
NET "codec_data_clk_p" TNM_NET = "codec_data_clk_p";
|
||||
TIMESPEC "TS_codec_data_clk_p" = PERIOD "codec_data_clk_p" 16276 ps HIGH 50 %;
|
||||
|
||||
|
||||
#always use IOB for GPIF pins for awesome timing
|
||||
INST "GPIF_*" IOB = TRUE;
|
||||
|
||||
# TODO not working... constraints ignored
|
||||
|
||||
#constrain FX3 IO
|
||||
INST "GPIF_D<*>" TNM = gpif_net_out;
|
||||
INST "GPIF_D<*>" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL0" TNM = gpif_net_out;
|
||||
INST "GPIF_CTL1" TNM = gpif_net_out;
|
||||
INST "GPIF_CTL2" TNM = gpif_net_out;
|
||||
INST "GPIF_CTL3" TNM = gpif_net_out;
|
||||
INST "GPIF_CTL4" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL5" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL6" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL7" TNM = gpif_net_out;
|
||||
INST "GPIF_CTL8" TNM = gpif_net_in;
|
||||
INST "GPIF_CTL11" TNM = gpif_net_out;
|
||||
INST "GPIF_CTL12" TNM = gpif_net_out;
|
||||
|
||||
#NET "gpif_clk" TNM_NET = "TNM_gpif_clk";
|
||||
#OFFSET = OUT 5 ns AFTER "gpif_clk";
|
||||
#TIMESPEC "TS_gpif_clk" = PERIOD "TNM_gpif_clk" 10000 ps HIGH 50 %;
|
||||
#TIMEGRP "gpif_net_in" OFFSET = IN 6 ns VALID 6 ns BEFORE "gpif_clk" RISING;
|
||||
#TIMEGRP "gpif_net_out" OFFSET = OUT 6 ns AFTER "gpif_clk" RISING;
|
||||
File diff suppressed because one or more lines are too long
Executable
+45
@@ -0,0 +1,45 @@
|
||||
#!/bin/bash
|
||||
|
||||
iterations=1
|
||||
directory="."
|
||||
targets=""
|
||||
name=""
|
||||
outdir=${PWD}
|
||||
|
||||
for arg in "$@"; do
|
||||
if [[ $arg == "--help" ]]; then
|
||||
echo "Usage: batch-build [options] targets"
|
||||
echo "Options:"
|
||||
echo " --runs=N [1] Build the specified targets N times"
|
||||
echo " --dir=<dir> [.] Makefile directory"
|
||||
echo " --name=<name> [<empty>] Name of this batch job. Used as a prefix for build output"
|
||||
echo " --help Print the message and exit"
|
||||
echo ""
|
||||
exit 0
|
||||
elif [[ $arg =~ "--runs="([0-9]+) ]]; then
|
||||
iterations=${BASH_REMATCH[1]}
|
||||
elif [[ $arg =~ "--dir="(.+) ]]; then
|
||||
directory=${BASH_REMATCH[1]}
|
||||
elif [[ $arg =~ "--name="(.+) ]]; then
|
||||
name=${BASH_REMATCH[1]}"_"
|
||||
else
|
||||
targets=$targets$arg" "
|
||||
fi
|
||||
done
|
||||
|
||||
cd $directory >/dev/null 2>&1
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "ERROR: Could not cd to $directory"
|
||||
exit
|
||||
fi
|
||||
|
||||
for i in $(seq 1 $iterations); do
|
||||
make $targets
|
||||
if [ $? -ne 0 ]; then
|
||||
echo "ERROR: Build Failed!!! Stopping batch build."
|
||||
exit
|
||||
fi
|
||||
cp -rf build ${outdir}/${name}batch-build_$(date +'%Y-%m-%d_%H-%M-%S')
|
||||
make clean
|
||||
done
|
||||
|
||||
@@ -1,70 +0,0 @@
|
||||
#!/usr/bin/env python
|
||||
#
|
||||
# Copyright 2012 Ettus Research LLC
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
|
||||
|
||||
import xml.etree.ElementTree as et
|
||||
import base64
|
||||
from optparse import OptionParser
|
||||
|
||||
|
||||
def main():
|
||||
parser = OptionParser()
|
||||
parser.add_option("-l", "--lvbitxfile", dest="lvbitxfile",
|
||||
help="donor labview fpga bitfile", metavar="LVBITXFILE")
|
||||
|
||||
parser.add_option("-b", "--bitfile", dest="bitfile",
|
||||
help="xilinx generated bitfile", metavar="BITFILE")
|
||||
|
||||
parser.add_option("-o", "--output", dest="outfile",
|
||||
help="output labview fpga bitfile", metavar="OUTFILE")
|
||||
|
||||
parser.add_option("-s", "--signature", dest="signature",
|
||||
help="output labview fpga bitfile signature", metavar="SIGNATURE",
|
||||
default="ABCDEFG")
|
||||
|
||||
|
||||
(options, args) = parser.parse_args()
|
||||
|
||||
tree = et.parse(options.lvbitxfile)
|
||||
root = tree.getroot()
|
||||
bs = root.find('Bitstream')
|
||||
if bs is None: return
|
||||
|
||||
print('Found "%s" tag in "%s"...' % (bs.tag, options.lvbitxfile))
|
||||
|
||||
print('Writing old bitfile content to "%s"...' % (options.bitfile+'.bak'))
|
||||
f_old = open(options.bitfile+'.bak', 'w')
|
||||
f_old.write(base64.b64decode(bs.text))
|
||||
f_old.close()
|
||||
|
||||
|
||||
print('Reading new bitfile "%s"...' % options.bitfile)
|
||||
f = open(options.bitfile, 'r')
|
||||
newbs = base64.b64encode(f.read())
|
||||
f.close()
|
||||
|
||||
|
||||
bs.text = newbs
|
||||
print('Saving new labview bitfile to "%s"...' % options.outfile)
|
||||
tree.write(options.outfile, xml_declaration=True, encoding='utf-8')
|
||||
|
||||
if __name__ == '__main__':
|
||||
try:
|
||||
main()
|
||||
except KeyboardInterrupt:
|
||||
pass
|
||||
+45
-76
@@ -2,8 +2,6 @@
|
||||
# Copyright 2012-2013 Ettus Research LLC
|
||||
#
|
||||
|
||||
# Uncomment following line to build with internal SRAM FIFOS instead of DRAM based FIFO's
|
||||
#OPTIONS += NO_DRAM_FIFOS=1
|
||||
# Uncomment the following lines to build radio's with no DSP's
|
||||
#OPTIONS += DELETE_DSP0=1
|
||||
#OPTIONS += DELETE_DSP1=1
|
||||
@@ -18,113 +16,84 @@ XGIGE_DEFS=ETH10G_PORT0=1 ETH10G_PORT1=1 BUILD_10G=1 $(OPTIONS)
|
||||
HYBRID_SRAM_DEFS=ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 $(OPTIONS)
|
||||
XGIGE_SRAM_DEFS=ETH10G_PORT0=1 ETH10G_PORT1=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 $(OPTIONS)
|
||||
|
||||
X300: X300_HGS X300_HG X300_XGS X300_XG
|
||||
|
||||
X310: X310_HGS X310_HG X310_XGS X310_XG
|
||||
|
||||
all: X300 X310
|
||||
find -name "*.twr" | xargs grep constraint | grep met
|
||||
|
||||
clean:
|
||||
rm -rf build*
|
||||
rm -rf build-*_*
|
||||
rm -rf build
|
||||
|
||||
#Build X300_HGS and X300_XGS
|
||||
X300: X300_HGS X300_XGS
|
||||
print_report = \
|
||||
echo "========================================================================"; \
|
||||
cat $(1) | grep "Design Summary:" -A 124; \
|
||||
echo "========================================================================"; \
|
||||
echo "Timing Summary:\n"; \
|
||||
cat $(1) | grep constraint | grep met | grep -v "*"; \
|
||||
echo "========================================================================";
|
||||
|
||||
#Build X310_HGS and X310_XGS
|
||||
X310: X310_HGS X310_XGS
|
||||
# post_build($1=Device, $2=Flavor)
|
||||
post_build = \
|
||||
@$(call print_report,build-$(1)_$(2)/build.log) \
|
||||
mkdir -p build; \
|
||||
echo "Exporting bitstream files..."; \
|
||||
cp build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
|
||||
cp build-$(1)_$(2)/x300.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
|
||||
echo "Generating LVBITX..."; \
|
||||
$(CREATE_LVBITX) --input-bin=build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
|
||||
cp -f x3x0_base.lvbitx build/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
|
||||
echo "Exporting logs..."; \
|
||||
cp build-$(1)_$(2)/build.log build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).log; \
|
||||
cp build-$(1)_$(2)/x300.twr build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).twr; \
|
||||
echo "\nDONE ... $(1)_$(2)\n";
|
||||
|
||||
#Build DRAM Hybrid images
|
||||
DRAM: X300_HG X310_HG
|
||||
|
||||
#Build X300_HGS and X310_HGS
|
||||
HGS: X300_HGS X310_HGS
|
||||
|
||||
#Build X300_HGS and X310_HGS
|
||||
XGS: X300_XGS X310_XGS
|
||||
|
||||
#1Gig on both ports
|
||||
X310_1G:
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(GIGE_DEFS) EXTRA_DEFS="$(GIGE_DEFS)"
|
||||
mkdir -p build
|
||||
cp build-X310/x300.bin build/usrp_x310_fpga_1G.bin
|
||||
cp build-X310/x300.bit build/usrp_x310_fpga_1G.bit
|
||||
$(CREATE_LVBITX) --input-bin=build-X310/x300.bin --output-lvbitx=build/usrp_x310_fpga_1G.lvbitx --device="USRP X310" x3x0_base.lvbitx
|
||||
cp -f x3x0_base.lvbitx build/x310.lvbitx_base
|
||||
|
||||
$(call post_build,X310,1G)
|
||||
|
||||
X300_1G:
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(GIGE_DEFS) EXTRA_DEFS="$(GIGE_DEFS)"
|
||||
mkdir -p build
|
||||
cp build-X300/x300.bin build/usrp_x300_fpga_1G.bin
|
||||
cp build-X300/x300.bit build/usrp_x300_fpga_1G.bit
|
||||
$(CREATE_LVBITX) --input-bin=build-X300/x300.bin --output-lvbitx=build/usrp_x300_fpga_1G.lvbitx --device="USRP X300" x3x0_base.lvbitx
|
||||
cp -f x3x0_base.lvbitx build/x300.lvbitx_base
|
||||
$(call post_build,X300,1G)
|
||||
|
||||
#1Gig on port0, 10Gig on port1
|
||||
X310_HG:
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)" FLOORPLAN="$(FLOORPLAN)"
|
||||
mkdir -p build
|
||||
cp build-X310_HG/x300.bin build/usrp_x310_fpga_HG.bin
|
||||
cp build-X310_HG/x300.bit build/usrp_x310_fpga_HG.bit
|
||||
$(CREATE_LVBITX) --input-bin=build-X310_HG/x300.bin --output-lvbitx=build/usrp_x310_fpga_HG.lvbitx --device="USRP X310" x3x0_base.lvbitx
|
||||
cp -f x3x0_base.lvbitx build/x310.lvbitx_base
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)"
|
||||
$(call post_build,X310,HG)
|
||||
|
||||
X300_HG:
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)" FLOORPLAN="$(FLOORPLAN)"
|
||||
mkdir -p build
|
||||
cp build-X300_HG/x300.bin build/usrp_x300_fpga_HG.bin
|
||||
cp build-X300_HG/x300.bit build/usrp_x300_fpga_HG.bit
|
||||
$(CREATE_LVBITX) --input-bin=build-X300_HG/x300.bin --output-lvbitx=build/usrp_x300_fpga_HG.lvbitx --device="USRP X300" x3x0_base.lvbitx
|
||||
cp -f x3x0_base.lvbitx build/x300.lvbitx_base
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_DEFS) EXTRA_DEFS="$(HYBRID_DEFS)"
|
||||
$(call post_build,X300,HG)
|
||||
|
||||
#10Gig on both ports
|
||||
X310_XG:
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)" FLOORPLAN="$(FLOORPLAN)"
|
||||
mkdir -p build
|
||||
cp build-X310_XG/x300.bin build/usrp_x310_fpga_XG.bin
|
||||
cp build-X310_XG/x300.bit build/usrp_x310_fpga_XG.bit
|
||||
$(CREATE_LVBITX) --input-bin=build-X310_XG/x300.bin --output-lvbitx=build/usrp_x310_fpga_XG.lvbitx --device="USRP X310" x3x0_base.lvbitx
|
||||
cp -f x3x0_base.lvbitx build/x310.lvbitx_base
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)"
|
||||
$(call post_build,X310,XG)
|
||||
|
||||
X300_XG:
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)" FLOORPLAN="$(FLOORPLAN)"
|
||||
mkdir -p build
|
||||
cp build-X300_XG/x300.bin build/usrp_x300_fpga_XG.bin
|
||||
cp build-X300_XG/x300.bit build/usrp_x300_fpga_XG.bit
|
||||
$(CREATE_LVBITX) --input-bin=build-X300_XG/x300.bin --output-lvbitx=build/usrp_x300_fpga_XG.lvbitx --device="USRP X300" x3x0_base.lvbitx
|
||||
cp -f x3x0_base.lvbitx build/x300.lvbitx_base
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_DEFS) EXTRA_DEFS="$(XGIGE_DEFS)"
|
||||
$(call post_build,X300,XG)
|
||||
|
||||
# 1Gig on port0, 10Gig on port1, SRAM Tx FIFO's
|
||||
X310_HGS:
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)" FLOORPLAN="$(FLOORPLAN)"
|
||||
mkdir -p build
|
||||
cp build-X310_HGS/x300.bin build/usrp_x310_fpga_HGS.bin
|
||||
cp build-X310_HGS/x300.bit build/usrp_x310_fpga_HGS.bit
|
||||
$(CREATE_LVBITX) --input-bin=build-X310_HGS/x300.bin --output-lvbitx=build/usrp_x310_fpga_HGS.lvbitx --device="USRP X310" x3x0_base.lvbitx
|
||||
cp -f x3x0_base.lvbitx build/x310.lvbitx_base
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)"
|
||||
$(call post_build,X310,HGS)
|
||||
|
||||
X300_HGS:
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)" FLOORPLAN="$(FLOORPLAN)"
|
||||
mkdir -p build
|
||||
cp build-X300_HGS/x300.bin build/usrp_x300_fpga_HGS.bin
|
||||
cp build-X300_HGS/x300.bit build/usrp_x300_fpga_HGS.bit
|
||||
$(CREATE_LVBITX) --input-bin=build-X300_HGS/x300.bin --output-lvbitx=build/usrp_x300_fpga_HGS.lvbitx --device="USRP X300" x3x0_base.lvbitx
|
||||
cp -f x3x0_base.lvbitx build/x300.lvbitx_base
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(HYBRID_SRAM_DEFS) EXTRA_DEFS="$(HYBRID_SRAM_DEFS)"
|
||||
$(call post_build,X300,HGS)
|
||||
|
||||
# 1Gig on both ports, SRAM Tx FIFO's
|
||||
X310_XGS:
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)" FLOORPLAN="$(FLOORPLAN)"
|
||||
mkdir -p build
|
||||
cp build-X310_XGS/x300.bin build/usrp_x310_fpga_XGS.bin
|
||||
cp build-X310_XGS/x300.bit build/usrp_x310_fpga_XGS.bit
|
||||
$(CREATE_LVBITX) --input-bin=build-X310_XGS/x300.bin --output-lvbitx=build/usrp_x310_fpga_XGS.lvbitx --device="USRP X310" x3x0_base.lvbitx
|
||||
cp -f x3x0_base.lvbitx build/x310.lvbitx_base
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K410T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)"
|
||||
$(call post_build,X310,XGS)
|
||||
|
||||
X300_XGS:
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)" FLOORPLAN="$(FLOORPLAN)"
|
||||
mkdir -p build
|
||||
cp build-X300_XGS/x300.bin build/usrp_x300_fpga_XGS.bin
|
||||
cp build-X300_XGS/x300.bit build/usrp_x300_fpga_XGS.bit
|
||||
$(CREATE_LVBITX) --input-bin=build-X300_XGS/x300.bin --output-lvbitx=build/usrp_x300_fpga_XGS.lvbitx --device="USRP X300" x3x0_base.lvbitx
|
||||
cp -f x3x0_base.lvbitx build/x300.lvbitx_base
|
||||
|
||||
make -f Makefile.x300.inc bin NAME=$@ DEVICE=XC7K325T $(XGIGE_SRAM_DEFS) EXTRA_DEFS="$(XGIGE_SRAM_DEFS)"
|
||||
$(call post_build,X300,XGS)
|
||||
|
||||
|
||||
.PHONY: all clean
|
||||
|
||||
+1
-1
@@ -141,7 +141,7 @@ module bus_int
|
||||
localparam RB_BIST = 8'd128;
|
||||
|
||||
|
||||
localparam COMPAT_MAJOR = 16'h0004;
|
||||
localparam COMPAT_MAJOR = 16'h0006;
|
||||
localparam COMPAT_MINOR = 16'h0000;
|
||||
|
||||
wire [31:0] set_data;
|
||||
|
||||
+3202
-3202
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
@@ -15,7 +15,7 @@
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
|
||||
@@ -53,16 +53,6 @@
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 8.000 ns HIGH 50% INPUT_JITTER 80.0ps;
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
|
||||
# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 175.000 MHz;
|
||||
|
||||
# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
|
||||
# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 125.000 MHz;
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "RESET" TIG;
|
||||
|
||||
@@ -55,8 +55,8 @@
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1___175.000______0.000______50.0______117.310____104.065
|
||||
// CLK_OUT2___125.000______0.000______50.0______125.031____104.065
|
||||
// CLK_OUT1___166.667______0.000______50.0______113.052_____96.948
|
||||
// CLK_OUT2___125.000______0.000______50.0______119.348_____96.948
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
@@ -109,12 +109,12 @@ module bus_clk_gen
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT (7),
|
||||
.CLKFBOUT_MULT (8),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKOUT0_DIVIDE (5),
|
||||
.CLKOUT0_DIVIDE (6),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_DIVIDE (7),
|
||||
.CLKOUT1_DIVIDE (8),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKIN1_PERIOD (8.000),
|
||||
|
||||
@@ -54,8 +54,8 @@
|
||||
// "Output Output Phase Duty Pk-to-Pk Phase"
|
||||
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
|
||||
//----------------------------------------------------------------------------
|
||||
// CLK_OUT1___175.000______0.000______50.0______117.310____104.065
|
||||
// CLK_OUT2___125.000______0.000______50.0______125.031____104.065
|
||||
// CLK_OUT1___166.667______0.000______50.0______113.052_____96.948
|
||||
// CLK_OUT2___125.000______0.000______50.0______119.348_____96.948
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// "Input Clock Freq (MHz) Input Jitter (UI)"
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
##############################################################
|
||||
#
|
||||
# Xilinx Core Generator version 14.4
|
||||
# Date: Thu Sep 19 21:49:46 2013
|
||||
# Xilinx Core Generator version 14.6
|
||||
# Date: Mon Apr 28 17:58:14 2014
|
||||
#
|
||||
##############################################################
|
||||
#
|
||||
@@ -70,7 +70,7 @@ CSET clkin2_jitter_ps=100.0
|
||||
CSET clkin2_ui_jitter=0.010
|
||||
CSET clkout1_drives=BUFG
|
||||
CSET clkout1_requested_duty_cycle=50.000
|
||||
CSET clkout1_requested_out_freq=175
|
||||
CSET clkout1_requested_out_freq=166.667
|
||||
CSET clkout1_requested_phase=0.000
|
||||
CSET clkout2_drives=BUFG
|
||||
CSET clkout2_requested_duty_cycle=50.000
|
||||
@@ -148,16 +148,16 @@ CSET jitter_options=UI
|
||||
CSET jitter_sel=No_Jitter
|
||||
CSET locked_port=LOCKED
|
||||
CSET mmcm_bandwidth=OPTIMIZED
|
||||
CSET mmcm_clkfbout_mult_f=7
|
||||
CSET mmcm_clkfbout_mult_f=8
|
||||
CSET mmcm_clkfbout_phase=0.000
|
||||
CSET mmcm_clkfbout_use_fine_ps=false
|
||||
CSET mmcm_clkin1_period=8.000
|
||||
CSET mmcm_clkin2_period=10.0
|
||||
CSET mmcm_clkout0_divide_f=5
|
||||
CSET mmcm_clkout0_divide_f=6
|
||||
CSET mmcm_clkout0_duty_cycle=0.500
|
||||
CSET mmcm_clkout0_phase=0.000
|
||||
CSET mmcm_clkout0_use_fine_ps=false
|
||||
CSET mmcm_clkout1_divide=7
|
||||
CSET mmcm_clkout1_divide=8
|
||||
CSET mmcm_clkout1_duty_cycle=0.500
|
||||
CSET mmcm_clkout1_phase=0.000
|
||||
CSET mmcm_clkout1_use_fine_ps=false
|
||||
@@ -266,4 +266,4 @@ CSET use_status=false
|
||||
MISC pkg_timestamp=2012-05-10T12:44:55Z
|
||||
# END Extra information
|
||||
GENERATE
|
||||
# CRC: 1d4d384f
|
||||
# CRC: 215f8243
|
||||
|
||||
@@ -9,28 +9,21 @@
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
|
||||
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="bus_clk_gen/example_design/bus_clk_gen_exdes.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="bus_clk_gen/example_design/bus_clk_gen_exdes.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<file xil_pn:name="bus_clk_gen.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="bus_clk_gen.v" xil_pn:type="FILE_VERILOG">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
@@ -46,7 +39,7 @@
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@@ -149,9 +142,9 @@
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|bus_clk_gen_exdes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="bus_clk_gen/example_design/bus_clk_gen_exdes.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/bus_clk_gen_exdes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Module|bus_clk_gen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="bus_clk_gen.v" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/bus_clk_gen" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@@ -205,7 +198,7 @@
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="bus_clk_gen_exdes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="bus_clk_gen" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
@@ -218,10 +211,10 @@
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="bus_clk_gen_exdes_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="bus_clk_gen_exdes_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="bus_clk_gen_exdes_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="bus_clk_gen_exdes_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="bus_clk_gen_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="bus_clk_gen_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="bus_clk_gen_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="bus_clk_gen_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@@ -345,13 +338,15 @@
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-09-19T14:50:10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="484FFD4A79488674A3CE815213589584" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-04-28T10:58:39" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="864AFA86C959B32B2CD711C532A10895" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
<bindings>
|
||||
<binding xil_pn:location="/bus_clk_gen" xil_pn:name="bus_clk_gen.ucf"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: July 25, 2012
|
||||
Release Date: June 19, 2013
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
@@ -74,6 +74,8 @@ solution. For the latest core updates, see the product page at:
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with example design becoming core top in planAhead
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
|
||||
@@ -113,6 +115,7 @@ designs that do not follow specified guidelines.
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
@@ -133,7 +136,7 @@ Date By Version Description
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
|
||||
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: July 25, 2012
|
||||
Release Date: June 19, 2013
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
@@ -74,6 +74,8 @@ solution. For the latest core updates, see the product page at:
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with example design becoming core top in planAhead
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
|
||||
@@ -113,6 +115,7 @@ designs that do not follow specified guidelines.
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
@@ -133,7 +136,7 @@ Date By Version Description
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
|
||||
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
|
||||
@@ -7,7 +7,7 @@
|
||||
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
|
||||
CHANGE LOG for LogiCORE Clocking Wizard V3.6
|
||||
|
||||
Release Date: July 25, 2012
|
||||
Release Date: June 19, 2013
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Table of Contents
|
||||
@@ -81,8 +81,10 @@ solution. For the latest core updates, see the product page at:
|
||||
|
||||
4.1 ISE
|
||||
|
||||
Resolved issue with example design becoming core top in planAhead
|
||||
|
||||
Resolved issue with Virtex6 MMCM instantiation for VHDL project
|
||||
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
|
||||
Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A>
|
||||
|
||||
................................................................................
|
||||
|
||||
@@ -120,6 +122,7 @@ designs that do not follow specified guidelines.
|
||||
|
||||
Date By Version Description
|
||||
================================================================================
|
||||
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
|
||||
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
|
||||
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
|
||||
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
|
||||
@@ -140,7 +143,7 @@ Date By Version Description
|
||||
|
||||
8. LEGAL DISCLAIMER
|
||||
|
||||
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
|
||||
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
|
||||
This file contains confidential and proprietary information
|
||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
|
||||
@@ -53,16 +53,6 @@
|
||||
NET "CLK_IN1" TNM_NET = "CLK_IN1";
|
||||
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 8.000 ns HIGH 50% INPUT_JITTER 80.0ps;
|
||||
|
||||
# Derived clock periods. These are commented out because they are
|
||||
# automatically propogated by the tools
|
||||
# However, if you'd like to use them for module level testing, you
|
||||
# can copy them into your module level timing checks
|
||||
#-----------------------------------------------------------------
|
||||
# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
|
||||
# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 175.000 MHz;
|
||||
|
||||
# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
|
||||
# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 125.000 MHz;
|
||||
|
||||
# FALSE PATH constraints
|
||||
PIN "COUNTER_RESET" TIG;
|
||||
|
||||
@@ -88,11 +88,11 @@ wire [2:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
real period1;
|
||||
real ref_period1;
|
||||
localparam ref_period1_clkin1 = (8.000*1*5*1000/7);
|
||||
localparam ref_period1_clkin1 = (8.000*1*6*1000/8);
|
||||
time prev_rise1;
|
||||
real period2;
|
||||
real ref_period2;
|
||||
localparam ref_period2_clkin1 = (8.000*1*7*1000/7);
|
||||
localparam ref_period2_clkin1 = (8.000*1*8*1000/8);
|
||||
time prev_rise2;
|
||||
|
||||
|
||||
|
||||
@@ -88,11 +88,11 @@ wire [2:1] CLK_OUT;
|
||||
//Freq Check using the M & D values setting and actual Frequency generated
|
||||
real period1;
|
||||
real ref_period1;
|
||||
localparam ref_period1_clkin1 = (8.000*1*5*1000/7);
|
||||
localparam ref_period1_clkin1 = (8.000*1*6*1000/8);
|
||||
time prev_rise1;
|
||||
real period2;
|
||||
real ref_period2;
|
||||
localparam ref_period2_clkin1 = (8.000*1*7*1000/7);
|
||||
localparam ref_period2_clkin1 = (8.000*1*8*1000/8);
|
||||
time prev_rise2;
|
||||
|
||||
reg [13:0] timeout_counter = 14'b00000000000000;
|
||||
|
||||
@@ -40,10 +40,6 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/example_design/bus_clk_gen_exdes.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/doc/clk_wiz_ds709.pdf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
@@ -52,10 +48,6 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/example_design/bus_clk_gen_exdes.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/implement/implement.bat
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
|
||||
incr fcount
|
||||
@@ -120,6 +112,10 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen.
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen.ucf
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
|
||||
incr fcount
|
||||
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen.v
|
||||
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
|
||||
incr fcount
|
||||
|
||||
+30
-14
@@ -285,7 +285,7 @@ module x300
|
||||
|
||||
bus_clk_gen bus_clk_gen (
|
||||
.CLK_IN1(fpga_clk125), //Input Clock: 125MHz Clock from STC3
|
||||
.CLK_OUT1(bus_clk), //Output Clock 1: 175MHz
|
||||
.CLK_OUT1(bus_clk), //Output Clock 1: 166.666667MHz
|
||||
.CLK_OUT2(ioport2_clk), //Output Clock 2: 125MHz
|
||||
.RESET(1'b0),
|
||||
.LOCKED(bus_clk_locked));
|
||||
@@ -555,10 +555,10 @@ module x300
|
||||
localparam TX_STREAM_START_IDX = `LVFPGA_IFACE_TX_DMA_INDEX;
|
||||
localparam RX_STREAM_START_IDX = `LVFPGA_IFACE_RX_DMA_INDEX;
|
||||
|
||||
wire [DMA_STREAM_WIDTH-1:0] dmatx_tdata, dmarx_tdata;
|
||||
wire dmatx_tvalid, dmarx_tvalid;
|
||||
wire dmatx_tlast, dmarx_tlast;
|
||||
wire dmatx_tready, dmarx_tready;
|
||||
wire [DMA_STREAM_WIDTH-1:0] dmatx_tdata, dmarx_tdata, pcii_tdata, pcio_tdata;
|
||||
wire dmatx_tvalid, dmarx_tvalid, pcii_tvalid, pcio_tvalid;
|
||||
wire dmatx_tlast, dmarx_tlast, pcii_tlast, pcio_tlast;
|
||||
wire dmatx_tready, dmarx_tready, pcii_tready, pcio_tready;
|
||||
|
||||
wire [IOP2_MSG_WIDTH-1:0] o_iop2_msg_tdata, i_iop2_msg_tdata;
|
||||
wire o_iop2_msg_tvalid, o_iop2_msg_tlast, o_iop2_msg_tready;
|
||||
@@ -725,10 +725,26 @@ module x300
|
||||
.regi_tready(i_iop2_msg_tready),
|
||||
|
||||
//Misc
|
||||
.misc_status({31'h0, aStc3Gpio7}),
|
||||
.misc_status({15'h0, aStc3Gpio7}),
|
||||
.debug()
|
||||
);
|
||||
|
||||
// The PCIe logic will tend to stay close to the physical IoPort2 pins
|
||||
// so add an additional stage of pipelining to give the tool more routing
|
||||
// slack. This is significantly help timing closure.
|
||||
|
||||
axi_fifo_short #(.WIDTH(DMA_STREAM_WIDTH+1)) pcii_pipeline_srl (
|
||||
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.i_tdata({dmatx_tlast, dmatx_tdata}), .i_tvalid(dmatx_tvalid), .i_tready(dmatx_tready),
|
||||
.o_tdata({pcii_tlast, pcii_tdata}), .o_tvalid(pcii_tvalid), .o_tready(pcii_tready),
|
||||
.space(), .occupied());
|
||||
|
||||
axi_fifo_short #(.WIDTH(DMA_STREAM_WIDTH+1)) pcio_pipeline_srl (
|
||||
.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
|
||||
.i_tdata({pcio_tlast, pcio_tdata}), .i_tvalid(pcio_tvalid), .i_tready(pcio_tready),
|
||||
.o_tdata({dmarx_tlast, dmarx_tdata}), .o_tvalid(dmarx_tvalid), .o_tready(dmarx_tready),
|
||||
.space(), .occupied());
|
||||
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Configure Ethernet PHY clocking
|
||||
@@ -1936,14 +1952,14 @@ module x300
|
||||
.i_iop2_msg_tlast (i_iop2_msg_tlast),
|
||||
.i_iop2_msg_tready (i_iop2_msg_tready),
|
||||
// PCIe DMA Data
|
||||
.pcio_tdata (dmarx_tdata),
|
||||
.pcio_tlast (dmarx_tlast),
|
||||
.pcio_tvalid (dmarx_tvalid),
|
||||
.pcio_tready (dmarx_tready),
|
||||
.pcii_tdata (dmatx_tdata),
|
||||
.pcii_tlast (dmatx_tlast),
|
||||
.pcii_tvalid (dmatx_tvalid),
|
||||
.pcii_tready (dmatx_tready)
|
||||
.pcio_tdata (pcio_tdata),
|
||||
.pcio_tlast (pcio_tlast),
|
||||
.pcio_tvalid (pcio_tvalid),
|
||||
.pcio_tready (pcio_tready),
|
||||
.pcii_tdata (pcii_tdata),
|
||||
.pcii_tlast (pcii_tlast),
|
||||
.pcii_tvalid (pcii_tvalid),
|
||||
.pcii_tready (pcii_tready)
|
||||
);
|
||||
|
||||
|
||||
|
||||
+41
-19
@@ -86,7 +86,7 @@ module x300_pcie_int #(
|
||||
//---------------------------------------------------------
|
||||
// Misc
|
||||
//---------------------------------------------------------
|
||||
input [31:0] misc_status,
|
||||
input [15:0] misc_status,
|
||||
output [127:0] debug
|
||||
);
|
||||
|
||||
@@ -143,11 +143,13 @@ module x300_pcie_int #(
|
||||
//
|
||||
//*******************************************************************************
|
||||
|
||||
wire [NUM_TX_STREAMS-1:0] dmatx_clear, dmatx_samp_stb, dmatx_pkt_stb, dmatx_error;
|
||||
wire [NUM_TX_STREAMS-1:0] dmatx_clear, dmatx_enabled;
|
||||
wire [NUM_TX_STREAMS-1:0] dmatx_samp_stb, dmatx_pkt_stb, dmatx_busy, dmatx_error;
|
||||
wire [(NUM_TX_STREAMS*DMA_FRAME_SIZE_WIDTH)-1:0] dmatx_frame_size;
|
||||
wire [(NUM_TX_STREAMS*3)-1:0] dmatx_swap;
|
||||
|
||||
wire [NUM_RX_STREAMS-1:0] dmarx_clear, dmarx_samp_stb, dmarx_pkt_stb, dmarx_error;
|
||||
wire [NUM_RX_STREAMS-1:0] dmarx_clear, dmarx_enabled;
|
||||
wire [NUM_RX_STREAMS-1:0] dmarx_samp_stb, dmarx_pkt_stb, dmarx_busy, dmarx_error;
|
||||
wire [(NUM_RX_STREAMS*DMA_FRAME_SIZE_WIDTH)-1:0] dmarx_frame_size;
|
||||
wire [(NUM_TX_STREAMS*3)-1:0] dmarx_swap;
|
||||
wire [DMA_STREAM_WIDTH-1:0] dmarx_header;
|
||||
@@ -189,11 +191,17 @@ module x300_pcie_int #(
|
||||
);
|
||||
assign regi_tlast = regi_tvalid;
|
||||
|
||||
pcie_basic_regs basic_regs (
|
||||
wire [15:0] fpga_status;
|
||||
assign fpga_status[7:0] = {|(dmatx_error), 1'b0, dmatx_enabled};
|
||||
assign fpga_status[15:8] = {|(dmarx_error), 1'b0, dmarx_enabled};
|
||||
|
||||
pcie_basic_regs #(
|
||||
.SIGNATURE(32'h58333030 /*ASCII:"X300"*/), .CLK_FREQ(32'd166666667 /*bus_clk = 166.666667MHz*/)
|
||||
) basic_regs (
|
||||
.clk(bus_clk), .reset(bus_rst),
|
||||
.regi_tdata(basic_regi_tdata), .regi_tvalid(basic_regi_tvalid), .regi_tready(basic_regi_tready),
|
||||
.rego_tdata(basic_rego_tdata), .rego_tvalid(basic_rego_tvalid), .rego_tready(basic_rego_tready),
|
||||
.misc_status(misc_status)
|
||||
.misc_status({fpga_status, misc_status})
|
||||
);
|
||||
|
||||
pcie_dma_ctrl #(
|
||||
@@ -203,8 +211,9 @@ module x300_pcie_int #(
|
||||
.clk(bus_clk), .reset(bus_rst),
|
||||
.regi_tdata(dmatx_regi_tdata), .regi_tvalid(dmatx_regi_tvalid), .regi_tready(dmatx_regi_tready),
|
||||
.rego_tdata(dmatx_rego_tdata), .rego_tvalid(dmatx_rego_tvalid), .rego_tready(dmatx_rego_tready),
|
||||
.set_clear(dmatx_clear), .set_frame_size(dmatx_frame_size), .sample_stb(dmatx_samp_stb), .packet_stb(dmatx_pkt_stb),
|
||||
.swap_lanes(dmatx_swap), .stream_err(dmatx_error), .rtr_sid(8'h00), .rtr_dst()
|
||||
.set_enabled(dmatx_enabled), .set_clear(dmatx_clear), .set_frame_size(dmatx_frame_size),
|
||||
.sample_stb(dmatx_samp_stb), .packet_stb(dmatx_pkt_stb),
|
||||
.swap_lanes(dmatx_swap), .stream_busy(dmatx_busy), .stream_err(dmatx_error), .rtr_sid(8'h00), .rtr_dst()
|
||||
);
|
||||
|
||||
pcie_dma_ctrl #(
|
||||
@@ -214,8 +223,9 @@ module x300_pcie_int #(
|
||||
.clk(bus_clk), .reset(bus_rst),
|
||||
.regi_tdata(dmarx_regi_tdata), .regi_tvalid(dmarx_regi_tvalid), .regi_tready(dmarx_regi_tready),
|
||||
.rego_tdata(dmarx_rego_tdata), .rego_tvalid(dmarx_rego_tvalid), .rego_tready(dmarx_rego_tready),
|
||||
.set_clear(dmarx_clear), .set_frame_size(dmarx_frame_size), .sample_stb(dmarx_samp_stb), .packet_stb(dmarx_pkt_stb),
|
||||
.swap_lanes(dmarx_swap), .stream_err(dmarx_error), .rtr_sid(dmarx_header[7:0]), .rtr_dst(dmarx_pkt_dest)
|
||||
.set_enabled(dmarx_enabled), .set_clear(dmarx_clear), .set_frame_size(dmarx_frame_size),
|
||||
.sample_stb(dmarx_samp_stb), .packet_stb(dmarx_pkt_stb),
|
||||
.swap_lanes(dmarx_swap), .stream_busy(dmarx_busy), .stream_err(dmarx_error), .rtr_sid(dmarx_header[7:0]), .rtr_dst(dmarx_pkt_dest)
|
||||
);
|
||||
//
|
||||
//*******************************************************************************
|
||||
@@ -223,9 +233,9 @@ module x300_pcie_int #(
|
||||
//*******************************************************************************
|
||||
// TX DMA Datapath
|
||||
//
|
||||
wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_bclk, dmatx_tdata_trun, dmatx_tdata_gt, dmatx_tdata_swap;
|
||||
wire [NUM_TX_STREAMS-1:0] dmatx_tvalid_bclk, dmatx_tvalid_trun, dmatx_tvalid_gt;
|
||||
wire [NUM_TX_STREAMS-1:0] dmatx_tready_bclk, dmatx_tready_trun, dmatx_tready_gt;
|
||||
wire [(NUM_TX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmatx_tdata_bclk, dmatx_tdata_in, dmatx_tdata_trun, dmatx_tdata_gt, dmatx_tdata_swap;
|
||||
wire [NUM_TX_STREAMS-1:0] dmatx_tvalid_bclk, dmatx_tvalid_in, dmatx_tvalid_trun, dmatx_tvalid_gt;
|
||||
wire [NUM_TX_STREAMS-1:0] dmatx_tready_bclk, dmatx_tready_in, dmatx_tready_trun, dmatx_tready_gt;
|
||||
wire [NUM_TX_STREAMS-1:0] dmatx_tlast_trun, dmatx_tlast_gt;
|
||||
|
||||
wire [DMA_STREAM_WIDTH-1:0] dmatx_tdata_mux;
|
||||
@@ -240,13 +250,19 @@ module x300_pcie_int #(
|
||||
.o_aclk(bus_clk), .o_tdata(`GET_DMA_BUS(dmatx_tdata_bclk,i)), .o_tvalid(dmatx_tvalid_bclk[i]), .o_tready(dmatx_tready_bclk[i])
|
||||
);
|
||||
|
||||
pcie_lossy_samp_gate tx_samp_gate (
|
||||
.i_tdata(`GET_DMA_BUS(dmatx_tdata_bclk,i)), .i_tvalid(dmatx_tvalid_bclk[i]), .i_tready(dmatx_tready_bclk[i]),
|
||||
.o_tdata(`GET_DMA_BUS(dmatx_tdata_in,i)), .o_tvalid(dmatx_tvalid_in[i]), .o_tready(dmatx_tready_in[i]),
|
||||
.drop(~dmatx_enabled[i]), .dropping(dmatx_busy[i])
|
||||
);
|
||||
|
||||
data_swapper_64 tx_data_swapper (
|
||||
.swap_lanes(`GET_SWAP_BUS(dmatx_swap,i)), .i_tdata(`GET_DMA_BUS(dmatx_tdata_bclk,i)), .o_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i))
|
||||
.swap_lanes(`GET_SWAP_BUS(dmatx_swap,i)), .i_tdata(`GET_DMA_BUS(dmatx_tdata_in,i)), .o_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i))
|
||||
);
|
||||
|
||||
cvita_dechunker tx_dma_dechunker (
|
||||
.clk(bus_clk), .reset(bus_rst), .clear(dmatx_clear[i]), .frame_size(`GET_FSIZE_BUS(dmatx_frame_size, i)),
|
||||
.i_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i)), .i_tvalid(dmatx_tvalid_bclk[i]), .i_tready(dmatx_tready_bclk[i]),
|
||||
.i_tdata(`GET_DMA_BUS(dmatx_tdata_swap,i)), .i_tvalid(dmatx_tvalid_in[i]), .i_tready(dmatx_tready_in[i]),
|
||||
.o_tdata(`GET_DMA_BUS(dmatx_tdata_trun,i)), .o_tlast(dmatx_tlast_trun[i]), .o_tvalid(dmatx_tvalid_trun[i]), .o_tready(dmatx_tready_trun[i]),
|
||||
.error(dmatx_error[i])
|
||||
);
|
||||
@@ -286,10 +302,10 @@ module x300_pcie_int #(
|
||||
//*******************************************************************************
|
||||
// RX DMA Datapath
|
||||
//
|
||||
wire [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_bclk, dmarx_tdata_pad, dmarx_tdata_swap;
|
||||
wire [NUM_RX_STREAMS-1:0] dmarx_tvalid_bclk, dmarx_tvalid_pad;
|
||||
wire [NUM_RX_STREAMS-1:0] dmarx_tready_bclk, dmarx_tready_pad;
|
||||
wire [NUM_RX_STREAMS-1:0] dmarx_tlast_bclk, dmarx_tlast_pad;
|
||||
wire [(NUM_RX_STREAMS*DMA_STREAM_WIDTH)-1:0] dmarx_tdata_bclk, dmarx_tdata_pad, dmarx_tdata_swap, dmarx_tdata_out;
|
||||
wire [NUM_RX_STREAMS-1:0] dmarx_tvalid_bclk, dmarx_tvalid_pad, dmarx_tvalid_out;
|
||||
wire [NUM_RX_STREAMS-1:0] dmarx_tready_bclk, dmarx_tready_pad, dmarx_tready_out;
|
||||
wire [NUM_RX_STREAMS-1:0] dmarx_tlast_bclk, dmarx_tlast_pad, dmarx_tlast_out;
|
||||
|
||||
wire [DMA_STREAM_WIDTH-1:0] dmarx_tdata_mux;
|
||||
wire dmarx_tvalid_mux, dmarx_tlast_mux, dmarx_tready_mux;
|
||||
@@ -331,9 +347,15 @@ module x300_pcie_int #(
|
||||
.swap_lanes(`GET_SWAP_BUS(dmarx_swap,j)), .i_tdata(`GET_DMA_BUS(dmarx_tdata_pad,j)), .o_tdata(`GET_DMA_BUS(dmarx_tdata_swap,j))
|
||||
);
|
||||
|
||||
pcie_lossy_samp_gate rx_samp_gate (
|
||||
.i_tdata(`GET_DMA_BUS(dmarx_tdata_swap,j)), .i_tvalid(dmarx_tvalid_pad[j]), .i_tready(dmarx_tready_pad[j]),
|
||||
.o_tdata(`GET_DMA_BUS(dmarx_tdata_out,j)), .o_tvalid(dmarx_tvalid_out[j]), .o_tready(dmarx_tready_out[j]),
|
||||
.drop(~dmarx_enabled[j]), .dropping(dmarx_busy[j])
|
||||
);
|
||||
|
||||
axi_fifo_2clk #(.WIDTH(DMA_STREAM_WIDTH), .SIZE(DMA_CLK_XING_FIFO_SIZE)) rx_dma_clock_crossing_fifo (
|
||||
.reset(bus_rst),
|
||||
.i_aclk(bus_clk), .i_tdata(`GET_DMA_BUS(dmarx_tdata_swap,j)), .i_tvalid(dmarx_tvalid_pad[j]), .i_tready(dmarx_tready_pad[j]),
|
||||
.i_aclk(bus_clk), .i_tdata(`GET_DMA_BUS(dmarx_tdata_out,j)), .i_tvalid(dmarx_tvalid_out[j]), .i_tready(dmarx_tready_out[j]),
|
||||
.o_aclk(ioport2_clk), .o_tdata(`GET_DMA_BUS(dmarx_tdata_iop2,j)), .o_tvalid(dmarx_tvalid_iop2[j]), .o_tready(dmarx_tready_iop2[j])
|
||||
);
|
||||
end
|
||||
|
||||
@@ -215,7 +215,7 @@ module x300_pcie_int_tb();
|
||||
TEST_CASE();
|
||||
usr_regport_request(READ, 20'hC, 32'h0);
|
||||
usr_regport_response();
|
||||
`CHECK_TRUE((pcie_usr_data == 175000000), "Verify counter frequency register");
|
||||
`CHECK_TRUE((pcie_usr_data == 166666667), "Verify counter frequency register");
|
||||
|
||||
TEST_CASE();
|
||||
usr_regport_request(WRITE, 20'h10, 32'hDEAD);
|
||||
|
||||
Reference in New Issue
Block a user