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fpga: updating b200 and x300 FPGA source code for latest images

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Original-commit: 00711ba213dde8aa0a099d2b18d3da0a33e6af79
This commit is contained in:
Ben Hilburn
2014-05-14 11:42:19 -07:00
parent 8f1cfd55b1
commit 5a525c84f5
71 changed files with 117080 additions and 4101 deletions
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top/x300/coregen/bus_clk_gen.xco
+7 -7
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@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Thu Sep 19 21:49:46 2013
# Xilinx Core Generator version 14.6
# Date: Mon Apr 28 17:58:14 2014
#
##############################################################
#
@@ -70,7 +70,7 @@ CSET clkin2_jitter_ps=100.0
CSET clkin2_ui_jitter=0.010
CSET clkout1_drives=BUFG
CSET clkout1_requested_duty_cycle=50.000
CSET clkout1_requested_out_freq=175
CSET clkout1_requested_out_freq=166.667
CSET clkout1_requested_phase=0.000
CSET clkout2_drives=BUFG
CSET clkout2_requested_duty_cycle=50.000
@@ -148,16 +148,16 @@ CSET jitter_options=UI
CSET jitter_sel=No_Jitter
CSET locked_port=LOCKED
CSET mmcm_bandwidth=OPTIMIZED
CSET mmcm_clkfbout_mult_f=7
CSET mmcm_clkfbout_mult_f=8
CSET mmcm_clkfbout_phase=0.000
CSET mmcm_clkfbout_use_fine_ps=false
CSET mmcm_clkin1_period=8.000
CSET mmcm_clkin2_period=10.0
CSET mmcm_clkout0_divide_f=5
CSET mmcm_clkout0_divide_f=6
CSET mmcm_clkout0_duty_cycle=0.500
CSET mmcm_clkout0_phase=0.000
CSET mmcm_clkout0_use_fine_ps=false
CSET mmcm_clkout1_divide=7
CSET mmcm_clkout1_divide=8
CSET mmcm_clkout1_duty_cycle=0.500
CSET mmcm_clkout1_phase=0.000
CSET mmcm_clkout1_use_fine_ps=false
@@ -266,4 +266,4 @@ CSET use_status=false
MISC pkg_timestamp=2012-05-10T12:44:55Z
# END Extra information
GENERATE
# CRC: 1d4d384f
# CRC: 215f8243