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fpga: updating b200 and x300 FPGA source code for latest images

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Original-commit: 00711ba213dde8aa0a099d2b18d3da0a33e6af79
This commit is contained in:
Ben Hilburn
2014-05-14 11:42:19 -07:00
parent 8f1cfd55b1
commit 5a525c84f5
71 changed files with 117080 additions and 4101 deletions
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top/x300/coregen/bus_clk_gen/clk_wiz_v3_6_readme.txt
+5 -2
View File
@@ -1,6 +1,6 @@
CHANGE LOG for LogiCORE Clocking Wizard V3.6
Release Date: July 25, 2012
Release Date: June 19, 2013
--------------------------------------------------------------------------------
Table of Contents
@@ -74,6 +74,8 @@ solution. For the latest core updates, see the product page at:
4.1 ISE
Resolved issue with example design becoming core top in planAhead
Resolved issue with Virtex6 MMCM instantiation for VHDL project
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
@@ -113,6 +115,7 @@ designs that do not follow specified guidelines.
Date By Version Description
================================================================================
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
@@ -133,7 +136,7 @@ Date By Version Description
8. LEGAL DISCLAIMER
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_readme.txt
+5 -2
View File
@@ -1,6 +1,6 @@
CHANGE LOG for LogiCORE Clocking Wizard V3.6
Release Date: July 25, 2012
Release Date: June 19, 2013
--------------------------------------------------------------------------------
Table of Contents
@@ -74,6 +74,8 @@ solution. For the latest core updates, see the product page at:
4.1 ISE
Resolved issue with example design becoming core top in planAhead
Resolved issue with Virtex6 MMCM instantiation for VHDL project
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
@@ -113,6 +115,7 @@ designs that do not follow specified guidelines.
Date By Version Description
================================================================================
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
@@ -133,7 +136,7 @@ Date By Version Description
8. LEGAL DISCLAIMER
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_vinfo.html
+6 -3
View File
@@ -7,7 +7,7 @@
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
CHANGE LOG for LogiCORE Clocking Wizard V3.6
Release Date: July 25, 2012
Release Date: June 19, 2013
--------------------------------------------------------------------------------
Table of Contents
@@ -81,8 +81,10 @@ solution. For the latest core updates, see the product page at:
4.1 ISE
Resolved issue with example design becoming core top in planAhead
Resolved issue with Virtex6 MMCM instantiation for VHDL project
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A>
................................................................................
@@ -120,6 +122,7 @@ designs that do not follow specified guidelines.
Date By Version Description
================================================================================
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
@@ -140,7 +143,7 @@ Date By Version Description
8. LEGAL DISCLAIMER
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
top/x300/coregen/bus_clk_gen/example_design/bus_clk_gen_exdes.ucf
-10
View File
@@ -53,16 +53,6 @@
NET "CLK_IN1" TNM_NET = "CLK_IN1";
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 8.000 ns HIGH 50% INPUT_JITTER 80.0ps;
# Derived clock periods. These are commented out because they are
# automatically propogated by the tools
# However, if you'd like to use them for module level testing, you
# can copy them into your module level timing checks
#-----------------------------------------------------------------
# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 175.000 MHz;
# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 125.000 MHz;
# FALSE PATH constraints
PIN "COUNTER_RESET" TIG;
top/x300/coregen/bus_clk_gen/simulation/bus_clk_gen_tb.v
+2 -2
View File
@@ -88,11 +88,11 @@ wire [2:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (8.000*1*5*1000/7);
localparam ref_period1_clkin1 = (8.000*1*6*1000/8);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (8.000*1*7*1000/7);
localparam ref_period2_clkin1 = (8.000*1*8*1000/8);
time prev_rise2;
top/x300/coregen/bus_clk_gen/simulation/timing/bus_clk_gen_tb.v
+2 -2
View File
@@ -88,11 +88,11 @@ wire [2:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (8.000*1*5*1000/7);
localparam ref_period1_clkin1 = (8.000*1*6*1000/8);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (8.000*1*7*1000/7);
localparam ref_period2_clkin1 = (8.000*1*8*1000/8);
time prev_rise2;
reg [13:0] timeout_counter = 14'b00000000000000;