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fpga: updating b200 and x300 FPGA source code for latest images

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Original-commit: 00711ba213dde8aa0a099d2b18d3da0a33e6af79
This commit is contained in:
Ben Hilburn
2014-05-14 11:42:19 -07:00
parent 8f1cfd55b1
commit 5a525c84f5
71 changed files with 117080 additions and 4101 deletions
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top/x300/coregen/bootram.coe
+3202 -3202
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top/x300/coregen/bootram.ngc
-3
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top/x300/coregen/bus_clk_gen.gise
+1 -1
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@@ -15,7 +15,7 @@
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
top/x300/coregen/bus_clk_gen.ucf
-10
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@@ -53,16 +53,6 @@
NET "CLK_IN1" TNM_NET = "CLK_IN1";
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 8.000 ns HIGH 50% INPUT_JITTER 80.0ps;
# Derived clock periods. These are commented out because they are
# automatically propogated by the tools
# However, if you'd like to use them for module level testing, you
# can copy them into your module level timing checks
#-----------------------------------------------------------------
# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 175.000 MHz;
# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 125.000 MHz;
# FALSE PATH constraints
PIN "RESET" TIG;
top/x300/coregen/bus_clk_gen.v
+5 -5
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@@ -55,8 +55,8 @@
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___175.000______0.000______50.0______117.310____104.065
// CLK_OUT2___125.000______0.000______50.0______125.031____104.065
// CLK_OUT1___166.667______0.000______50.0______113.052_____96.948
// CLK_OUT2___125.000______0.000______50.0______119.348_____96.948
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
@@ -109,12 +109,12 @@ module bus_clk_gen
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (7),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (5),
.CLKOUT0_DIVIDE (6),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (7),
.CLKOUT1_DIVIDE (8),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (8.000),
top/x300/coregen/bus_clk_gen.veo
+2 -2
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@@ -54,8 +54,8 @@
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___175.000______0.000______50.0______117.310____104.065
// CLK_OUT2___125.000______0.000______50.0______125.031____104.065
// CLK_OUT1___166.667______0.000______50.0______113.052_____96.948
// CLK_OUT2___125.000______0.000______50.0______119.348_____96.948
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
top/x300/coregen/bus_clk_gen.xco
+7 -7
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@@ -1,7 +1,7 @@
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Thu Sep 19 21:49:46 2013
# Xilinx Core Generator version 14.6
# Date: Mon Apr 28 17:58:14 2014
#
##############################################################
#
@@ -70,7 +70,7 @@ CSET clkin2_jitter_ps=100.0
CSET clkin2_ui_jitter=0.010
CSET clkout1_drives=BUFG
CSET clkout1_requested_duty_cycle=50.000
CSET clkout1_requested_out_freq=175
CSET clkout1_requested_out_freq=166.667
CSET clkout1_requested_phase=0.000
CSET clkout2_drives=BUFG
CSET clkout2_requested_duty_cycle=50.000
@@ -148,16 +148,16 @@ CSET jitter_options=UI
CSET jitter_sel=No_Jitter
CSET locked_port=LOCKED
CSET mmcm_bandwidth=OPTIMIZED
CSET mmcm_clkfbout_mult_f=7
CSET mmcm_clkfbout_mult_f=8
CSET mmcm_clkfbout_phase=0.000
CSET mmcm_clkfbout_use_fine_ps=false
CSET mmcm_clkin1_period=8.000
CSET mmcm_clkin2_period=10.0
CSET mmcm_clkout0_divide_f=5
CSET mmcm_clkout0_divide_f=6
CSET mmcm_clkout0_duty_cycle=0.500
CSET mmcm_clkout0_phase=0.000
CSET mmcm_clkout0_use_fine_ps=false
CSET mmcm_clkout1_divide=7
CSET mmcm_clkout1_divide=8
CSET mmcm_clkout1_duty_cycle=0.500
CSET mmcm_clkout1_phase=0.000
CSET mmcm_clkout1_use_fine_ps=false
@@ -266,4 +266,4 @@ CSET use_status=false
MISC pkg_timestamp=2012-05-10T12:44:55Z
# END Extra information
GENERATE
# CRC: 1d4d384f
# CRC: 215f8243
top/x300/coregen/bus_clk_gen.xise
+22 -27
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@@ -9,28 +9,21 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.4" xil_pn:schema_version="2"/>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="bus_clk_gen/example_design/bus_clk_gen_exdes.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="bus_clk_gen/example_design/bus_clk_gen_exdes.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<file xil_pn:name="bus_clk_gen.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="bus_clk_gen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
</file>
</files>
@@ -46,7 +39,7 @@
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -149,9 +142,9 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|bus_clk_gen_exdes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="bus_clk_gen/example_design/bus_clk_gen_exdes.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/bus_clk_gen_exdes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|bus_clk_gen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="bus_clk_gen.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/bus_clk_gen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -205,7 +198,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="bus_clk_gen_exdes" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="bus_clk_gen" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -218,10 +211,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="bus_clk_gen_exdes_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="bus_clk_gen_exdes_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="bus_clk_gen_exdes_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="bus_clk_gen_exdes_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="bus_clk_gen_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="bus_clk_gen_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="bus_clk_gen_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="bus_clk_gen_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -345,13 +338,15 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-09-19T14:50:10" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="484FFD4A79488674A3CE815213589584" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-04-28T10:58:39" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="864AFA86C959B32B2CD711C532A10895" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<bindings>
<binding xil_pn:location="/bus_clk_gen" xil_pn:name="bus_clk_gen.ucf"/>
</bindings>
<libraries/>
top/x300/coregen/bus_clk_gen/clk_wiz_v3_6_readme.txt
+5 -2
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@@ -1,6 +1,6 @@
CHANGE LOG for LogiCORE Clocking Wizard V3.6
Release Date: July 25, 2012
Release Date: June 19, 2013
--------------------------------------------------------------------------------
Table of Contents
@@ -74,6 +74,8 @@ solution. For the latest core updates, see the product page at:
4.1 ISE
Resolved issue with example design becoming core top in planAhead
Resolved issue with Virtex6 MMCM instantiation for VHDL project
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
@@ -113,6 +115,7 @@ designs that do not follow specified guidelines.
Date By Version Description
================================================================================
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
@@ -133,7 +136,7 @@ Date By Version Description
8. LEGAL DISCLAIMER
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_readme.txt
+5 -2
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@@ -1,6 +1,6 @@
CHANGE LOG for LogiCORE Clocking Wizard V3.6
Release Date: July 25, 2012
Release Date: June 19, 2013
--------------------------------------------------------------------------------
Table of Contents
@@ -74,6 +74,8 @@ solution. For the latest core updates, see the product page at:
4.1 ISE
Resolved issue with example design becoming core top in planAhead
Resolved issue with Virtex6 MMCM instantiation for VHDL project
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
@@ -113,6 +115,7 @@ designs that do not follow specified guidelines.
Date By Version Description
================================================================================
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
@@ -133,7 +136,7 @@ Date By Version Description
8. LEGAL DISCLAIMER
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
top/x300/coregen/bus_clk_gen/doc/clk_wiz_v3_6_vinfo.html
+6 -3
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@@ -7,7 +7,7 @@
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
CHANGE LOG for LogiCORE Clocking Wizard V3.6
Release Date: July 25, 2012
Release Date: June 19, 2013
--------------------------------------------------------------------------------
Table of Contents
@@ -81,8 +81,10 @@ solution. For the latest core updates, see the product page at:
4.1 ISE
Resolved issue with example design becoming core top in planAhead
Resolved issue with Virtex6 MMCM instantiation for VHDL project
Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A>
................................................................................
@@ -120,6 +122,7 @@ designs that do not follow specified guidelines.
Date By Version Description
================================================================================
06/19/2013 Xilinx, Inc. 3.6(Rev3) ISE 14.6 support
10/16/2012 Xilinx, Inc. 3.6(Rev2) ISE 14.3 support
07/25/2012 Xilinx, Inc. 3.6 ISE 14.2 support
04/24/2012 Xilinx, Inc. 3.5 ISE 14.1 support
@@ -140,7 +143,7 @@ Date By Version Description
8. LEGAL DISCLAIMER
(c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
top/x300/coregen/bus_clk_gen/example_design/bus_clk_gen_exdes.ucf
-10
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@@ -53,16 +53,6 @@
NET "CLK_IN1" TNM_NET = "CLK_IN1";
TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 8.000 ns HIGH 50% INPUT_JITTER 80.0ps;
# Derived clock periods. These are commented out because they are
# automatically propogated by the tools
# However, if you'd like to use them for module level testing, you
# can copy them into your module level timing checks
#-----------------------------------------------------------------
# NET "clk_int[1]" TNM_NET = "CLK_OUT1";
# TIMESPEC "TS_CLK_OUT1" = PERIOD "CLK_OUT1" 175.000 MHz;
# NET "clk_int[2]" TNM_NET = "CLK_OUT2";
# TIMESPEC "TS_CLK_OUT2" = PERIOD "CLK_OUT2" 125.000 MHz;
# FALSE PATH constraints
PIN "COUNTER_RESET" TIG;
top/x300/coregen/bus_clk_gen/simulation/bus_clk_gen_tb.v
+2 -2
View File
@@ -88,11 +88,11 @@ wire [2:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (8.000*1*5*1000/7);
localparam ref_period1_clkin1 = (8.000*1*6*1000/8);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (8.000*1*7*1000/7);
localparam ref_period2_clkin1 = (8.000*1*8*1000/8);
time prev_rise2;
top/x300/coregen/bus_clk_gen/simulation/timing/bus_clk_gen_tb.v
+2 -2
View File
@@ -88,11 +88,11 @@ wire [2:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (8.000*1*5*1000/7);
localparam ref_period1_clkin1 = (8.000*1*6*1000/8);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (8.000*1*7*1000/7);
localparam ref_period2_clkin1 = (8.000*1*8*1000/8);
time prev_rise2;
reg [13:0] timeout_counter = 14'b00000000000000;
top/x300/coregen/bus_clk_gen_xmdf.tcl
+4 -8
View File
@@ -40,10 +40,6 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/example_design/bus_clk_gen_exdes.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/doc/clk_wiz_ds709.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
@@ -52,10 +48,6 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/example_design/bus_clk_gen_exdes.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen/implement/implement.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
@@ -120,6 +112,10 @@ utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen.
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path bus_clk_gen.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount