fpga: updating b200 and x300 FPGA source code for latest images

Original-commit: 00711ba213dde8aa0a099d2b18d3da0a33e6af79

lib/vita/new_tx_control.v

@@ -4,26 +4,26 @@ module new_tx_control
   #(parameter BASE=0)
    (input clk, input reset, input clear,
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
-    
+
     input [63:0] vita_time,
     output reg ack_or_error,
     output packet_consumed,
     output [11:0] seqnum,
     output reg [63:0] error_code,
     output [31:0] sid,
-    
+
     // From tx_deframer
     input [175:0] sample_tdata,
     input sample_tvalid,
     output sample_tready,
-    
+
     // To DSP Core
-    output [31:0] sample,    
+    output [31:0] sample,
     output run,    input strobe,
-    
+
     output [31:0] debug
     );
-   
+
    wire [31:0] 	  sample1 = sample_tdata[31:0];
    wire [31:0] 	  sample0 = sample_tdata[63:32];
    wire [63:0] 	  send_time = sample_tdata[127:64];
@@ -33,39 +33,39 @@ module new_tx_control
    wire 	  eob = sample_tdata[173];
    wire 	  send_at = sample_tdata[174];
    wire 	  odd = sample_tdata[175];
-   
+
    wire 	  now, early, late, too_early;
    wire 	  policy_next_burst, policy_next_packet, policy_wait;
    wire 	  clear_seqnum;
-   
+
    setting_reg #(.my_addr(BASE), .width(3)) sr_error_policy
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({policy_next_burst,policy_next_packet,policy_wait}),.changed(clear_seqnum));
 
-   time_compare 
+   time_compare
      time_compare (.clk(clk), .reset(reset), .time_now(vita_time), .trigger_time(send_time),
 		   .now(now), .early(early), .late(late), .too_early(too_early));
 
    assign run = (state == ST_SAMP0) | (state == ST_SAMP1);
-   
+
    assign sample = (state == ST_SAMP0) ? sample0 : sample1;
-   
+
    reg [2:0] 	 state;
-   
+
    localparam ST_IDLE  = 0;
    localparam ST_SAMP0 = 1;
    localparam ST_SAMP1 = 2;
    localparam ST_ERROR = 3;
    localparam ST_WAIT  = 4;
 
+   reg [11:0]  expected_seqnum;
+
    wire [63:0] CODE_EOB_ACK            = {32'd1,20'd0,seqnum};
    wire [63:0] CODE_UNDERRUN           = {32'd2,20'd0,seqnum};
-   wire [63:0] CODE_SEQ_ERROR          = {32'd4,20'd0,seqnum};
+   wire [63:0] CODE_SEQ_ERROR          = {32'd4,4'd0,expected_seqnum,4'd0,seqnum};
    wire [63:0] CODE_TIME_ERROR         = {32'd8,20'd0,seqnum};
    wire [63:0] CODE_UNDERRUN_MIDPKT    = {32'd16,20'd0,seqnum};
-   wire [63:0] CODE_SEQ_ERROR_MIDBURST = {32'd32,20'd0,seqnum};
-
-   reg [11:0]  expected_seqnum;
+   wire [63:0] CODE_SEQ_ERROR_MIDBURST = {32'd32,4'd0,expected_seqnum,4'd0,seqnum};
 
    always @(posedge clk)
      if(reset | clear | clear_seqnum)
@@ -73,14 +73,14 @@ module new_tx_control
      else
        if(sample_tvalid & sample_tready & eop)
 	 expected_seqnum <= seqnum + 12'd1;
-   
+
    always @(posedge clk)
      if(reset | clear)
        begin
 	  state <= ST_IDLE;
 	  ack_or_error <= 1'b0;
 	  error_code <= 64'd0;
-       end     
+       end
      else
        case(state)
 	 ST_IDLE :
@@ -151,7 +151,7 @@ module new_tx_control
    assign sample_tready = (state == ST_ERROR) | (strobe & ( (state == ST_SAMP1) | ((state == ST_SAMP0) & eop & odd) ) );
 
    assign packet_consumed = eop & sample_tvalid & sample_tready;
-   
+
    assign debug = {
 		   error_code[37:32], // [30:25]
 		   error_code[11:0], // [24:13]
@@ -168,5 +168,5 @@ module new_tx_control
 		   state[2:0] //  [2:0]
 		   };
 
-   
+
 endmodule // new_tx_control