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fpga: lib: simplify timing in pulse stretch

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Original-commit: 2a3520b068456f1fdd291d4f8b0165e435a21757
This commit is contained in:
Max Köhler
2025-01-23 19:18:48 -06:00
committed by Wade Fife
parent edfe117b9c
commit 52cc1735fd
1 changed files with 5 additions and 6 deletions
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lib/control/pulse_stretch.v
+5 -6
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@@ -7,10 +7,10 @@
//
// Description:
//
// Pulse stretcher. Takes any input pulse that is SCALE+2 clock cycles or
// less and outputs a pulse that is SCALE+1 clock cycles. However, if an
// input pulse is longer than SCALE+2 clock cycles then the output pulse
// repeats. If more than one pulse is input within SCALE+2 clock cycles then
// Pulse stretcher. Takes any input pulse that is SCALE+2 clock cycles or
// less and outputs a pulse that is SCALE+1 clock cycles. However, if an
// input pulse is longer than SCALE+2 clock cycles then the output pulse
// repeats. If more than one pulse is input within SCALE+2 clock cycles then
// additional pulses will be ignored.
//
// Examples (SCALE = 2):
@@ -66,10 +66,9 @@ module pulse_stretch #(
end
1'b1: begin
count <= count + 1'b1;
if (count == SCALE)
state <= 1'b0;
else
count <= count + 1'b1;
end
endcase
end