From 52cc1735fd6bc5073b8b7379e34fc78a1c003442 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Max=20K=C3=B6hler?= Date: Thu, 23 Jan 2025 00:09:44 +0100 Subject: [PATCH] fpga: lib: simplify timing in pulse stretch Original-commit: 2a3520b068456f1fdd291d4f8b0165e435a21757 --- lib/control/pulse_stretch.v | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/lib/control/pulse_stretch.v b/lib/control/pulse_stretch.v index 2235286..bd52c7b 100644 --- a/lib/control/pulse_stretch.v +++ b/lib/control/pulse_stretch.v @@ -7,10 +7,10 @@ // // Description: // -// Pulse stretcher. Takes any input pulse that is SCALE+2 clock cycles or -// less and outputs a pulse that is SCALE+1 clock cycles. However, if an -// input pulse is longer than SCALE+2 clock cycles then the output pulse -// repeats. If more than one pulse is input within SCALE+2 clock cycles then +// Pulse stretcher. Takes any input pulse that is SCALE+2 clock cycles or +// less and outputs a pulse that is SCALE+1 clock cycles. However, if an +// input pulse is longer than SCALE+2 clock cycles then the output pulse +// repeats. If more than one pulse is input within SCALE+2 clock cycles then // additional pulses will be ignored. // // Examples (SCALE = 2): @@ -66,10 +66,9 @@ module pulse_stretch #( end 1'b1: begin + count <= count + 1'b1; if (count == SCALE) state <= 1'b0; - else - count <= count + 1'b1; end endcase end