fpga: x4xx: replace ADC/DAC info by RFDC memory
Original-commit: 6c6d52fd655b144aa5ee581edae7911dc734854e
This commit is contained in:
Max Köhler
committed by
Jörg Hofrichter
Jörg Hofrichter
parent
37b8b0d017
commit
50f20ef4ab
@@ -384,126 +384,6 @@
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// </bitfield>
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// </regtype>
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//
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// <regtype name="ADC_TILEMAP_REGTYPE" size="32" writable="false">
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// <info>
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// This register describes how the ADCs map to the respective tiles. It
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// lets us designate an ADC as channel 0, channel 1, etc. depending on
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// how those channels are externally connected to the RFSoC.{BR/}
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//
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// For every channel, this register stores the tile number and the block
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// number of the converter. This can be used to then address the correct
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// converter in the various Xilinx interfaces/APIs.
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// </info>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN0_TILE" range="1..0" initialvalue="0">
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// <info>Tile number of the ADC for channel 0, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN0_BLOCK" range="3..2" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 0, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN1_TILE" range="5..4" initialvalue="0">
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// <info>Tile number of the ADC for channel 1, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN1_BLOCK" range="7..6" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 1, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN2_TILE" range="9..8" initialvalue="0">
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// <info>Tile number of the ADC for channel 2, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN2_BLOCK" range="11..10" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 2, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN3_TILE" range="13..12" initialvalue="0">
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// <info>Tile number of the ADC for channel 3, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB0_CHAN3_BLOCK" range="15..14" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 3, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN0_TILE" range="17..16" initialvalue="0">
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// <info>Tile number of the ADC for channel 0, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN0_BLOCK" range="19..18" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 0, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN1_TILE" range="21..20" initialvalue="0">
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// <info>Tile number of the ADC for channel 1, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN1_BLOCK" range="23..22" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 1, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN2_TILE" range="25..24" initialvalue="0">
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// <info>Tile number of the ADC for channel 2, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN2_BLOCK" range="27..26" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 2, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN3_TILE" range="29..28" initialvalue="0">
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// <info>Tile number of the ADC for channel 3, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="ADC_TILEMAP_DB1_CHAN3_BLOCK" range="31..30" initialvalue="0">
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// <info>Block number (within the tile) of the ADC for channel 3, daughterboard 1.</info>
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// </bitfield>
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// </regtype>
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// <regtype name="DAC_TILEMAP_REGTYPE" size="32" writable="false">
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// <info>
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// This register describes how the DACs map to the respective tiles. It
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// lets us designate an DAC as channel 0, channel 1, etc. depending on
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// how those channels are externally connected to the RFSoC.{BR/}
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//
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// For every channel, this register stores the tile number and the block
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// number of the converter. This can be used to then address the correct
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// converter in the various Xilinx interfaces/APIs.
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// </info>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN0_TILE" range="1..0" initialvalue="0">
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// <info>Tile number of the DAC for channel 0, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN0_BLOCK" range="3..2" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 0, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN1_TILE" range="5..4" initialvalue="0">
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// <info>Tile number of the DAC for channel 1, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN1_BLOCK" range="7..6" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 1, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN2_TILE" range="9..8" initialvalue="0">
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// <info>Tile number of the DAC for channel 2, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN2_BLOCK" range="11..10" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 2, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN3_TILE" range="13..12" initialvalue="0">
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// <info>Tile number of the DAC for channel 3, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB0_CHAN3_BLOCK" range="15..14" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 3, daughterboard 0.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN0_TILE" range="17..16" initialvalue="0">
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// <info>Tile number of the DAC for channel 0, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN0_BLOCK" range="19..18" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 0, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN1_TILE" range="21..20" initialvalue="0">
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// <info>Tile number of the DAC for channel 1, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN1_BLOCK" range="23..22" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 1, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN2_TILE" range="25..24" initialvalue="0">
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// <info>Tile number of the DAC for channel 2, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN2_BLOCK" range="27..26" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 2, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN3_TILE" range="29..28" initialvalue="0">
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// <info>Tile number of the DAC for channel 3, daughterboard 1.</info>
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// </bitfield>
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// <bitfield name="DAC_TILEMAP_DB1_CHAN3_BLOCK" range="31..30" initialvalue="0">
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// <info>Block number (within the tile) of the DAC for channel 3, daughterboard 1.</info>
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// </bitfield>
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// </regtype>
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//
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//
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// </group>
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//</regmap>
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//XmlParse xml_off
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@@ -11,20 +11,30 @@ x410_ps_rfdc_bd.tcl \
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)
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IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \
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rfdc_info_pkg.sv \
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) \
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$(addprefix $(BASE_DIR)/x400/rf/x410/, \
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x410_rf_reset_controller.vhd \
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x410_clock_gates.vhd \
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x410_rfdc_memory_content_pkg.sv \
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) \
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$(addprefix $(BASE_DIR)/x400/rf/common/, \
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capture_sysref.v \
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rf_nco_reset.vhd \
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rf_reset.vhd \
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sync_wrapper.v \
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axis_mux.vhd \
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gpio_to_axis_mux.vhd \
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) \
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$(addprefix $(BASE_DIR)/x400/rf/x410/, \
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x410_rf_reset_controller.vhd \
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x410_clock_gates.vhd \
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rfdc_info_memory.sv \
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axi_rfdc_info_memory.v \
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) \
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$(addprefix $(BASE_DIR)/../lib/control/, \
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synchronizer.v \
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synchronizer_impl.v \
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reset_sync.v \
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) \
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$(addprefix $(BASE_DIR)/../lib/rfnoc/core/, \
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ctrlport.vh \
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) \
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$(addprefix $(BASE_DIR)/x400/regmap/x410/, PkgRFDC_REGS_REGMAP.vhd )
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@@ -1,14 +1,22 @@
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set script_loc [file normalize [info script]]
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set script_dir [file dirname $script_loc]
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read_verilog -library work $script_dir/../../../../../lib/axi/axi_defs.v
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read_verilog -library work $script_dir/../../../../../lib/control/axil_ctrlport_master.v
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read_verilog -library work $script_dir/../../../../../lib/control/reset_sync.v
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read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
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read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
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read_verilog -library work $script_dir/../../../../../lib/rfnoc/core/ctrlport.vh
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read_vhdl -library work $script_dir/../../../regmap/x410/PkgRFDC_REGS_REGMAP.vhd
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read_verilog -library work $script_dir/../../../rf/common/axi_rfdc_info_memory.v
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read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
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read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
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read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
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read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
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read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
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read_verilog -sv -library work $script_dir/../../../rf/common/rfdc_info_memory.sv
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read_verilog -sv -library work $script_dir/../../../rf/common/rfdc_info_pkg.sv
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read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
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read_vhdl -library work $script_dir/../../../rf/x410/x410_clock_gates.vhd
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read_vhdl -library work $script_dir/../../../rf/x410/x410_rf_reset_controller.vhd
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read_verilog -sv -library work $script_dir/../../../rf/x410/x410_rfdc_memory_content_pkg.sv
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@@ -215,8 +215,7 @@
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// </register>
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//
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// <register name="FABRIC_DSP_REG" offset="0x13008" typename="FABRIC_DSP_REGTYPE"/>
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// <register name="ADC_TILEMAP_REG" offset="0x17000" typename="ADC_TILEMAP_REGTYPE"/>
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// <register name="DAC_TILEMAP_REG" offset="0x17008" typename="DAC_TILEMAP_REGTYPE"/>
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// <register name="RFDC_INFO_MEM" offset="0x17000" count="16" step="4" typename="RFDC_INFO_MEMTYPE"/>
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// <register name="RFDC_INFO_REG" offset="0x18000" typename="RFDC_INFO_REGTYPE"/>
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//
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// </group>
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@@ -40,7 +40,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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# The design that will be created by this Tcl script contains the following
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# module references:
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# capture_sysref, x410_clock_gates, rf_nco_reset, x410_rf_reset_controller, x410_rf_reset_controller, gpio_to_axis_mux
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# axi_rfdc_info_memory, capture_sysref, x410_clock_gates, rf_nco_reset, x410_rf_reset_controller, x410_rf_reset_controller, gpio_to_axis_mux
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# Please add the sources of those modules before sourcing this Tcl script.
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@@ -179,6 +179,7 @@ xilinx.com:ip:smartconnect:1.0\
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set bCheckModules 1
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if { $bCheckModules == 1 } {
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set list_check_mods "\
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axi_rfdc_info_memory\
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capture_sysref\
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x410_clock_gates\
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rf_nco_reset\
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@@ -749,6 +750,25 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
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CONFIG.STRATEGY {1} \
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] $axi_interconnect_rf
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# Create instance: axi_rfdc_info_memory_0, and set properties
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set block_name axi_rfdc_info_memory
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set block_cell_name axi_rfdc_info_memory_0
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if { [catch {set axi_rfdc_info_memory_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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} elseif { $axi_rfdc_info_memory_0 eq "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
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return 1
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}
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set_property -dict [ list \
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CONFIG.AXI_ADDR_WIDTH {7} \
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CONFIG.CTRLPORT_AWIDTH {7} \
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] $axi_rfdc_info_memory_0
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {axi_s} \
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] [get_bd_pins /rfdc/axi_rfdc_info_memory_0/s_axi_aclk]
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# Create instance: calibration_muxes
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create_hier_cell_calibration_muxes $hier_obj calibration_muxes
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@@ -917,14 +937,6 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
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CONFIG.C_ALL_INPUTS {1} \
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] $reg_rfdc_info
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# Create instance: reg_rfdc_tile_mapping, and set properties
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set reg_rfdc_tile_mapping [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rfdc_tile_mapping ]
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set_property -dict [ list \
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CONFIG.C_ALL_INPUTS {1} \
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CONFIG.C_ALL_INPUTS_2 {1} \
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CONFIG.C_IS_DUAL {1} \
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] $reg_rfdc_tile_mapping
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# Create instance: rf_data_converter, and set properties
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set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ]
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set_property -dict [ list \
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@@ -1214,20 +1226,6 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
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return 1
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}
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# Create instance: rfdc_adc_map, and set properties
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set rfdc_adc_map [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 rfdc_adc_map ]
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set_property -dict [ list \
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CONFIG.CONST_VAL {0b0000001001100000000000000100} \
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CONFIG.CONST_WIDTH {32} \
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] $rfdc_adc_map
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# Create instance: rfdc_dac_map, and set properties
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set rfdc_dac_map [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 rfdc_dac_map ]
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set_property -dict [ list \
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CONFIG.CONST_VAL {0b0000010100010000000001000000} \
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CONFIG.CONST_WIDTH {32} \
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] $rfdc_dac_map
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# Create instance: slice_iqswap_11_8_radio0, and set properties
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set slice_iqswap_11_8_radio0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_iqswap_11_8_radio0 ]
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set_property -dict [ list \
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@@ -1273,7 +1271,7 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
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connect_bd_intf_net -intf_net axi_interconnect_rf_M05_AXI [get_bd_intf_pins axi_interconnect_rf/M05_AXI] [get_bd_intf_pins reg_rf_axi_status/S_AXI]
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connect_bd_intf_net -intf_net axi_interconnect_rf_M07_AXI [get_bd_intf_pins axi_interconnect_rf/M07_AXI] [get_bd_intf_pins reg_clock_gate_control/S_AXI]
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connect_bd_intf_net -intf_net axi_interconnect_rf_M08_AXI [get_bd_intf_pins ThresholdRegister/S_AXI] [get_bd_intf_pins axi_interconnect_rf/M08_AXI]
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connect_bd_intf_net -intf_net axi_interconnect_rf_M09_AXI [get_bd_intf_pins axi_interconnect_rf/M09_AXI] [get_bd_intf_pins reg_rfdc_tile_mapping/S_AXI]
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connect_bd_intf_net -intf_net axi_interconnect_rf_M09_AXI [get_bd_intf_pins axi_interconnect_rf/M09_AXI] [get_bd_intf_pins axi_rfdc_info_memory_0/axi_s]
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connect_bd_intf_net -intf_net axi_interconnect_rf_M10_AXI [get_bd_intf_pins axi_interconnect_rf/M10_AXI] [get_bd_intf_pins reg_rfdc_info/S_AXI]
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connect_bd_intf_net -intf_net axi_interconnect_rf_M11_AXI [get_bd_intf_pins axi_interconnect_rf/M11_AXI] [get_bd_intf_pins reg_invert_iq_radio1/S_AXI]
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connect_bd_intf_net -intf_net axi_interconnect_rf_M12_AXI [get_bd_intf_pins axi_interconnect_rf/M12_AXI] [get_bd_intf_pins reg_rf_reset_control_radio1/S_AXI]
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@@ -1372,10 +1370,9 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
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connect_bd_net -net rf_reset_controller_1_rAdcRfdcAxiReset_n [get_bd_pins rf_data_converter/m2_axis_aresetn] [get_bd_pins rf_reset_controller_1/rAdcRfdcAxiReset_n]
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connect_bd_net -net rf_reset_controller_1_rDacRfdcAxiReset_n [get_bd_pins rf_data_converter/s1_axis_aresetn] [get_bd_pins rf_reset_controller_1/rDacRfdcAxiReset_n]
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connect_bd_net -net rf_rfdc_info_sclk_1 [get_bd_pins rf_rfdc_info_sclk] [get_bd_pins reg_rfdc_info/gpio_io_i]
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connect_bd_net -net rfdc_adc_map_dout [get_bd_pins reg_rfdc_tile_mapping/gpio_io_i] [get_bd_pins rfdc_adc_map/dout]
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connect_bd_net -net rfdc_regs_gpio_io_o [get_bd_pins reg_invert_iq_radio0/gpio_io_o] [get_bd_pins slice_iqswap_11_8_radio0/Din] [get_bd_pins slice_iqswap_3_0_radio0/Din]
|
||||
connect_bd_net -net s_axi_aresetn_0_1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins ThresholdRegister/s_axi_config_aresetn] [get_bd_pins axi_interconnect_rf/ARESETN] [get_bd_pins axi_interconnect_rf/M00_ARESETN] [get_bd_pins axi_interconnect_rf/M03_ARESETN] [get_bd_pins axi_interconnect_rf/M04_ARESETN] [get_bd_pins axi_interconnect_rf/M05_ARESETN] [get_bd_pins axi_interconnect_rf/M06_ARESETN] [get_bd_pins axi_interconnect_rf/M07_ARESETN] [get_bd_pins axi_interconnect_rf/M08_ARESETN] [get_bd_pins axi_interconnect_rf/M09_ARESETN] [get_bd_pins axi_interconnect_rf/M10_ARESETN] [get_bd_pins axi_interconnect_rf/M12_ARESETN] [get_bd_pins axi_interconnect_rf/S00_ARESETN] [get_bd_pins calibration_muxes/s_axi_config_aresetn] [get_bd_pins reg_clock_gate_control/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/s_axi_aresetn] [get_bd_pins reg_rf_axi_status/s_axi_aresetn] [get_bd_pins reg_rf_reset_control_radio0/s_axi_aresetn] [get_bd_pins reg_rf_reset_control_radio1/s_axi_aresetn] [get_bd_pins reg_rfdc_info/s_axi_aresetn] [get_bd_pins reg_rfdc_tile_mapping/s_axi_aresetn] [get_bd_pins rf_data_converter/s_axi_aresetn]
|
||||
connect_bd_net -net s_axi_config_clk_1 [get_bd_pins s_axi_config_clk] [get_bd_pins ThresholdRegister/s_axi_config_clk] [get_bd_pins axi_interconnect_rf/ACLK] [get_bd_pins axi_interconnect_rf/M00_ACLK] [get_bd_pins axi_interconnect_rf/M01_ACLK] [get_bd_pins axi_interconnect_rf/M03_ACLK] [get_bd_pins axi_interconnect_rf/M04_ACLK] [get_bd_pins axi_interconnect_rf/M05_ACLK] [get_bd_pins axi_interconnect_rf/M06_ACLK] [get_bd_pins axi_interconnect_rf/M07_ACLK] [get_bd_pins axi_interconnect_rf/M08_ACLK] [get_bd_pins axi_interconnect_rf/M09_ACLK] [get_bd_pins axi_interconnect_rf/M10_ACLK] [get_bd_pins axi_interconnect_rf/M12_ACLK] [get_bd_pins axi_interconnect_rf/S00_ACLK] [get_bd_pins calibration_muxes/s_axi_config_clk] [get_bd_pins clock_gates_0/ReliableClk] [get_bd_pins data_clock_mmcm/s_axi_aclk] [get_bd_pins reg_clock_gate_control/s_axi_aclk] [get_bd_pins reg_reset_mmcm/s_axi_aclk] [get_bd_pins reg_rf_axi_status/s_axi_aclk] [get_bd_pins reg_rf_reset_control_radio0/s_axi_aclk] [get_bd_pins reg_rf_reset_control_radio1/s_axi_aclk] [get_bd_pins reg_rfdc_info/s_axi_aclk] [get_bd_pins reg_rfdc_tile_mapping/s_axi_aclk] [get_bd_pins rf_data_converter/s_axi_aclk] [get_bd_pins rf_nco_reset_0/ConfigClk] [get_bd_pins rf_reset_controller_0/ConfigClk] [get_bd_pins rf_reset_controller_1/ConfigClk]
|
||||
connect_bd_net -net s_axi_aresetn_0_1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins ThresholdRegister/s_axi_config_aresetn] [get_bd_pins axi_interconnect_rf/ARESETN] [get_bd_pins axi_interconnect_rf/M00_ARESETN] [get_bd_pins axi_interconnect_rf/M03_ARESETN] [get_bd_pins axi_interconnect_rf/M04_ARESETN] [get_bd_pins axi_interconnect_rf/M05_ARESETN] [get_bd_pins axi_interconnect_rf/M06_ARESETN] [get_bd_pins axi_interconnect_rf/M07_ARESETN] [get_bd_pins axi_interconnect_rf/M08_ARESETN] [get_bd_pins axi_interconnect_rf/M09_ARESETN] [get_bd_pins axi_interconnect_rf/M10_ARESETN] [get_bd_pins axi_interconnect_rf/M12_ARESETN] [get_bd_pins axi_interconnect_rf/S00_ARESETN] [get_bd_pins axi_rfdc_info_memory_0/s_axi_aresetn] [get_bd_pins calibration_muxes/s_axi_config_aresetn] [get_bd_pins reg_clock_gate_control/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/s_axi_aresetn] [get_bd_pins reg_rf_axi_status/s_axi_aresetn] [get_bd_pins reg_rf_reset_control_radio0/s_axi_aresetn] [get_bd_pins reg_rf_reset_control_radio1/s_axi_aresetn] [get_bd_pins reg_rfdc_info/s_axi_aresetn] [get_bd_pins rf_data_converter/s_axi_aresetn]
|
||||
connect_bd_net -net s_axi_config_clk_1 [get_bd_pins s_axi_config_clk] [get_bd_pins ThresholdRegister/s_axi_config_clk] [get_bd_pins axi_interconnect_rf/ACLK] [get_bd_pins axi_interconnect_rf/M00_ACLK] [get_bd_pins axi_interconnect_rf/M01_ACLK] [get_bd_pins axi_interconnect_rf/M03_ACLK] [get_bd_pins axi_interconnect_rf/M04_ACLK] [get_bd_pins axi_interconnect_rf/M05_ACLK] [get_bd_pins axi_interconnect_rf/M06_ACLK] [get_bd_pins axi_interconnect_rf/M07_ACLK] [get_bd_pins axi_interconnect_rf/M08_ACLK] [get_bd_pins axi_interconnect_rf/M09_ACLK] [get_bd_pins axi_interconnect_rf/M10_ACLK] [get_bd_pins axi_interconnect_rf/M12_ACLK] [get_bd_pins axi_interconnect_rf/S00_ACLK] [get_bd_pins axi_rfdc_info_memory_0/s_axi_aclk] [get_bd_pins calibration_muxes/s_axi_config_clk] [get_bd_pins clock_gates_0/ReliableClk] [get_bd_pins data_clock_mmcm/s_axi_aclk] [get_bd_pins reg_clock_gate_control/s_axi_aclk] [get_bd_pins reg_reset_mmcm/s_axi_aclk] [get_bd_pins reg_rf_axi_status/s_axi_aclk] [get_bd_pins reg_rf_reset_control_radio0/s_axi_aclk] [get_bd_pins reg_rf_reset_control_radio1/s_axi_aclk] [get_bd_pins reg_rfdc_info/s_axi_aclk] [get_bd_pins rf_data_converter/s_axi_aclk] [get_bd_pins rf_nco_reset_0/ConfigClk] [get_bd_pins rf_reset_controller_0/ConfigClk] [get_bd_pins rf_reset_controller_1/ConfigClk]
|
||||
connect_bd_net -net slice_iqswap_11_8_radio0_Dout [get_bd_pins radio0_invert_dac_iq_r0clk] [get_bd_pins slice_iqswap_11_8_radio0/Dout]
|
||||
connect_bd_net -net slice_iqswap_11_8_radio1_Dout [get_bd_pins radio1_invert_dac_iq_r1clk] [get_bd_pins slice_iqswap_11_8_radio1/Dout]
|
||||
connect_bd_net -net slice_iqswap_3_0_radio0_Dout [get_bd_pins radio0_invert_adc_iq_r0clk] [get_bd_pins slice_iqswap_3_0_radio0/Dout]
|
||||
@@ -1383,7 +1380,6 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
connect_bd_net -net start_nco_reset_rclk_1 [get_bd_pins start_nco_reset_dclk] [get_bd_pins rf_nco_reset_0/dStartNcoReset]
|
||||
connect_bd_net -net sysref_in_0_2 [get_bd_pins sysref_pl_in] [get_bd_pins capture_sysref/sysref_in]
|
||||
connect_bd_net -net xlconstant_0_dout [get_bd_pins rf_nco_reset_0/cAdc1xNcoUpdateBusy] [get_bd_pins rf_nco_reset_0/cAdc3xNcoUpdateBusy] [get_bd_pins xlconstant_0/dout]
|
||||
connect_bd_net -net xlconstant_1_dout [get_bd_pins reg_rfdc_tile_mapping/gpio2_io_i] [get_bd_pins rfdc_dac_map/dout]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
@@ -3694,6 +3690,7 @@ proc create_root_design { parentCell } {
|
||||
assign_bd_address -offset 0x0010000A4000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/S_AXI_LITE/Reg] -force
|
||||
assign_bd_address -offset 0x001000155000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/ThresholdRegister/axi_gpio_0/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000154000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/calibration_muxes/axi_gpio_data/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000157000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/axi_rfdc_info_memory_0/axi_s/reg0] -force
|
||||
assign_bd_address -offset 0x001000000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/cpld_jtag_engine/S_AXI/reg0] -force
|
||||
assign_bd_address -offset 0x001000140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/data_clock_mmcm/s_axi_lite/Reg] -force
|
||||
assign_bd_address -offset 0x001200000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_app/Reg] -force
|
||||
@@ -3709,7 +3706,6 @@ proc create_root_design { parentCell } {
|
||||
assign_bd_address -offset 0x001000152000 -range 0x00000800 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control_radio0/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000152800 -range 0x00000800 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control_radio1/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000158000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rfdc_info/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000157000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rfdc_tile_mapping/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000100000 -range 0x00040000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/rf_data_converter/s_axi/Reg] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force
|
||||
|
||||
@@ -11,25 +11,32 @@ x440_ps_rfdc_bd.tcl \
|
||||
)
|
||||
|
||||
IP_X4XX_PS_RFDC_HDL_SRCS = $(addprefix $(BASE_DIR)/x400/rf/common/, \
|
||||
rfdc_info_pkg.sv \
|
||||
) \
|
||||
$(addprefix $(BASE_DIR)/x400/rf/x440/, \
|
||||
x440_clock_gates.vhd \
|
||||
x440_rf_reset_controller.vhd \
|
||||
x440_rfdc_memory_content_pkg.sv \
|
||||
) \
|
||||
$(addprefix $(BASE_DIR)/x400/rf/common/, \
|
||||
capture_sysref.v \
|
||||
rf_nco_reset.vhd \
|
||||
rf_reset.vhd \
|
||||
sync_wrapper.v \
|
||||
axis_mux.vhd \
|
||||
gpio_to_axis_mux.vhd \
|
||||
) \
|
||||
$(addprefix $(BASE_DIR)/x400/rf/x440/, \
|
||||
x440_clock_gates.vhd \
|
||||
x440_rf_reset_controller.vhd \
|
||||
x440_rfdc_tx_control_remap.v \
|
||||
rfdc_info_memory.sv \
|
||||
axi_rfdc_info_memory.v \
|
||||
) \
|
||||
$(addprefix $(BASE_DIR)/../lib/control/, \
|
||||
synchronizer.v \
|
||||
synchronizer_impl.v \
|
||||
) \
|
||||
$(addprefix $(BASE_DIR)/../lib/rfnoc/core/, \
|
||||
ctrlport.vh \
|
||||
) \
|
||||
$(addprefix $(BASE_DIR)/x400/regmap/x440/, \
|
||||
PkgRFDC_REGS_REGMAP.vhd \
|
||||
rfdc_mapping_regmap_utils.vh \
|
||||
)
|
||||
|
||||
IP_X4XX_PS_RFDC_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/x440_ps_rfdc_bd/, \
|
||||
|
||||
@@ -1,16 +1,22 @@
|
||||
set script_loc [file normalize [info script]]
|
||||
set script_dir [file dirname $script_loc]
|
||||
|
||||
read_verilog -library work $script_dir/../../../../../lib/axi/axi_defs.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/axil_ctrlport_master.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/reset_sync.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/rfnoc/core/ctrlport.vh
|
||||
read_vhdl -library work $script_dir/../../../regmap/x440/PkgRFDC_REGS_REGMAP.vhd
|
||||
read_verilog -library work $script_dir/../../../regmap/x440/rfdc_mapping_regmap_utils.vh
|
||||
read_verilog -library work $script_dir/../../../rf/common/axi_rfdc_info_memory.v
|
||||
read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
|
||||
read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
|
||||
read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
|
||||
read_verilog -sv -library work $script_dir/../../../rf/common/rfdc_info_memory.sv
|
||||
read_verilog -sv -library work $script_dir/../../../rf/common/rfdc_info_pkg.sv
|
||||
read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
|
||||
read_vhdl -library work $script_dir/../../../rf/x440/x440_clock_gates.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/x440/x440_rf_reset_controller.vhd
|
||||
read_verilog -library work $script_dir/../../../rf/x440/x440_rfdc_tx_control_remap.v
|
||||
read_verilog -sv -library work $script_dir/../../../rf/x440/x440_rfdc_memory_content_pkg.sv
|
||||
|
||||
@@ -253,8 +253,7 @@
|
||||
// </register>
|
||||
//
|
||||
// <register name="FABRIC_DSP_REG" offset="0x13008" typename="FABRIC_DSP_REGTYPE"/>
|
||||
// <register name="ADC_TILEMAP_REG" offset="0x17000" typename="ADC_TILEMAP_REGTYPE"/>
|
||||
// <register name="DAC_TILEMAP_REG" offset="0x17008" typename="DAC_TILEMAP_REGTYPE"/>
|
||||
// <register name="RFDC_INFO_MEM" offset="0x17000" count="16" step="4" typename="RFDC_INFO_MEMTYPE"/>
|
||||
// <register name="RFDC_INFO_REG" offset="0x18000" typename="RFDC_INFO_REGTYPE"/>
|
||||
//
|
||||
// </group>
|
||||
|
||||
@@ -40,7 +40,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
|
||||
# The design that will be created by this Tcl script contains the following
|
||||
# module references:
|
||||
# capture_sysref, x440_clock_gates, rf_nco_reset, x440_rf_reset_controller, x440_rf_reset_controller, gpio_to_axis_mux, x440_rfdc_tx_control_remap
|
||||
# axi_rfdc_info_memory, capture_sysref, x440_clock_gates, rf_nco_reset, x440_rf_reset_controller, x440_rf_reset_controller, gpio_to_axis_mux
|
||||
|
||||
# Please add the sources of those modules before sourcing this Tcl script.
|
||||
|
||||
@@ -179,13 +179,13 @@ xilinx.com:ip:smartconnect:1.0\
|
||||
set bCheckModules 1
|
||||
if { $bCheckModules == 1 } {
|
||||
set list_check_mods "\
|
||||
axi_rfdc_info_memory\
|
||||
capture_sysref\
|
||||
x440_clock_gates\
|
||||
rf_nco_reset\
|
||||
x440_rf_reset_controller\
|
||||
x440_rf_reset_controller\
|
||||
gpio_to_axis_mux\
|
||||
x440_rfdc_tx_control_remap\
|
||||
"
|
||||
|
||||
set list_mods_missing ""
|
||||
@@ -313,17 +313,6 @@ proc create_hier_cell_calibration_muxes { parentCell nameHier } {
|
||||
CONFIG.kGpioWidth {32} \
|
||||
] $gpio_to_axis_mux_0
|
||||
|
||||
# Create instance: x440_rfdc_tx_control_0, and set properties
|
||||
set block_name x440_rfdc_tx_control_remap
|
||||
set block_cell_name x440_rfdc_tx_control_0
|
||||
if { [catch {set x440_rfdc_tx_control_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $x440_rfdc_tx_control_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins m_axis_0_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_0]
|
||||
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins m_axis_1_0] [get_bd_intf_pins gpio_to_axis_mux_0/m_axis_1]
|
||||
@@ -347,10 +336,9 @@ proc create_hier_cell_calibration_muxes { parentCell nameHier } {
|
||||
connect_bd_net -net Net [get_bd_pins s_axi_config_clk] [get_bd_pins axi_gpio_data/s_axi_aclk]
|
||||
connect_bd_net -net Net1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins axi_gpio_data/s_axi_aresetn]
|
||||
connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins axi_gpio_data/gpio_io_o] [get_bd_pins gpio_to_axis_mux_0/gpio]
|
||||
connect_bd_net -net axi_gpio_data_gpio2_io_o [get_bd_pins axi_gpio_data/gpio2_io_o] [get_bd_pins x440_rfdc_tx_control_0/input_controls]
|
||||
connect_bd_net -net axi_gpio_data_gpio2_io_o [get_bd_pins axi_gpio_data/gpio2_io_o] [get_bd_pins gpio_to_axis_mux_0/mux_select]
|
||||
connect_bd_net -net s_axi_aclk_0_1 [get_bd_pins s_axi_aclk_0] [get_bd_pins gpio_to_axis_mux_0/m_axis_0_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_1_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_2_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_3_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_0_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_1_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_2_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_3_aclk]
|
||||
connect_bd_net -net s_axi_aclk_1_1 [get_bd_pins s_axi_aclk_1] [get_bd_pins gpio_to_axis_mux_0/m_axis_4_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_5_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_6_aclk] [get_bd_pins gpio_to_axis_mux_0/m_axis_7_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_4_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_5_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_6_aclk] [get_bd_pins gpio_to_axis_mux_0/s_axis_7_aclk]
|
||||
connect_bd_net -net x440_rfdc_tx_control_0_output_controls [get_bd_pins gpio_to_axis_mux_0/mux_select] [get_bd_pins x440_rfdc_tx_control_0/output_controls]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
@@ -831,6 +819,25 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
CONFIG.STRATEGY {1} \
|
||||
] $axi_interconnect_rf
|
||||
|
||||
# Create instance: axi_rfdc_info_memory_0, and set properties
|
||||
set block_name axi_rfdc_info_memory
|
||||
set block_cell_name axi_rfdc_info_memory_0
|
||||
if { [catch {set axi_rfdc_info_memory_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
} elseif { $axi_rfdc_info_memory_0 eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
||||
return 1
|
||||
}
|
||||
set_property -dict [ list \
|
||||
CONFIG.AXI_ADDR_WIDTH {7} \
|
||||
CONFIG.CTRLPORT_AWIDTH {7} \
|
||||
] $axi_rfdc_info_memory_0
|
||||
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {axi_s} \
|
||||
] [get_bd_pins /rfdc/axi_rfdc_info_memory_0/s_axi_aclk]
|
||||
|
||||
# Create instance: calibration_muxes
|
||||
create_hier_cell_calibration_muxes $hier_obj calibration_muxes
|
||||
|
||||
@@ -1008,14 +1015,6 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
CONFIG.C_ALL_INPUTS {1} \
|
||||
] $reg_rfdc_info
|
||||
|
||||
# Create instance: reg_rfdc_tile_mapping, and set properties
|
||||
set reg_rfdc_tile_mapping [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 reg_rfdc_tile_mapping ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_ALL_INPUTS {1} \
|
||||
CONFIG.C_ALL_INPUTS_2 {1} \
|
||||
CONFIG.C_IS_DUAL {1} \
|
||||
] $reg_rfdc_tile_mapping
|
||||
|
||||
# Create instance: rf_data_converter, and set properties
|
||||
set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ]
|
||||
set_property -dict [ list \
|
||||
@@ -1370,20 +1369,6 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
return 1
|
||||
}
|
||||
|
||||
# Create instance: rfdc_adc_map, and set properties
|
||||
set rfdc_adc_map [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 rfdc_adc_map ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.CONST_VAL {0b00110010011001110001000001000101} \
|
||||
CONFIG.CONST_WIDTH {32} \
|
||||
] $rfdc_adc_map
|
||||
|
||||
# Create instance: rfdc_dac_map, and set properties
|
||||
set rfdc_dac_map [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 rfdc_dac_map ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.CONST_VAL {0b01011101100100010100110010000000} \
|
||||
CONFIG.CONST_WIDTH {32} \
|
||||
] $rfdc_dac_map
|
||||
|
||||
# Create instance: slice_iqswap_11_8_radio0, and set properties
|
||||
set slice_iqswap_11_8_radio0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 slice_iqswap_11_8_radio0 ]
|
||||
set_property -dict [ list \
|
||||
@@ -1428,7 +1413,7 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
connect_bd_intf_net -intf_net axi_interconnect_rf_M05_AXI [get_bd_intf_pins axi_interconnect_rf/M05_AXI] [get_bd_intf_pins reg_rf_axi_status/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_rf_M07_AXI [get_bd_intf_pins axi_interconnect_rf/M07_AXI] [get_bd_intf_pins reg_clock_gate_control/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_rf_M08_AXI [get_bd_intf_pins ThresholdRegister/S_AXI] [get_bd_intf_pins axi_interconnect_rf/M08_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_rf_M09_AXI [get_bd_intf_pins axi_interconnect_rf/M09_AXI] [get_bd_intf_pins reg_rfdc_tile_mapping/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_rf_M09_AXI [get_bd_intf_pins axi_interconnect_rf/M09_AXI] [get_bd_intf_pins axi_rfdc_info_memory_0/axi_s]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_rf_M10_AXI [get_bd_intf_pins axi_interconnect_rf/M10_AXI] [get_bd_intf_pins reg_rfdc_info/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_rf_M11_AXI [get_bd_intf_pins axi_interconnect_rf/M11_AXI] [get_bd_intf_pins reg_invert_iq_radio1/S_AXI]
|
||||
connect_bd_intf_net -intf_net axi_interconnect_rf_M12_AXI [get_bd_intf_pins axi_interconnect_rf/M12_AXI] [get_bd_intf_pins reg_rf_reset_control_radio1/S_AXI]
|
||||
@@ -1560,10 +1545,9 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
connect_bd_net -net rf_reset_controller_1_rAdcReset_n [get_bd_pins adc_rfdc_axi_resetn_r1clk] [get_bd_pins rf_data_converter/m2_axis_aresetn] [get_bd_pins rf_data_converter/m3_axis_aresetn] [get_bd_pins rf_reset_controller_1/rAdcReset_n]
|
||||
connect_bd_net -net rf_reset_controller_1_rDacReset_n [get_bd_pins dac_data_in_resetn_r1clk] [get_bd_pins rf_data_converter/s1_axis_aresetn] [get_bd_pins rf_reset_controller_1/rDacReset_n]
|
||||
connect_bd_net -net rf_rfdc_info_sclk_1 [get_bd_pins rf_rfdc_info_sclk] [get_bd_pins reg_rfdc_info/gpio_io_i]
|
||||
connect_bd_net -net rfdc_adc_map_dout [get_bd_pins reg_rfdc_tile_mapping/gpio_io_i] [get_bd_pins rfdc_adc_map/dout]
|
||||
connect_bd_net -net rfdc_regs_gpio_io_o [get_bd_pins reg_invert_iq_radio0/gpio_io_o] [get_bd_pins slice_iqswap_11_8_radio0/Din] [get_bd_pins slice_iqswap_3_0_radio0/Din]
|
||||
connect_bd_net -net s_axi_aresetn_0_1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins ThresholdRegister/s_axi_config_aresetn] [get_bd_pins axi_interconnect_rf/ARESETN] [get_bd_pins axi_interconnect_rf/M00_ARESETN] [get_bd_pins axi_interconnect_rf/M03_ARESETN] [get_bd_pins axi_interconnect_rf/M04_ARESETN] [get_bd_pins axi_interconnect_rf/M05_ARESETN] [get_bd_pins axi_interconnect_rf/M06_ARESETN] [get_bd_pins axi_interconnect_rf/M07_ARESETN] [get_bd_pins axi_interconnect_rf/M08_ARESETN] [get_bd_pins axi_interconnect_rf/M09_ARESETN] [get_bd_pins axi_interconnect_rf/M10_ARESETN] [get_bd_pins axi_interconnect_rf/M12_ARESETN] [get_bd_pins axi_interconnect_rf/S00_ARESETN] [get_bd_pins calibration_muxes/s_axi_config_aresetn] [get_bd_pins reg_clock_gate_control/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/s_axi_aresetn] [get_bd_pins reg_rf_axi_status/s_axi_aresetn] [get_bd_pins reg_rf_reset_control_radio0/s_axi_aresetn] [get_bd_pins reg_rf_reset_control_radio1/s_axi_aresetn] [get_bd_pins reg_rfdc_info/s_axi_aresetn] [get_bd_pins reg_rfdc_tile_mapping/s_axi_aresetn] [get_bd_pins rf_data_converter/s_axi_aresetn]
|
||||
connect_bd_net -net s_axi_config_clk_1 [get_bd_pins s_axi_config_clk] [get_bd_pins ThresholdRegister/s_axi_config_clk] [get_bd_pins axi_interconnect_rf/ACLK] [get_bd_pins axi_interconnect_rf/M00_ACLK] [get_bd_pins axi_interconnect_rf/M01_ACLK] [get_bd_pins axi_interconnect_rf/M03_ACLK] [get_bd_pins axi_interconnect_rf/M04_ACLK] [get_bd_pins axi_interconnect_rf/M05_ACLK] [get_bd_pins axi_interconnect_rf/M06_ACLK] [get_bd_pins axi_interconnect_rf/M07_ACLK] [get_bd_pins axi_interconnect_rf/M08_ACLK] [get_bd_pins axi_interconnect_rf/M09_ACLK] [get_bd_pins axi_interconnect_rf/M10_ACLK] [get_bd_pins axi_interconnect_rf/M12_ACLK] [get_bd_pins axi_interconnect_rf/S00_ACLK] [get_bd_pins calibration_muxes/s_axi_config_clk] [get_bd_pins clock_gates_0/ReliableClk] [get_bd_pins data_clock_mmcm/s_axi_aclk] [get_bd_pins reg_clock_gate_control/s_axi_aclk] [get_bd_pins reg_reset_mmcm/s_axi_aclk] [get_bd_pins reg_rf_axi_status/s_axi_aclk] [get_bd_pins reg_rf_reset_control_radio0/s_axi_aclk] [get_bd_pins reg_rf_reset_control_radio1/s_axi_aclk] [get_bd_pins reg_rfdc_info/s_axi_aclk] [get_bd_pins reg_rfdc_tile_mapping/s_axi_aclk] [get_bd_pins rf_data_converter/s_axi_aclk] [get_bd_pins rf_nco_reset_0/ConfigClk] [get_bd_pins rf_reset_controller_0/ConfigClk] [get_bd_pins rf_reset_controller_1/ConfigClk]
|
||||
connect_bd_net -net s_axi_aresetn_0_1 [get_bd_pins s_axi_config_aresetn] [get_bd_pins ThresholdRegister/s_axi_config_aresetn] [get_bd_pins axi_interconnect_rf/ARESETN] [get_bd_pins axi_interconnect_rf/M00_ARESETN] [get_bd_pins axi_interconnect_rf/M03_ARESETN] [get_bd_pins axi_interconnect_rf/M04_ARESETN] [get_bd_pins axi_interconnect_rf/M05_ARESETN] [get_bd_pins axi_interconnect_rf/M06_ARESETN] [get_bd_pins axi_interconnect_rf/M07_ARESETN] [get_bd_pins axi_interconnect_rf/M08_ARESETN] [get_bd_pins axi_interconnect_rf/M09_ARESETN] [get_bd_pins axi_interconnect_rf/M10_ARESETN] [get_bd_pins axi_interconnect_rf/M12_ARESETN] [get_bd_pins axi_interconnect_rf/S00_ARESETN] [get_bd_pins axi_rfdc_info_memory_0/s_axi_aresetn] [get_bd_pins calibration_muxes/s_axi_config_aresetn] [get_bd_pins reg_clock_gate_control/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/s_axi_aresetn] [get_bd_pins reg_rf_axi_status/s_axi_aresetn] [get_bd_pins reg_rf_reset_control_radio0/s_axi_aresetn] [get_bd_pins reg_rf_reset_control_radio1/s_axi_aresetn] [get_bd_pins reg_rfdc_info/s_axi_aresetn] [get_bd_pins rf_data_converter/s_axi_aresetn]
|
||||
connect_bd_net -net s_axi_config_clk_1 [get_bd_pins s_axi_config_clk] [get_bd_pins ThresholdRegister/s_axi_config_clk] [get_bd_pins axi_interconnect_rf/ACLK] [get_bd_pins axi_interconnect_rf/M00_ACLK] [get_bd_pins axi_interconnect_rf/M01_ACLK] [get_bd_pins axi_interconnect_rf/M03_ACLK] [get_bd_pins axi_interconnect_rf/M04_ACLK] [get_bd_pins axi_interconnect_rf/M05_ACLK] [get_bd_pins axi_interconnect_rf/M06_ACLK] [get_bd_pins axi_interconnect_rf/M07_ACLK] [get_bd_pins axi_interconnect_rf/M08_ACLK] [get_bd_pins axi_interconnect_rf/M09_ACLK] [get_bd_pins axi_interconnect_rf/M10_ACLK] [get_bd_pins axi_interconnect_rf/M12_ACLK] [get_bd_pins axi_interconnect_rf/S00_ACLK] [get_bd_pins axi_rfdc_info_memory_0/s_axi_aclk] [get_bd_pins calibration_muxes/s_axi_config_clk] [get_bd_pins clock_gates_0/ReliableClk] [get_bd_pins data_clock_mmcm/s_axi_aclk] [get_bd_pins reg_clock_gate_control/s_axi_aclk] [get_bd_pins reg_reset_mmcm/s_axi_aclk] [get_bd_pins reg_rf_axi_status/s_axi_aclk] [get_bd_pins reg_rf_reset_control_radio0/s_axi_aclk] [get_bd_pins reg_rf_reset_control_radio1/s_axi_aclk] [get_bd_pins reg_rfdc_info/s_axi_aclk] [get_bd_pins rf_data_converter/s_axi_aclk] [get_bd_pins rf_nco_reset_0/ConfigClk] [get_bd_pins rf_reset_controller_0/ConfigClk] [get_bd_pins rf_reset_controller_1/ConfigClk]
|
||||
connect_bd_net -net slice_iqswap_11_8_radio0_Dout [get_bd_pins radio0_invert_dac_iq_r0clk] [get_bd_pins slice_iqswap_11_8_radio0/Dout]
|
||||
connect_bd_net -net slice_iqswap_11_8_radio1_Dout [get_bd_pins radio1_invert_dac_iq_r1clk] [get_bd_pins slice_iqswap_11_8_radio1/Dout]
|
||||
connect_bd_net -net slice_iqswap_3_0_radio0_Dout [get_bd_pins radio0_invert_adc_iq_r0clk] [get_bd_pins slice_iqswap_3_0_radio0/Dout]
|
||||
@@ -1574,7 +1558,6 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
connect_bd_net -net x440_rf_reset_contro_0_r2DacReset_n [get_bd_pins dac_data_in_resetn_r0clk2x] [get_bd_pins rf_reset_controller_0/r2DacReset_n]
|
||||
connect_bd_net -net x440_rf_reset_contro_0_rAdcEnableData [get_bd_pins adc_enable_data_r0clk] [get_bd_pins rf_reset_controller_0/rAdcEnableData]
|
||||
connect_bd_net -net x440_rf_reset_contro_0_rDacReset_n [get_bd_pins dac_data_in_resetn_r0clk] [get_bd_pins rf_data_converter/s0_axis_aresetn] [get_bd_pins rf_reset_controller_0/rDacReset_n]
|
||||
connect_bd_net -net xlconstant_1_dout [get_bd_pins reg_rfdc_tile_mapping/gpio2_io_i] [get_bd_pins rfdc_dac_map/dout]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
@@ -4031,6 +4014,7 @@ proc create_root_design { parentCell } {
|
||||
assign_bd_address -offset 0x0010000A4000 -range 0x00004000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/eth_dma_internal/axi_eth_dma_internal/S_AXI_LITE/Reg] -force
|
||||
assign_bd_address -offset 0x001000155000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/ThresholdRegister/axi_gpio_0/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000154000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/calibration_muxes/axi_gpio_data/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000157000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/axi_rfdc_info_memory_0/axi_s/reg0] -force
|
||||
assign_bd_address -offset 0x001000000000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs ps/cpld_jtag_engine/S_AXI/reg0] -force
|
||||
assign_bd_address -offset 0x001000140000 -range 0x00010000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/data_clock_mmcm/s_axi_lite/Reg] -force
|
||||
assign_bd_address -offset 0x001200000000 -range 0x000200000000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs m_axi_app/Reg] -force
|
||||
@@ -4046,7 +4030,6 @@ proc create_root_design { parentCell } {
|
||||
assign_bd_address -offset 0x001000152000 -range 0x00000800 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control_radio0/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000152800 -range 0x00000800 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rf_reset_control_radio1/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000158000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rfdc_info/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000157000 -range 0x00001000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/reg_rfdc_tile_mapping/S_AXI/Reg] -force
|
||||
assign_bd_address -offset 0x001000100000 -range 0x00040000 -target_address_space [get_bd_addr_spaces ps/inst_zynq_ps/Data] [get_bd_addr_segs rfdc/rf_data_converter/s_axi/Reg] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_SG] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force
|
||||
assign_bd_address -offset 0x000800000000 -range 0x000800000000 -target_address_space [get_bd_addr_spaces ps/eth_dma_internal/axi_eth_dma_internal/Data_MM2S] [get_bd_addr_segs ps/inst_zynq_ps/SAXIGP1/HPC1_DDR_HIGH] -force
|
||||
|
||||
@@ -0,0 +1,141 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: axi_rfdc_info_memory
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This module is a bridge between the RFDC info memory and the AXI4-Lite bus.
|
||||
// The RFDC info memory contains information about the ADC / DAC configuration
|
||||
// of the RFDC block and their respective logical RFNoC channels.
|
||||
//
|
||||
// Parameters:
|
||||
//
|
||||
// TIMEOUT Control port will timeout after 2^TIMEOUT AXI clock cycles
|
||||
// AXI_ADDR_WIDTH Width of the AXI bus. Aliasing occurs if AXI_ADDR_WIDTH > CTRLPORT_AWIDTH
|
||||
// CTRLPORT_AWIDTH Number of address LSBs forwarded to m_ctrlport_req_addr
|
||||
//
|
||||
|
||||
|
||||
module axi_rfdc_info_memory #(
|
||||
parameter TIMEOUT = 2,
|
||||
parameter AXI_ADDR_WIDTH = 6,
|
||||
parameter CTRLPORT_AWIDTH = 6
|
||||
)(
|
||||
//Clock and reset
|
||||
input wire s_axi_aclk,
|
||||
input wire s_axi_aresetn,
|
||||
// AXI4-Lite: Write address port (domain: s_axi_aclk)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s AWADDR" *)
|
||||
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s AWVALID" *)
|
||||
input wire s_axi_awvalid,
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s AWREADY" *)
|
||||
output wire s_axi_awready,
|
||||
// AXI4-Lite: Write data port (domain: s_axi_aclk)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s WDATA" *)
|
||||
input wire [31:0] s_axi_wdata,
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s WSTRB" *)
|
||||
input wire [ 3:0] s_axi_wstrb,
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s WVALID" *)
|
||||
input wire s_axi_wvalid,
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s WREADY" *)
|
||||
output wire s_axi_wready,
|
||||
// AXI4-Lite: Write response port (domain: s_axi_aclk)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s BRESP" *)
|
||||
output wire [ 1:0] s_axi_bresp,
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s BVALID" *)
|
||||
output wire s_axi_bvalid,
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s BREADY" *)
|
||||
input wire s_axi_bready,
|
||||
// AXI4-Lite: Read address port (domain: s_axi_aclk)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s ARADDR" *)
|
||||
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s ARVALID" *)
|
||||
input wire s_axi_arvalid,
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s ARREADY" *)
|
||||
output wire s_axi_arready,
|
||||
// AXI4-Lite: Read data port (domain: s_axi_aclk)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s RDATA" *)
|
||||
output wire[31:0] s_axi_rdata,
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s RRESP" *)
|
||||
output wire[ 1:0] s_axi_rresp,
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s RVALID" *)
|
||||
output wire s_axi_rvalid,
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi_s RREADY" *)
|
||||
input wire s_axi_rready
|
||||
);
|
||||
|
||||
// synchronize reset
|
||||
wire resetn;
|
||||
reset_sync reset_syncx (
|
||||
.clk (s_axi_aclk), //input wire
|
||||
.reset_in (s_axi_aresetn), //input wire
|
||||
.reset_out(resetn) //output reg
|
||||
);
|
||||
|
||||
//ctrlport signals between memory and axi ctrlport bridge
|
||||
wire [19:0] ctrlport_req_addr;
|
||||
wire [ 3:0] ctrlport_req_byte_en;
|
||||
wire [31:0] ctrlport_req_data;
|
||||
wire ctrlport_req_rd;
|
||||
wire ctrlport_req_wr;
|
||||
wire ctrlport_resp_ack;
|
||||
wire [31:0] ctrlport_resp_data;
|
||||
wire [ 1:0] ctrlport_resp_status;
|
||||
|
||||
axil_ctrlport_master #(
|
||||
.TIMEOUT (TIMEOUT), //integer:=10
|
||||
.AXI_AWIDTH (AXI_ADDR_WIDTH), //integer:=17
|
||||
.CTRLPORT_AWIDTH(CTRLPORT_AWIDTH) //integer:=17
|
||||
) axil_ctrlport_masterx (
|
||||
.s_axi_aclk (s_axi_aclk), //input wire
|
||||
.s_axi_aresetn (s_axi_aresetn), //input wire
|
||||
.s_axi_awaddr (s_axi_awaddr), //input wire[(AXI_ADDR_WIDTH-1):0]
|
||||
.s_axi_awvalid (s_axi_awvalid), //input wire
|
||||
.s_axi_awready (s_axi_awready), //output reg
|
||||
.s_axi_wdata (s_axi_wdata), //input wire[31:0]
|
||||
.s_axi_wstrb (s_axi_wstrb), //input wire[3:0]
|
||||
.s_axi_wvalid (s_axi_wvalid), //input wire
|
||||
.s_axi_wready (s_axi_wready), //output reg
|
||||
.s_axi_bresp (s_axi_bresp), //output reg[1:0]
|
||||
.s_axi_bvalid (s_axi_bvalid), //output reg
|
||||
.s_axi_bready (s_axi_bready), //input wire
|
||||
.s_axi_araddr (s_axi_araddr), //input wire[(AXI_ADDR_WIDTH-1):0]
|
||||
.s_axi_arvalid (s_axi_arvalid), //input wire
|
||||
.s_axi_arready (s_axi_arready), //output reg
|
||||
.s_axi_rdata (s_axi_rdata), //output reg[31:0]
|
||||
.s_axi_rresp (s_axi_rresp), //output reg[1:0]
|
||||
.s_axi_rvalid (s_axi_rvalid), //output reg
|
||||
.s_axi_rready (s_axi_rready), //input wire
|
||||
.m_ctrlport_req_wr (ctrlport_req_wr), //output reg
|
||||
.m_ctrlport_req_rd (ctrlport_req_rd), //output reg
|
||||
.m_ctrlport_req_addr (ctrlport_req_addr), //output reg[19:0]
|
||||
.m_ctrlport_req_portid (), //output wire[9:0]
|
||||
.m_ctrlport_req_rem_epid (), //output wire[15:0]
|
||||
.m_ctrlport_req_rem_portid(), //output wire[9:0]
|
||||
.m_ctrlport_req_data (ctrlport_req_data), //output reg[31:0]
|
||||
.m_ctrlport_req_byte_en (ctrlport_req_byte_en), //output reg[3:0]
|
||||
.m_ctrlport_req_has_time (), //output wire
|
||||
.m_ctrlport_req_time (), //output wire[63:0]
|
||||
.m_ctrlport_resp_ack (ctrlport_resp_ack), //input wire
|
||||
.m_ctrlport_resp_status (ctrlport_resp_status), //input wire[1:0]
|
||||
.m_ctrlport_resp_data (ctrlport_resp_data) //input wire[31:0]
|
||||
);
|
||||
|
||||
rfdc_info_memory rfdc_info_memoryx (
|
||||
.clk (s_axi_aclk), //input logic
|
||||
.rst (~resetn), //input logic
|
||||
.s_ctrlport_req_addr (ctrlport_req_addr), //input logic[19:0]
|
||||
.s_ctrlport_req_byte_en(ctrlport_req_byte_en), //input logic[3:0]
|
||||
.s_ctrlport_req_data (ctrlport_req_data), //input logic[31:0]
|
||||
.s_ctrlport_req_rd (ctrlport_req_rd), //input logic
|
||||
.s_ctrlport_req_wr (ctrlport_req_wr), //input logic
|
||||
.s_ctrlport_resp_ack (ctrlport_resp_ack), //output logic
|
||||
.s_ctrlport_resp_data (ctrlport_resp_data), //output logic[31:0]
|
||||
.s_ctrlport_resp_status(ctrlport_resp_status) //output logic[1:0]
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,89 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: rfdc_info_memory
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This module implements a memory that stores the RFDC information for the
|
||||
// RFDCs in the RFSoC. The memory is accessed via a controlport interface.
|
||||
// The memory is initialized by a device specfic pkg_rfdc_memory_content.
|
||||
// The memory is read only.
|
||||
//
|
||||
|
||||
module rfdc_info_memory
|
||||
(
|
||||
// Clocks and Resets
|
||||
input logic clk,
|
||||
input logic rst,
|
||||
|
||||
// request
|
||||
input logic [19:0] s_ctrlport_req_addr,
|
||||
input logic [ 3:0] s_ctrlport_req_byte_en,
|
||||
input logic [31:0] s_ctrlport_req_data,
|
||||
input logic s_ctrlport_req_rd,
|
||||
input logic s_ctrlport_req_wr,
|
||||
|
||||
// response
|
||||
output logic s_ctrlport_resp_ack,
|
||||
output logic [31:0] s_ctrlport_resp_data,
|
||||
output logic [ 1:0] s_ctrlport_resp_status
|
||||
);
|
||||
|
||||
`include "../../../../lib/rfnoc/core/ctrlport.vh"
|
||||
import rfdc_info_pkg::*;
|
||||
`ifdef X410
|
||||
import x410_rfdc_memory_content_pkg::*;
|
||||
`else
|
||||
import x440_rfdc_memory_content_pkg::*;
|
||||
`endif
|
||||
|
||||
localparam int MEMORY_ADDR_SIZE = $clog2(NUM_ENTRIES);
|
||||
localparam int MEM_ADDR_INCR = 4;
|
||||
localparam int MEMORY_ADDR_LSB = $clog2(MEM_ADDR_INCR);
|
||||
|
||||
// create memory with the RFDC information
|
||||
rfdc_memory_entry_t rfdc_memory [0:NUM_ENTRIES-1];
|
||||
|
||||
initial begin
|
||||
// initialize memory
|
||||
for (int i = 0; i < NUM_ENTRIES; i++) begin
|
||||
rfdc_memory[i] = get_memory_entry(i);
|
||||
$info("Memory entry %d: %p", i, rfdc_memory[i]);
|
||||
end
|
||||
end
|
||||
|
||||
// connect memory to the controlport interface
|
||||
always_ff @(posedge clk) begin
|
||||
if (rst) begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
s_ctrlport_resp_data <= 32'b0;
|
||||
s_ctrlport_resp_status <= 2'b00;
|
||||
|
||||
// handle reads
|
||||
end else if (s_ctrlport_req_rd) begin
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
|
||||
// check overrange
|
||||
if (s_ctrlport_req_addr >= NUM_ENTRIES*MEM_ADDR_INCR) begin
|
||||
s_ctrlport_resp_data <= 32'b0;
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
end else begin
|
||||
s_ctrlport_resp_data <= rfdc_memory[s_ctrlport_req_addr[MEMORY_ADDR_LSB +: MEMORY_ADDR_SIZE]];
|
||||
s_ctrlport_resp_status <= CTRL_STS_OKAY;
|
||||
end
|
||||
|
||||
// handle writes
|
||||
end else if (s_ctrlport_req_wr) begin
|
||||
s_ctrlport_resp_ack <= 1'b1;
|
||||
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
|
||||
|
||||
// any other case
|
||||
end else begin
|
||||
s_ctrlport_resp_ack <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,91 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, A National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: rfdc_info_pkg
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// Typedefs for RFDC information memory which are used by the device specific
|
||||
// RFDC memory content packages.
|
||||
//
|
||||
|
||||
package rfdc_info_pkg;
|
||||
|
||||
typedef enum logic [1:0] {
|
||||
ENABLED = 2'b00,
|
||||
DISABLED = 2'b11
|
||||
} block_mode_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic is_adc;
|
||||
logic db;
|
||||
logic [1:0] channel;
|
||||
logic [1:0] reserved2;
|
||||
logic [1:0] tile;
|
||||
logic [1:0] block;
|
||||
block_mode_t block_mode;
|
||||
} rfdc_memory_entry_t;
|
||||
|
||||
// Empty entry constant
|
||||
localparam rfdc_memory_entry_t EMPTY_ENTRY = '{
|
||||
is_adc: 0,
|
||||
db: 0,
|
||||
channel: 0,
|
||||
reserved2: 0,
|
||||
tile: 0,
|
||||
block: 0,
|
||||
block_mode: DISABLED
|
||||
};
|
||||
|
||||
// current RFSoC has 8 DACs and 8 ADCs
|
||||
localparam int NUM_ENTRIES = 16;
|
||||
|
||||
endpackage
|
||||
|
||||
//XmlParse xml_on
|
||||
//<regmap name="RFDC_REGS_REGMAP">
|
||||
// <group name="RFDC_REGS">
|
||||
// <enumeratedtype name="RFDC_BLOCK_INFO_ENUM" showhex="true">
|
||||
// <value name="ENABLED" integer="0"/>
|
||||
// <value name="DISABLED" integer="3"/>
|
||||
// </enumeratedtype>
|
||||
// <regtype name="RFDC_INFO_MEMTYPE" size="32" writable="false">
|
||||
// <info>
|
||||
// This register provides information for one ADC/DAC within the RFSoC and its RFDC
|
||||
// configuration. There is further information on the RFNoC index of this channel.
|
||||
// The register is defined as a SystemVerilog typedef and consumed by MPM using the RFDC
|
||||
// Python register interface.
|
||||
// </info>
|
||||
// <bitfield name="BLOCK_MODE" range="1..0" type="RFDC_BLOCK_INFO_ENUM">
|
||||
// <info>The state of this ADC/DAC.</info>
|
||||
// </bitfield>
|
||||
// <bitfield name="BLOCK" range="3..2">
|
||||
// <info>Index of the ADC/DAC within the FPGA tile.</info>
|
||||
// </bitfield>
|
||||
// <bitfield name="TILE" range="5..4">
|
||||
// <info>
|
||||
// Zero based tile offset of the FPGA.
|
||||
// For DAC index i equals to FPGA tile 228+i.
|
||||
// For ADC index i equals to FPGA tile 224+i.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="RESERVED2" range="7..6">
|
||||
// <info>
|
||||
// Reserved for later use.
|
||||
// </info>
|
||||
// </bitfield>
|
||||
// <bitfield name="CHANNEL" range="9..8">
|
||||
// <info>Index of the RFNoC channel per DB.</info>
|
||||
// </bitfield>
|
||||
// <bitfield name="DB" range="10">
|
||||
// <info>DB index.</info>
|
||||
// </bitfield>
|
||||
// <bitfield name="IS_ADC" range="11">
|
||||
// <info>If the converter is an ADC this bit is set. Otherwise it is an DAC.</info>
|
||||
// </bitfield>
|
||||
// </regtype>
|
||||
// </group>
|
||||
//</regmap>
|
||||
//XmlParse xml_off
|
||||
@@ -0,0 +1,50 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: x410_rfdc_memory_content_pkg
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This package will generate the device specific RFDC memory entries to be
|
||||
// used by the RFDC memory module.
|
||||
//
|
||||
|
||||
package x410_rfdc_memory_content_pkg;
|
||||
|
||||
import rfdc_info_pkg::*;
|
||||
|
||||
function automatic rfdc_memory_entry_t get_memory_entry(
|
||||
input int i
|
||||
);
|
||||
|
||||
localparam USED_ENTRIES = 8;
|
||||
rfdc_memory_entry_t entries [USED_ENTRIES] = '{
|
||||
// See corresponding code in x4xx.sv where ADC data (adc_data_out_tdata) is
|
||||
// assigned to rx_data_qi.
|
||||
// RX has been swapped in Rev B -> block 1 = channel 0, block 0 = channel 1
|
||||
// ADCs are located in tile 224 and 226 of the RFSoC
|
||||
'{is_adc:1, db:0, channel:0, reserved2:0, tile:0, block:1, block_mode:ENABLED},
|
||||
'{is_adc:1, db:0, channel:1, reserved2:0, tile:0, block:0, block_mode:ENABLED},
|
||||
'{is_adc:1, db:1, channel:0, reserved2:0, tile:2, block:1, block_mode:ENABLED},
|
||||
'{is_adc:1, db:1, channel:1, reserved2:0, tile:2, block:0, block_mode:ENABLED},
|
||||
// See corresponding code in x4xx.sv where DAC data (dac_data_in_tdata) is
|
||||
// assigned from tx_data_qi.
|
||||
// TX uses a 1-1 mapping.
|
||||
// DACs are the first two blocks of tile 228 and 229
|
||||
'{is_adc:0, db:0, channel:0, reserved2:0, tile:0, block:0, block_mode:ENABLED},
|
||||
'{is_adc:0, db:0, channel:1, reserved2:0, tile:0, block:1, block_mode:ENABLED},
|
||||
'{is_adc:0, db:1, channel:0, reserved2:0, tile:1, block:0, block_mode:ENABLED},
|
||||
'{is_adc:0, db:1, channel:1, reserved2:0, tile:1, block:1, block_mode:ENABLED}
|
||||
};
|
||||
|
||||
if (i < USED_ENTRIES) begin
|
||||
return entries[i];
|
||||
// return an disable entry for remaining entries
|
||||
end else begin
|
||||
return EMPTY_ENTRY;
|
||||
end
|
||||
endfunction
|
||||
|
||||
endpackage
|
||||
@@ -0,0 +1,58 @@
|
||||
//
|
||||
// Copyright 2025 Ettus Research, a National Instruments Brand
|
||||
//
|
||||
// SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
//
|
||||
// Module: x440_rfdc_memory_content_pkg
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
// This package will generate the device specific RFDC memory entries to be
|
||||
// used by the RFDC memory module.
|
||||
//
|
||||
|
||||
package x440_rfdc_memory_content_pkg;
|
||||
|
||||
import rfdc_info_pkg::*;
|
||||
|
||||
function automatic rfdc_memory_entry_t get_memory_entry(
|
||||
input int i
|
||||
);
|
||||
localparam USED_ENTRIES = 16;
|
||||
rfdc_memory_entry_t entries [USED_ENTRIES] = '{
|
||||
// See corresponding code in x4xx.sv where ADC data (adc_data_out_tdata) is
|
||||
// assigned to rx_data_qi.
|
||||
// DB 0 uses tiles 224 and 225
|
||||
'{is_adc:1, db:0, channel:0, reserved2:0, tile:1, block:1, block_mode:ENABLED},
|
||||
'{is_adc:1, db:0, channel:1, reserved2:0, tile:0, block:1, block_mode:ENABLED},
|
||||
'{is_adc:1, db:0, channel:2, reserved2:0, tile:0, block:0, block_mode:ENABLED},
|
||||
'{is_adc:1, db:0, channel:3, reserved2:0, tile:1, block:0, block_mode:ENABLED},
|
||||
// DB 1 uses tiles 226 and 227
|
||||
'{is_adc:1, db:1, channel:0, reserved2:0, tile:3, block:1, block_mode:ENABLED},
|
||||
'{is_adc:1, db:1, channel:1, reserved2:0, tile:2, block:1, block_mode:ENABLED},
|
||||
'{is_adc:1, db:1, channel:2, reserved2:0, tile:2, block:0, block_mode:ENABLED},
|
||||
'{is_adc:1, db:1, channel:3, reserved2:0, tile:3, block:0, block_mode:ENABLED},
|
||||
|
||||
// See corresponding code in x4xx.sv where DAC data (dac_data_in_tdata) is
|
||||
// assigned from tx_data_qi.
|
||||
// DB 0 uses tile 228
|
||||
'{is_adc:0, db:0, channel:0, reserved2:0, tile:0, block:0, block_mode:ENABLED},
|
||||
'{is_adc:0, db:0, channel:1, reserved2:0, tile:0, block:2, block_mode:ENABLED},
|
||||
'{is_adc:0, db:0, channel:2, reserved2:0, tile:0, block:3, block_mode:ENABLED},
|
||||
'{is_adc:0, db:0, channel:3, reserved2:0, tile:0, block:1, block_mode:ENABLED},
|
||||
// DB 1 uses tile 229
|
||||
'{is_adc:0, db:1, channel:0, reserved2:0, tile:1, block:0, block_mode:ENABLED},
|
||||
'{is_adc:0, db:1, channel:1, reserved2:0, tile:1, block:2, block_mode:ENABLED},
|
||||
'{is_adc:0, db:1, channel:2, reserved2:0, tile:1, block:3, block_mode:ENABLED},
|
||||
'{is_adc:0, db:1, channel:3, reserved2:0, tile:1, block:1, block_mode:ENABLED}
|
||||
};
|
||||
|
||||
if (i < USED_ENTRIES) begin
|
||||
return entries[i];
|
||||
// return an disable entry for remaining entries
|
||||
end else begin
|
||||
return EMPTY_ENTRY;
|
||||
end
|
||||
endfunction
|
||||
|
||||
endpackage
|
||||
Reference in New Issue
Block a user