92 lines
2.6 KiB
Systemverilog
92 lines
2.6 KiB
Systemverilog
//
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// Copyright 2025 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfdc_info_pkg
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//
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// Description:
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//
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// Typedefs for RFDC information memory which are used by the device specific
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// RFDC memory content packages.
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//
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package rfdc_info_pkg;
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typedef enum logic [1:0] {
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ENABLED = 2'b00,
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DISABLED = 2'b11
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} block_mode_t;
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typedef struct packed {
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logic is_adc;
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logic db;
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logic [1:0] channel;
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logic [1:0] reserved2;
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logic [1:0] tile;
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logic [1:0] block;
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block_mode_t block_mode;
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} rfdc_memory_entry_t;
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// Empty entry constant
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localparam rfdc_memory_entry_t EMPTY_ENTRY = '{
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is_adc: 0,
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db: 0,
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channel: 0,
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reserved2: 0,
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tile: 0,
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block: 0,
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block_mode: DISABLED
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};
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// current RFSoC has 8 DACs and 8 ADCs
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localparam int NUM_ENTRIES = 16;
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endpackage
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//XmlParse xml_on
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//<regmap name="RFDC_REGS_REGMAP">
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// <group name="RFDC_REGS">
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// <enumeratedtype name="RFDC_BLOCK_INFO_ENUM" showhex="true">
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// <value name="ENABLED" integer="0"/>
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// <value name="DISABLED" integer="3"/>
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// </enumeratedtype>
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// <regtype name="RFDC_INFO_MEMTYPE" size="32" writable="false">
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// <info>
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// This register provides information for one ADC/DAC within the RFSoC and its RFDC
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// configuration. There is further information on the RFNoC index of this channel.
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// The register is defined as a SystemVerilog typedef and consumed by MPM using the RFDC
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// Python register interface.
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// </info>
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// <bitfield name="BLOCK_MODE" range="1..0" type="RFDC_BLOCK_INFO_ENUM">
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// <info>The state of this ADC/DAC.</info>
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// </bitfield>
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// <bitfield name="BLOCK" range="3..2">
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// <info>Index of the ADC/DAC within the FPGA tile.</info>
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// </bitfield>
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// <bitfield name="TILE" range="5..4">
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// <info>
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// Zero based tile offset of the FPGA.
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// For DAC index i equals to FPGA tile 228+i.
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// For ADC index i equals to FPGA tile 224+i.
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// </info>
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// </bitfield>
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// <bitfield name="RESERVED2" range="7..6">
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// <info>
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// Reserved for later use.
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// </info>
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// </bitfield>
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// <bitfield name="CHANNEL" range="9..8">
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// <info>Index of the RFNoC channel per DB.</info>
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// </bitfield>
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// <bitfield name="DB" range="10">
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// <info>DB index.</info>
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// </bitfield>
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// <bitfield name="IS_ADC" range="11">
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// <info>If the converter is an ADC this bit is set. Otherwise it is an DAC.</info>
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// </bitfield>
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// </regtype>
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// </group>
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//</regmap>
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//XmlParse xml_off
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