fpga: x440: remove extra synchronizer

Original-commit: a2f4fc49ac52b84593a8e529efa9c5ccbeacb325
This commit is contained in:
Javier Valenzuela
2023-10-17 10:18:17 -05:00
committed by Wade Fife
parent c5a4ea2f0e
commit 4e26d6946f
+2 -2
View File
@@ -422,13 +422,13 @@ module x4xx_pps_sync #(
endgenerate endgenerate
always @(posedge radio_clk[0]) begin always @(posedge radio_clk[0]) begin
pps_shift_reg_rc[3:0] <= {pps_shift_reg_rc[2:0], pps_delayed_prc_rc[0]}; pps_shift_reg_rc[3:0] <= {pps_shift_reg_rc[2:0], pps_delayed_prc};
// Restoring a one clock cycle pulse by feeding back to output value. // Restoring a one clock cycle pulse by feeding back to output value.
pps_out_rc[0] <= pps_shift_reg_rc[prc_rc_divider_rc[1:0]] & ~pps_out_rc[0] & pps_rc_enabled_rc[0]; pps_out_rc[0] <= pps_shift_reg_rc[prc_rc_divider_rc[1:0]] & ~pps_out_rc[0] & pps_rc_enabled_rc[0];
end end
always @(posedge radio_clk[1]) begin always @(posedge radio_clk[1]) begin
pps_shift_reg_rc[7:4] <= {pps_shift_reg_rc[6:4], pps_delayed_prc_rc[1]}; pps_shift_reg_rc[7:4] <= {pps_shift_reg_rc[6:4], pps_delayed_prc};
// Restoring a one clock cycle pulse by feeding back to output value. // Restoring a one clock cycle pulse by feeding back to output value.
pps_out_rc[1] <= pps_shift_reg_rc[prc_rc_divider_rc[3:2]] & ~pps_out_rc[1] & pps_rc_enabled_rc[1]; pps_out_rc[1] <= pps_shift_reg_rc[prc_rc_divider_rc[3:2]] & ~pps_out_rc[1] & pps_rc_enabled_rc[1];
end end