From 4e26d6946ffaaab5fa4653ceae6ce28bae3b9d2d Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Wed, 10 May 2023 07:01:42 -0500 Subject: [PATCH] fpga: x440: remove extra synchronizer Original-commit: a2f4fc49ac52b84593a8e529efa9c5ccbeacb325 --- top/x400/x4xx_pps_sync.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/top/x400/x4xx_pps_sync.v b/top/x400/x4xx_pps_sync.v index 2569782..8787777 100644 --- a/top/x400/x4xx_pps_sync.v +++ b/top/x400/x4xx_pps_sync.v @@ -422,13 +422,13 @@ module x4xx_pps_sync #( endgenerate always @(posedge radio_clk[0]) begin - pps_shift_reg_rc[3:0] <= {pps_shift_reg_rc[2:0], pps_delayed_prc_rc[0]}; + pps_shift_reg_rc[3:0] <= {pps_shift_reg_rc[2:0], pps_delayed_prc}; // Restoring a one clock cycle pulse by feeding back to output value. pps_out_rc[0] <= pps_shift_reg_rc[prc_rc_divider_rc[1:0]] & ~pps_out_rc[0] & pps_rc_enabled_rc[0]; end always @(posedge radio_clk[1]) begin - pps_shift_reg_rc[7:4] <= {pps_shift_reg_rc[6:4], pps_delayed_prc_rc[1]}; + pps_shift_reg_rc[7:4] <= {pps_shift_reg_rc[6:4], pps_delayed_prc}; // Restoring a one clock cycle pulse by feeding back to output value. pps_out_rc[1] <= pps_shift_reg_rc[prc_rc_divider_rc[3:2]] & ~pps_out_rc[1] & pps_rc_enabled_rc[1]; end