fpga: x400: Update SYSREF Delay and capture mechanism

Together with an update to the LMK04832 register config according to
TIs data sheet, all clock outputs are now aligned to SYSREF rising edge.
Therefore, I needed to adjust the SYSREF capture mechanism inside the
RFSoC and the SYSREF LMK Delay.
SYSREF is now captured first at the falling edge of PRC.
To be on the safe side, we are still double synchronizing SYSREF
afterwards on the rising edges of PRC.

As we are now independent of any MCR regarding timing constraints the
SYSREF Delay is also set to '0' for all X4xx devices.


Original-commit: b5cb4fac42ab530174e108455b730ffa1510d70a

top/x400/constraints/timing/x410.xdc

@@ -90,18 +90,17 @@ set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates
 # SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces
 # the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both
 # SYSREF and PLL reference clock are directly fed into the RFSoC.
-# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC
+# The LMK04832 is configured to output all clocks synchronized to the
-# output) with a double synchronizer and then transfered to the RFDC clock
+# rising edge of SYSREF. SYSREF is first captured by the FPGA fabric in the
-# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for
+# PRC clock domain (MMCM's PRC output) on the falling edge to meet setup and
-# sync. purposes.
+# hold times. Afterwards it is captured with a double synchronizer and then
-# SYSREF is a continuous signal running at PRC freq. / 25, and it is
+# transferred to the RFDC clock domain. Both SYSREF versions (PRC and RFDC)
-# intentionally shifted in the LMK chip to align it closer to the
+# are used by downstream logic for sync purposes.
-# PRC's falling edge.
+# The highest PRC frequency supported in MPM (64 MHz) is used for
-# The added delay follows the formula:
+# timing constraints.
-#   SYSREF LMK delay = 22 * sample clock period
+# Set SYSREF LMK Delay to 0 ns as we assume rising edge alignment from the
-# The highest sampling frequency supported in MPM (3.072 GHz) is used for
+# LMK04832 chip.
-# timing constraints. Therefore, SYSREF LMK's delay = 22 * (1 / 3.072e9).
+set sysref_lmk_delay 0
-set sysref_lmk_delay 7.161
 #
 # These are the signals' lengths and corresponding delays (assuming 170 ps/in):
 #   - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns

top/x400/constraints/timing/x440.xdc

@@ -76,15 +76,17 @@ set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates
 # SYSREF is generated by the LMK04832 clocking chip (SPLL), which also produces
 # the PLL reference clock (PRC) used to generate data clocks with a MMCM. Both
 # SYSREF and PLL reference clock are directly fed into the RFSoC.
-# SYSREF is captured by the FPGA fabric in the PRC clock domain (MMCM's PRC
+# The LMK04832 is configured to output all clocks synchronized to the
-# output) with a double synchronizer and then transfered to the RFDC clock
+# rising edge of SYSREF. SYSREF is first captured by the FPGA fabric in the
-# domain. Both SYSREF versions (PRC and RFDC) are used by downstream logic for
+# PRC clock domain (MMCM's PRC output) on the falling edge to meet setup and
-# sync. purposes.
+# hold times. Afterwards it is captured with a double synchronizer and then
-# SYSREF is a continuous signal intentionally shifted in the LMK chip to align
+# transferred to the RFDC clock domain. Both SYSREF versions (PRC and RFDC)
-# it closer to the PRC's falling edge.
+# are used by downstream logic for sync purposes.
 # The highest PRC frequency supported in MPM (64 MHz) is used for
-# timing constraints. Therefore, SYSREF LMK's delay = (1/64e6)/2.
+# timing constraints.
-set sysref_lmk_delay 7.8125
+# Set SYSREF LMK Delay to 0 ns as we assume rising edge alignment from the
+# LMK04832 chip.
+set sysref_lmk_delay 0
 #
 # These are the signals' lengths and corresponding delays (assuming 170 ps/in):
 #   - SYSREF --> 5794 mils (5.794 inches) = 0.985 ns

top/x400/rf/common/capture_sysref.v

@@ -32,15 +32,32 @@ module capture_sysref (
   output wire sysref_out_rclk  // RFDC output  (Domain: rfdc_clk).
 );
 
-  (* ASYNC_REG = "TRUE" *) reg sysref_pclk_ms = 1'b0;
+  (* ASYNC_REG = "TRUE" *) reg sysref_neg_pclk_ms = 1'b0;
-  reg sysref_pclk = 1'b0;
+  (* ASYNC_REG = "TRUE" *) reg sysref_pos_pclk_ms = 1'b0;
-  reg sysref_rclk = 1'b0;
+  reg sysref_pclk     = 1'b0;
+  reg sysref_rclk     = 1'b0;
 
-  // Capture SYSREF synchronously with the pll_ref_clk, but double-sync it just
+  // The following waveform illustrates the capture process of SYSREF.
-  // in case static timing isn't met so as not to destroy downstream logic.
+  //
+  // PRC                   ___/-----\_____/-----\_____/-----\_____/----
+  // SYSREF                ___/----------------------------------------
+  // falling edge FF MS    ---------|R|--------------------------------
+  // rising edge FF MS     ---------------|R|--------------------------
+  // rising edge FF        ---------------------------|R|--------------
+  //
+  // Capture SYSREF synchronously with the pll_ref_clk, but at the falling edge.
+  // This is done to ensure that SYSREF is captured well after its initial
+  // rising edge to ensure a stable signal.
+  // But to be on the safe side when combining this FPGA code with older
+  // LMK04832 MPM configuration (before June 2024), the signal is considered
+  // metastable and requires additional double synchronization.
+  always @ (negedge pll_ref_clk) begin
+    sysref_neg_pclk_ms <= sysref_in;
+  end
+  
   always @ (posedge pll_ref_clk) begin
-    sysref_pclk_ms <= sysref_in;
+    sysref_pos_pclk_ms  <= sysref_neg_pclk_ms;
-    sysref_pclk    <= sysref_pclk_ms;
+    sysref_pclk         <= sysref_pos_pclk_ms;
   end
 
   assign sysref_out_pclk = sysref_pclk;