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fpga: Update rfnoc_image_core for all targets

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Update rfnoc_image_core.v to take into account the new image_core_name
fields and version strings. Add new rfnoc_image_core.vh. Update YAML
where needed.


Original-commit: b0033158a4c520063540881451d8daac91e98714
This commit is contained in:
Wade Fife
2021-06-10 11:56:58 -05:00
committed by Aaron Rossetto
parent 235703e806
commit 43e32abd11
18 changed files with 6493 additions and 5781 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/e31x/e310_rfnoc_image_core.v
+239 -196
View File
@@ -1,68 +1,86 @@
// //
// Copyright 2020 Ettus Research, A National Instruments Brand // Copyright 2021 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: rfnoc_image_core (for e31x) // Module: rfnoc_image_core (for e31x)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) //
// Re-running that tool will overwrite this file! // Description:
// File generated on: 2020-09-08T10:54:16.062742 //
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:11.395850
// Source: e310_rfnoc_image_core.yml // Source: e310_rfnoc_image_core.yml
// Source SHA256: 00908abb846aaf175d1f8f2e75c6d39a3cd4958b326ab3125f4a1023c7b78b39 // Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc
//
`default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0} parameter CHDR_W = 64,
)( parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) (
// Clocks // Clocks
input wire chdr_aclk, input wire chdr_aclk,
input wire ctrl_aclk, input wire ctrl_aclk,
input wire core_arst, input wire core_arst,
input wire radio_clk, input wire radio_clk,
// Basic // Basic
input wire [15:0] device_id, input wire [ 15:0] device_id,
//// IO ports //////////////////////////////////
// ctrlport_radio // IO ports /////////////////////////
output wire [ 1-1:0] m_ctrlport_req_wr,
output wire [ 1-1:0] m_ctrlport_req_rd, // ctrlport_radio
output wire [ 20-1:0] m_ctrlport_req_addr, output wire [ 0:0] m_ctrlport_req_wr,
output wire [ 32-1:0] m_ctrlport_req_data, output wire [ 0:0] m_ctrlport_req_rd,
output wire [ 4-1:0] m_ctrlport_req_byte_en, output wire [ 19:0] m_ctrlport_req_addr,
output wire [ 1-1:0] m_ctrlport_req_has_time, output wire [ 31:0] m_ctrlport_req_data,
output wire [ 64-1:0] m_ctrlport_req_time, output wire [ 3:0] m_ctrlport_req_byte_en,
input wire [ 1-1:0] m_ctrlport_resp_ack, output wire [ 0:0] m_ctrlport_req_has_time,
input wire [ 2-1:0] m_ctrlport_resp_status, output wire [ 63:0] m_ctrlport_req_time,
input wire [ 32-1:0] m_ctrlport_resp_data, input wire [ 0:0] m_ctrlport_resp_ack,
// time_keeper input wire [ 1:0] m_ctrlport_resp_status,
input wire [ 64-1:0] radio_time, input wire [ 31:0] m_ctrlport_resp_data,
// x300_radio // time_keeper
input wire [ 64-1:0] radio_rx_data, input wire [ 63:0] radio_time,
input wire [ 2-1:0] radio_rx_stb, // x300_radio
output wire [ 2-1:0] radio_rx_running, input wire [ 63:0] radio_rx_data,
output wire [ 64-1:0] radio_tx_data, input wire [ 1:0] radio_rx_stb,
input wire [ 2-1:0] radio_tx_stb, output wire [ 1:0] radio_rx_running,
output wire [ 2-1:0] radio_tx_running, output wire [ 63:0] radio_tx_data,
// Transport 0 (dma dma) input wire [ 1:0] radio_tx_stb,
input wire [64-1:0] s_dma_tdata, output wire [ 1:0] radio_tx_running,
input wire s_dma_tlast,
input wire s_dma_tvalid, // Transport Adapters ///////////////
output wire s_dma_tready,
output wire [64-1:0] m_dma_tdata, // Transport 0 (dma)
output wire m_dma_tlast, input wire [CHDR_W-1:0] s_dma_tdata,
output wire m_dma_tvalid, input wire s_dma_tlast,
input wire m_dma_tready input wire s_dma_tvalid,
output wire s_dma_tready,
output wire [CHDR_W-1:0] m_dma_tdata,
output wire m_dma_tlast,
output wire m_dma_tvalid,
input wire m_dma_tready
); );
localparam CHDR_W = 64;
localparam MTU = 10;
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// CHDR Crossbar // CHDR Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
@@ -95,12 +113,12 @@ module rfnoc_image_core #(
.clk (rfnoc_chdr_clk), .clk (rfnoc_chdr_clk),
.reset (rfnoc_chdr_rst), .reset (rfnoc_chdr_rst),
.device_id (device_id), .device_id (device_id),
.s_axis_tdata ({ep1_to_xb_tdata, ep0_to_xb_tdata, s_dma_tdata}), .s_axis_tdata ({ep1_to_xb_tdata , ep0_to_xb_tdata , s_dma_tdata }),
.s_axis_tlast ({ep1_to_xb_tlast, ep0_to_xb_tlast, s_dma_tlast}), .s_axis_tlast ({ep1_to_xb_tlast , ep0_to_xb_tlast , s_dma_tlast }),
.s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid}), .s_axis_tvalid ({ep1_to_xb_tvalid, ep0_to_xb_tvalid, s_dma_tvalid}),
.s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready}), .s_axis_tready ({ep1_to_xb_tready, ep0_to_xb_tready, s_dma_tready}),
.m_axis_tdata ({xb_to_ep1_tdata, xb_to_ep0_tdata, m_dma_tdata}), .m_axis_tdata ({xb_to_ep1_tdata , xb_to_ep0_tdata , m_dma_tdata }),
.m_axis_tlast ({xb_to_ep1_tlast, xb_to_ep0_tlast, m_dma_tlast}), .m_axis_tlast ({xb_to_ep1_tlast , xb_to_ep0_tlast , m_dma_tlast }),
.m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid}), .m_axis_tvalid ({xb_to_ep1_tvalid, xb_to_ep0_tvalid, m_dma_tvalid}),
.m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready}), .m_axis_tready ({xb_to_ep1_tready, xb_to_ep0_tready, m_dma_tready}),
.ext_rtcfg_stb (1'h0), .ext_rtcfg_stb (1'h0),
@@ -109,9 +127,18 @@ module rfnoc_image_core #(
.ext_rtcfg_ack () .ext_rtcfg_ack ()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Stream Endpoints // Stream Endpoints
// ---------------------------------------------------- //---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 16384;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
@@ -121,8 +148,8 @@ module rfnoc_image_core #(
wire s_ep0_in0_tlast; wire s_ep0_in0_tlast;
wire s_ep0_in0_tvalid; wire s_ep0_in0_tvalid;
wire s_ep0_in0_tready; wire s_ep0_in0_tready;
wire [31:0] m_ep0_ctrl_tdata , s_ep0_ctrl_tdata ; wire [ 31:0] m_ep0_ctrl_tdata, s_ep0_ctrl_tdata;
wire m_ep0_ctrl_tlast , s_ep0_ctrl_tlast ; wire m_ep0_ctrl_tlast, s_ep0_ctrl_tlast;
wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid; wire m_ep0_ctrl_tvalid, s_ep0_ctrl_tvalid;
wire m_ep0_ctrl_tready, s_ep0_ctrl_tready; wire m_ep0_ctrl_tready, s_ep0_ctrl_tready;
@@ -135,23 +162,23 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk ), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst ), .rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ), .rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id ), .device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep0_tdata ), .s_axis_chdr_tdata (xb_to_ep0_tdata),
.s_axis_chdr_tlast (xb_to_ep0_tlast ), .s_axis_chdr_tlast (xb_to_ep0_tlast),
.s_axis_chdr_tvalid (xb_to_ep0_tvalid ), .s_axis_chdr_tvalid (xb_to_ep0_tvalid),
.s_axis_chdr_tready (xb_to_ep0_tready ), .s_axis_chdr_tready (xb_to_ep0_tready),
.m_axis_chdr_tdata (ep0_to_xb_tdata ), .m_axis_chdr_tdata (ep0_to_xb_tdata),
.m_axis_chdr_tlast (ep0_to_xb_tlast ), .m_axis_chdr_tlast (ep0_to_xb_tlast),
.m_axis_chdr_tvalid (ep0_to_xb_tvalid ), .m_axis_chdr_tvalid (ep0_to_xb_tvalid),
.m_axis_chdr_tready (ep0_to_xb_tready ), .m_axis_chdr_tready (ep0_to_xb_tready),
.s_axis_data_tdata ({s_ep0_in0_tdata}), .s_axis_data_tdata ({s_ep0_in0_tdata}),
.s_axis_data_tlast ({s_ep0_in0_tlast}), .s_axis_data_tlast ({s_ep0_in0_tlast}),
.s_axis_data_tvalid ({s_ep0_in0_tvalid}), .s_axis_data_tvalid ({s_ep0_in0_tvalid}),
@@ -160,20 +187,28 @@ module rfnoc_image_core #(
.m_axis_data_tlast ({m_ep0_out0_tlast}), .m_axis_data_tlast ({m_ep0_out0_tlast}),
.m_axis_data_tvalid ({m_ep0_out0_tvalid}), .m_axis_data_tvalid ({m_ep0_out0_tvalid}),
.m_axis_data_tready ({m_ep0_out0_tready}), .m_axis_data_tready ({m_ep0_out0_tready}),
.s_axis_ctrl_tdata (s_ep0_ctrl_tdata ), .s_axis_ctrl_tdata (s_ep0_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep0_ctrl_tlast ), .s_axis_ctrl_tlast (s_ep0_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid), .s_axis_ctrl_tvalid (s_ep0_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep0_ctrl_tready), .s_axis_ctrl_tready (s_ep0_ctrl_tready),
.m_axis_ctrl_tdata (m_ep0_ctrl_tdata ), .m_axis_ctrl_tdata (m_ep0_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep0_ctrl_tlast ), .m_axis_ctrl_tlast (m_ep0_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid), .m_axis_ctrl_tvalid (m_ep0_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep0_ctrl_tready), .m_axis_ctrl_tready (m_ep0_ctrl_tready),
.strm_seq_err_stb ( ), .strm_seq_err_stb (),
.strm_data_err_stb ( ), .strm_data_err_stb (),
.strm_route_err_stb ( ), .strm_route_err_stb (),
.signal_data_err (1'b0 ) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 16384;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
@@ -182,8 +217,8 @@ module rfnoc_image_core #(
wire s_ep1_in0_tlast; wire s_ep1_in0_tlast;
wire s_ep1_in0_tvalid; wire s_ep1_in0_tvalid;
wire s_ep1_in0_tready; wire s_ep1_in0_tready;
wire [31:0] m_ep1_ctrl_tdata , s_ep1_ctrl_tdata ; wire [ 31:0] m_ep1_ctrl_tdata, s_ep1_ctrl_tdata;
wire m_ep1_ctrl_tlast , s_ep1_ctrl_tlast ; wire m_ep1_ctrl_tlast, s_ep1_ctrl_tlast;
wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid; wire m_ep1_ctrl_tvalid, s_ep1_ctrl_tvalid;
wire m_ep1_ctrl_tready, s_ep1_ctrl_tready; wire m_ep1_ctrl_tready, s_ep1_ctrl_tready;
@@ -196,23 +231,23 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
.rfnoc_chdr_clk (rfnoc_chdr_clk ), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_chdr_rst (rfnoc_chdr_rst ), .rfnoc_chdr_rst (rfnoc_chdr_rst),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk ), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.rfnoc_ctrl_rst (rfnoc_ctrl_rst ), .rfnoc_ctrl_rst (rfnoc_ctrl_rst),
.device_id (device_id ), .device_id (device_id),
.s_axis_chdr_tdata (xb_to_ep1_tdata ), .s_axis_chdr_tdata (xb_to_ep1_tdata),
.s_axis_chdr_tlast (xb_to_ep1_tlast ), .s_axis_chdr_tlast (xb_to_ep1_tlast),
.s_axis_chdr_tvalid (xb_to_ep1_tvalid ), .s_axis_chdr_tvalid (xb_to_ep1_tvalid),
.s_axis_chdr_tready (xb_to_ep1_tready ), .s_axis_chdr_tready (xb_to_ep1_tready),
.m_axis_chdr_tdata (ep1_to_xb_tdata ), .m_axis_chdr_tdata (ep1_to_xb_tdata),
.m_axis_chdr_tlast (ep1_to_xb_tlast ), .m_axis_chdr_tlast (ep1_to_xb_tlast),
.m_axis_chdr_tvalid (ep1_to_xb_tvalid ), .m_axis_chdr_tvalid (ep1_to_xb_tvalid),
.m_axis_chdr_tready (ep1_to_xb_tready ), .m_axis_chdr_tready (ep1_to_xb_tready),
.s_axis_data_tdata ({s_ep1_in0_tdata}), .s_axis_data_tdata ({s_ep1_in0_tdata}),
.s_axis_data_tlast ({s_ep1_in0_tlast}), .s_axis_data_tlast ({s_ep1_in0_tlast}),
.s_axis_data_tvalid ({s_ep1_in0_tvalid}), .s_axis_data_tvalid ({s_ep1_in0_tvalid}),
@@ -221,34 +256,33 @@ module rfnoc_image_core #(
.m_axis_data_tlast ({m_ep1_out0_tlast}), .m_axis_data_tlast ({m_ep1_out0_tlast}),
.m_axis_data_tvalid ({m_ep1_out0_tvalid}), .m_axis_data_tvalid ({m_ep1_out0_tvalid}),
.m_axis_data_tready ({m_ep1_out0_tready}), .m_axis_data_tready ({m_ep1_out0_tready}),
.s_axis_ctrl_tdata (s_ep1_ctrl_tdata ), .s_axis_ctrl_tdata (s_ep1_ctrl_tdata),
.s_axis_ctrl_tlast (s_ep1_ctrl_tlast ), .s_axis_ctrl_tlast (s_ep1_ctrl_tlast),
.s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid), .s_axis_ctrl_tvalid (s_ep1_ctrl_tvalid),
.s_axis_ctrl_tready (s_ep1_ctrl_tready), .s_axis_ctrl_tready (s_ep1_ctrl_tready),
.m_axis_ctrl_tdata (m_ep1_ctrl_tdata ), .m_axis_ctrl_tdata (m_ep1_ctrl_tdata),
.m_axis_ctrl_tlast (m_ep1_ctrl_tlast ), .m_axis_ctrl_tlast (m_ep1_ctrl_tlast),
.m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid), .m_axis_ctrl_tvalid (m_ep1_ctrl_tvalid),
.m_axis_ctrl_tready (m_ep1_ctrl_tready), .m_axis_ctrl_tready (m_ep1_ctrl_tready),
.strm_seq_err_stb ( ), .strm_seq_err_stb (),
.strm_data_err_stb ( ), .strm_data_err_stb (),
.strm_route_err_stb ( ), .strm_route_err_stb (),
.signal_data_err (1'b0 ) .signal_data_err (1'b0)
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Control Crossbar // Control Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata , s_core_ctrl_tdata ; wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast , s_core_ctrl_tlast ; wire m_core_ctrl_tlast, s_core_ctrl_tlast;
wire m_core_ctrl_tvalid, s_core_ctrl_tvalid; wire m_core_ctrl_tvalid, s_core_ctrl_tvalid;
wire m_core_ctrl_tready, s_core_ctrl_tready; wire m_core_ctrl_tready, s_core_ctrl_tready;
wire [31:0] m_radio0_ctrl_tdata , s_radio0_ctrl_tdata ; wire [31:0] m_radio0_ctrl_tdata, s_radio0_ctrl_tdata;
wire m_radio0_ctrl_tlast , s_radio0_ctrl_tlast ; wire m_radio0_ctrl_tlast, s_radio0_ctrl_tlast;
wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid; wire m_radio0_ctrl_tvalid, s_radio0_ctrl_tvalid;
wire m_radio0_ctrl_tready, s_radio0_ctrl_tready; wire m_radio0_ctrl_tready, s_radio0_ctrl_tready;
axis_ctrl_crossbar_nxn #( axis_ctrl_crossbar_nxn #(
.WIDTH (32), .WIDTH (32),
@@ -272,9 +306,11 @@ module rfnoc_image_core #(
.deadlock_detected() .deadlock_detected()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// RFNoC Core Kernel // RFNoC Core Kernel
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [(512*1)-1:0] rfnoc_core_config, rfnoc_core_status; wire [(512*1)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #( rfnoc_core_kernel #(
@@ -299,12 +335,12 @@ module rfnoc_image_core #(
.core_chdr_rst (rfnoc_chdr_rst), .core_chdr_rst (rfnoc_chdr_rst),
.core_ctrl_clk (rfnoc_ctrl_clk), .core_ctrl_clk (rfnoc_ctrl_clk),
.core_ctrl_rst (rfnoc_ctrl_rst), .core_ctrl_rst (rfnoc_ctrl_rst),
.s_axis_ctrl_tdata (s_core_ctrl_tdata ), .s_axis_ctrl_tdata (s_core_ctrl_tdata),
.s_axis_ctrl_tlast (s_core_ctrl_tlast ), .s_axis_ctrl_tlast (s_core_ctrl_tlast),
.s_axis_ctrl_tvalid (s_core_ctrl_tvalid), .s_axis_ctrl_tvalid (s_core_ctrl_tvalid),
.s_axis_ctrl_tready (s_core_ctrl_tready), .s_axis_ctrl_tready (s_core_ctrl_tready),
.m_axis_ctrl_tdata (m_core_ctrl_tdata ), .m_axis_ctrl_tdata (m_core_ctrl_tdata),
.m_axis_ctrl_tlast (m_core_ctrl_tlast ), .m_axis_ctrl_tlast (m_core_ctrl_tlast),
.m_axis_ctrl_tvalid (m_core_ctrl_tvalid), .m_axis_ctrl_tvalid (m_core_ctrl_tvalid),
.m_axis_ctrl_tready (m_core_ctrl_tready), .m_axis_ctrl_tready (m_core_ctrl_tready),
.device_id (device_id), .device_id (device_id),
@@ -312,13 +348,15 @@ module rfnoc_image_core #(
.rfnoc_core_status (rfnoc_core_status) .rfnoc_core_status (rfnoc_core_status)
); );
// ----------------------------------------------------
// Blocks
// ----------------------------------------------------
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// radio0 // radio0
// ---------------------------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
@@ -329,113 +367,115 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid; wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 1-1:0] radio0_m_ctrlport_req_rd; wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 20-1:0] radio0_m_ctrlport_req_addr; wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 32-1:0] radio0_m_ctrlport_req_data; wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio0_m_ctrlport_req_has_time; wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 64-1:0] radio0_m_ctrlport_req_time; wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 1-1:0] radio0_m_ctrlport_resp_ack; wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 2-1:0] radio0_m_ctrlport_resp_status; wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 32-1:0] radio0_m_ctrlport_resp_data; wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio0_radio_time; wire [ 63:0] radio0_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio0_radio_rx_data; wire [ 63:0] radio0_radio_rx_data;
wire [ 2-1:0] radio0_radio_rx_stb; wire [ 1:0] radio0_radio_rx_stb;
wire [ 2-1:0] radio0_radio_rx_running; wire [ 1:0] radio0_radio_rx_running;
wire [ 64-1:0] radio0_radio_tx_data; wire [ 63:0] radio0_radio_tx_data;
wire [ 2-1:0] radio0_radio_tx_stb; wire [ 1:0] radio0_radio_tx_stb;
wire [ 2-1:0] radio0_radio_tx_running; wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID(2), .THIS_PORTID (2),
.CHDR_W(CHDR_W), .CHDR_W (CHDR_W),
.NUM_PORTS(2), .NUM_PORTS (2),
.MTU(MTU) .MTU (MTU)
) b_radio0_0 ( ) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk), .rfnoc_chdr_clk (rfnoc_chdr_clk),
.rfnoc_ctrl_clk (rfnoc_ctrl_clk), .rfnoc_ctrl_clk (rfnoc_ctrl_clk),
.radio_clk(radio0_radio_clk), .radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_wr(radio0_m_ctrlport_req_wr), .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_rd(radio0_m_ctrlport_req_rd), .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
.m_ctrlport_req_addr(radio0_m_ctrlport_req_addr), .m_ctrlport_req_data (radio0_m_ctrlport_req_data),
.m_ctrlport_req_data(radio0_m_ctrlport_req_data),
.m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en), .m_ctrlport_req_byte_en(radio0_m_ctrlport_req_byte_en),
.m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time), .m_ctrlport_req_has_time(radio0_m_ctrlport_req_has_time),
.m_ctrlport_req_time(radio0_m_ctrlport_req_time), .m_ctrlport_req_time (radio0_m_ctrlport_req_time),
.m_ctrlport_resp_ack(radio0_m_ctrlport_resp_ack), .m_ctrlport_resp_ack (radio0_m_ctrlport_resp_ack),
.m_ctrlport_resp_status(radio0_m_ctrlport_resp_status), .m_ctrlport_resp_status(radio0_m_ctrlport_resp_status),
.m_ctrlport_resp_data(radio0_m_ctrlport_resp_data), .m_ctrlport_resp_data(radio0_m_ctrlport_resp_data),
.radio_time(radio0_radio_time), .radio_time (radio0_radio_time),
.radio_rx_data(radio0_radio_rx_data), .radio_rx_data (radio0_radio_rx_data),
.radio_rx_stb(radio0_radio_rx_stb), .radio_rx_stb (radio0_radio_rx_stb),
.radio_rx_running(radio0_radio_rx_running), .radio_rx_running (radio0_radio_rx_running),
.radio_tx_data(radio0_radio_tx_data), .radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb(radio0_radio_tx_stb), .radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running(radio0_radio_tx_running), .radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
.s_rfnoc_chdr_tvalid({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), .s_rfnoc_chdr_tready ({s_radio0_in_1_tready, s_radio0_in_0_tready}),
.s_rfnoc_chdr_tready({s_radio0_in_1_tready, s_radio0_in_0_tready}), .m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }),
.m_rfnoc_chdr_tdata ({m_radio0_out_1_tdata , m_radio0_out_0_tdata }), .m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }),
.m_rfnoc_chdr_tlast ({m_radio0_out_1_tlast , m_radio0_out_0_tlast }), .m_rfnoc_chdr_tvalid ({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}),
.m_rfnoc_chdr_tvalid({m_radio0_out_1_tvalid, m_radio0_out_0_tvalid}), .m_rfnoc_chdr_tready ({m_radio0_out_1_tready, m_radio0_out_0_tready}),
.m_rfnoc_chdr_tready({m_radio0_out_1_tready, m_radio0_out_0_tready}), .s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata),
.s_rfnoc_ctrl_tdata (s_radio0_ctrl_tdata ), .s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast),
.s_rfnoc_ctrl_tlast (s_radio0_ctrl_tlast ), .s_rfnoc_ctrl_tvalid (s_radio0_ctrl_tvalid),
.s_rfnoc_ctrl_tvalid(s_radio0_ctrl_tvalid), .s_rfnoc_ctrl_tready (s_radio0_ctrl_tready),
.s_rfnoc_ctrl_tready(s_radio0_ctrl_tready), .m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata),
.m_rfnoc_ctrl_tdata (m_radio0_ctrl_tdata ), .m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast),
.m_rfnoc_ctrl_tlast (m_radio0_ctrl_tlast ), .m_rfnoc_ctrl_tvalid (m_radio0_ctrl_tvalid),
.m_rfnoc_ctrl_tvalid(m_radio0_ctrl_tvalid), .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
.m_rfnoc_ctrl_tready(m_radio0_ctrl_tready)
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Static Router // Static Router
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_radio0_in_0_tdata = m_ep0_out0_tdata ;
assign s_radio0_in_0_tlast = m_ep0_out0_tlast ; assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
assign m_ep0_out0_tready = s_radio0_in_0_tready; assign m_ep0_out0_tready = s_radio0_in_0_tready;
assign s_radio0_in_1_tdata = m_ep1_out0_tdata ; assign s_radio0_in_1_tdata = m_ep1_out0_tdata;
assign s_radio0_in_1_tlast = m_ep1_out0_tlast ; assign s_radio0_in_1_tlast = m_ep1_out0_tlast;
assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid; assign s_radio0_in_1_tvalid = m_ep1_out0_tvalid;
assign m_ep1_out0_tready = s_radio0_in_1_tready; assign m_ep1_out0_tready = s_radio0_in_1_tready;
assign s_ep0_in0_tdata = m_radio0_out_0_tdata ; assign s_ep0_in0_tdata = m_radio0_out_0_tdata;
assign s_ep0_in0_tlast = m_radio0_out_0_tlast ; assign s_ep0_in0_tlast = m_radio0_out_0_tlast;
assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid; assign s_ep0_in0_tvalid = m_radio0_out_0_tvalid;
assign m_radio0_out_0_tready = s_ep0_in0_tready; assign m_radio0_out_0_tready = s_ep0_in0_tready;
assign s_ep1_in0_tdata = m_radio0_out_1_tdata ; assign s_ep1_in0_tdata = m_radio0_out_1_tdata;
assign s_ep1_in0_tlast = m_radio0_out_1_tlast ; assign s_ep1_in0_tlast = m_radio0_out_1_tlast;
assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid; assign s_ep1_in0_tvalid = m_radio0_out_1_tvalid;
assign m_radio0_out_1_tready = s_ep1_in0_tready; assign m_radio0_out_1_tready = s_ep1_in0_tready;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Unused Ports // Unused Ports
// ---------------------------------------------------- //---------------------------------------------------------------------------
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains // Clock Domains
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk; assign radio0_radio_clk = radio_clk;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// IO Port Connection // IO Port Connection
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Master/Slave Connections: // Master/Slave Connections:
assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd; assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd;
@@ -459,3 +499,6 @@ module rfnoc_image_core #(
assign radio0_radio_time = radio_time; assign radio0_radio_time = radio_time;
endmodule endmodule
`default_nettype wire
top/e31x/e310_rfnoc_image_core.vh
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for e31x)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:11.441866
// Source: e310_rfnoc_image_core.yml
// Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/e31x/e310_rfnoc_image_core.yml
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@@ -6,7 +6,8 @@ license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used
version: '1.0' # File version version: '1.0' # File version
rfnoc_version: '1.0' # RFNoC protocol version rfnoc_version: '1.0' # RFNoC protocol version
chdr_width: 64 # Bit width of the CHDR bus for this image chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'e310' device: 'e310' # USRP type
image_core_name: 'e310' # Name to use for the RFNoC Image Core files
default_target: 'E310_SG3' default_target: 'E310_SG3'
# A list of all stream endpoints in design # A list of all stream endpoints in design
top/e320/e320_rfnoc_image_core.v
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for e320)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:10.746455
// Source: e320_rfnoc_image_core.yml
// Source SHA256: 8b38ab7ba86e214c213ab62a63b698739c0858fdf10fcc5b737f87a56fb04454
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n300_bist_image_core.v
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top/n3xx/n300_rfnoc_image_core.vh
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n300)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:08.505495
// Source: n300_rfnoc_image_core.yml
// Source SHA256: 64f2b862b3e60cb0456befb88ea28825b6bba271ff4e86a24ab618932773a861
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n310_bist_image_core.v
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top/n3xx/n310_rfnoc_image_core.vh
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n310)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:09.279594
// Source: n310_rfnoc_image_core.yml
// Source SHA256: cc561a3de48fea9e224425413802738d125393f55f6dd46e196db8fdabe09284
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n320_bist_image_core.v
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top/n3xx/n320_rfnoc_image_core.vh
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@@ -0,0 +1,21 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n320)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:09.997079
// Source: n320_rfnoc_image_core.yml
// Source SHA256: 3c3a33be8bc2e3b3a7268ba3e07001c6dc6c21af4c9027309a787ac8404e5e8f
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x300/x300_rfnoc_image_core.v
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top/x300/x300_rfnoc_image_core.vh
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x300)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:07.013471
// Source: x300_rfnoc_image_core.yml
// Source SHA256: 32a28be8a0bcbe6bb9a5df0058b3c813741fa80c1faafd11270d8b500d7d9b85
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x300/x310_rfnoc_image_core.v
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//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x300)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:07.779170
// Source: x310_rfnoc_image_core.yml
// Source SHA256: 7a01e3b4aa95b9e5b59f627d5a7d3f27c16afb4bb6bdad1f7fb9a624fb4b9647
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }