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fpga: Update rfnoc_image_core for all targets

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Update rfnoc_image_core.v to take into account the new image_core_name
fields and version strings. Add new rfnoc_image_core.vh. Update YAML
where needed.


Original-commit: b0033158a4c520063540881451d8daac91e98714
This commit is contained in:
Wade Fife
2021-06-10 11:56:58 -05:00
committed by Aaron Rossetto
parent 235703e806
commit 43e32abd11
18 changed files with 6493 additions and 5781 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/e31x/e310_rfnoc_image_core.v
+116 -73
View File
@@ -1,18 +1,31 @@
// //
// Copyright 2020 Ettus Research, A National Instruments Brand // Copyright 2021 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: rfnoc_image_core (for e31x) // Module: rfnoc_image_core (for e31x)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) //
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// File generated on: 2020-09-08T10:54:16.062742 //
// File generated on: 2021-05-03T08:51:11.395850
// Source: e310_rfnoc_image_core.yml // Source: e310_rfnoc_image_core.yml
// Source SHA256: 00908abb846aaf175d1f8f2e75c6d39a3cd4958b326ab3125f4a1023c7b78b39 // Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc
//
`default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0} parameter CHDR_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) ( ) (
// Clocks // Clocks
input wire chdr_aclk, input wire chdr_aclk,
@@ -21,48 +34,53 @@ module rfnoc_image_core #(
input wire radio_clk, input wire radio_clk,
// Basic // Basic
input wire [ 15:0] device_id, input wire [ 15:0] device_id,
//// IO ports //////////////////////////////////
// IO ports /////////////////////////
// ctrlport_radio // ctrlport_radio
output wire [ 1-1:0] m_ctrlport_req_wr, output wire [ 0:0] m_ctrlport_req_wr,
output wire [ 1-1:0] m_ctrlport_req_rd, output wire [ 0:0] m_ctrlport_req_rd,
output wire [ 20-1:0] m_ctrlport_req_addr, output wire [ 19:0] m_ctrlport_req_addr,
output wire [ 32-1:0] m_ctrlport_req_data, output wire [ 31:0] m_ctrlport_req_data,
output wire [ 4-1:0] m_ctrlport_req_byte_en, output wire [ 3:0] m_ctrlport_req_byte_en,
output wire [ 1-1:0] m_ctrlport_req_has_time, output wire [ 0:0] m_ctrlport_req_has_time,
output wire [ 64-1:0] m_ctrlport_req_time, output wire [ 63:0] m_ctrlport_req_time,
input wire [ 1-1:0] m_ctrlport_resp_ack, input wire [ 0:0] m_ctrlport_resp_ack,
input wire [ 2-1:0] m_ctrlport_resp_status, input wire [ 1:0] m_ctrlport_resp_status,
input wire [ 32-1:0] m_ctrlport_resp_data, input wire [ 31:0] m_ctrlport_resp_data,
// time_keeper // time_keeper
input wire [ 64-1:0] radio_time, input wire [ 63:0] radio_time,
// x300_radio // x300_radio
input wire [ 64-1:0] radio_rx_data, input wire [ 63:0] radio_rx_data,
input wire [ 2-1:0] radio_rx_stb, input wire [ 1:0] radio_rx_stb,
output wire [ 2-1:0] radio_rx_running, output wire [ 1:0] radio_rx_running,
output wire [ 64-1:0] radio_tx_data, output wire [ 63:0] radio_tx_data,
input wire [ 2-1:0] radio_tx_stb, input wire [ 1:0] radio_tx_stb,
output wire [ 2-1:0] radio_tx_running, output wire [ 1:0] radio_tx_running,
// Transport 0 (dma dma)
input wire [64-1:0] s_dma_tdata, // Transport Adapters ///////////////
// Transport 0 (dma)
input wire [CHDR_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [64-1:0] m_dma_tdata, output wire [CHDR_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam CHDR_W = 64;
localparam MTU = 10;
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// CHDR Crossbar // CHDR Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
@@ -109,9 +127,18 @@ module rfnoc_image_core #(
.ext_rtcfg_ack () .ext_rtcfg_ack ()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Stream Endpoints // Stream Endpoints
// ---------------------------------------------------- //---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 16384;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
@@ -135,7 +162,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
@@ -174,6 +201,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 16384;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
@@ -196,7 +231,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
@@ -236,10 +271,9 @@ module rfnoc_image_core #(
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Control Crossbar // Control Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast; wire m_core_ctrl_tlast, s_core_ctrl_tlast;
@@ -272,9 +306,11 @@ module rfnoc_image_core #(
.deadlock_detected() .deadlock_detected()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// RFNoC Core Kernel // RFNoC Core Kernel
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [(512*1)-1:0] rfnoc_core_config, rfnoc_core_status; wire [(512*1)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #( rfnoc_core_kernel #(
@@ -312,13 +348,15 @@ module rfnoc_image_core #(
.rfnoc_core_status (rfnoc_core_status) .rfnoc_core_status (rfnoc_core_status)
); );
// ----------------------------------------------------
// Blocks
// ----------------------------------------------------
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// radio0 // radio0
// ---------------------------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
@@ -330,25 +368,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 1-1:0] radio0_m_ctrlport_req_rd; wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 20-1:0] radio0_m_ctrlport_req_addr; wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 32-1:0] radio0_m_ctrlport_req_data; wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio0_m_ctrlport_req_has_time; wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 64-1:0] radio0_m_ctrlport_req_time; wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 1-1:0] radio0_m_ctrlport_resp_ack; wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 2-1:0] radio0_m_ctrlport_resp_status; wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 32-1:0] radio0_m_ctrlport_resp_data; wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio0_radio_time; wire [ 63:0] radio0_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio0_radio_rx_data; wire [ 63:0] radio0_radio_rx_data;
wire [ 2-1:0] radio0_radio_rx_stb; wire [ 1:0] radio0_radio_rx_stb;
wire [ 2-1:0] radio0_radio_rx_running; wire [ 1:0] radio0_radio_rx_running;
wire [ 64-1:0] radio0_radio_tx_data; wire [ 63:0] radio0_radio_tx_data;
wire [ 2-1:0] radio0_radio_tx_stb; wire [ 1:0] radio0_radio_tx_stb;
wire [ 2-1:0] radio0_radio_tx_running; wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (2), .THIS_PORTID (2),
@@ -361,7 +399,6 @@ module rfnoc_image_core #(
.radio_clk (radio0_radio_clk), .radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
@@ -379,7 +416,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio0_radio_tx_data), .radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb), .radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running), .radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
@@ -398,10 +434,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Static Router // Static Router
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_radio0_in_0_tdata = m_ep0_out0_tdata; assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
assign s_radio0_in_0_tlast = m_ep0_out0_tlast; assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
@@ -423,19 +459,23 @@ module rfnoc_image_core #(
assign m_radio0_out_1_tready = s_ep1_in0_tready; assign m_radio0_out_1_tready = s_ep1_in0_tready;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Unused Ports // Unused Ports
// ---------------------------------------------------- //---------------------------------------------------------------------------
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains // Clock Domains
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk; assign radio0_radio_clk = radio_clk;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// IO Port Connection // IO Port Connection
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Master/Slave Connections: // Master/Slave Connections:
assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd; assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd;
@@ -459,3 +499,6 @@ module rfnoc_image_core #(
assign radio0_radio_time = radio_time; assign radio0_radio_time = radio_time;
endmodule endmodule
`default_nettype wire
top/e31x/e310_rfnoc_image_core.vh
+21
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@@ -0,0 +1,21 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for e31x)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:11.441866
// Source: e310_rfnoc_image_core.yml
// Source SHA256: 7fef622f1ae280dd7573abd823c7a6bbecf51921a74cea948e6bfb9f8f65e2cc
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/e31x/e310_rfnoc_image_core.yml
+2 -1
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@@ -6,7 +6,8 @@ license: 'SPDX-License-Identifier: LGPL-3.0-or-later' # License information used
version: '1.0' # File version version: '1.0' # File version
rfnoc_version: '1.0' # RFNoC protocol version rfnoc_version: '1.0' # RFNoC protocol version
chdr_width: 64 # Bit width of the CHDR bus for this image chdr_width: 64 # Bit width of the CHDR bus for this image
device: 'e310' device: 'e310' # USRP type
image_core_name: 'e310' # Name to use for the RFNoC Image Core files
default_target: 'E310_SG3' default_target: 'E310_SG3'
# A list of all stream endpoints in design # A list of all stream endpoints in design
top/e320/e320_rfnoc_image_core.v
+237 -186
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@@ -1,18 +1,31 @@
// //
// Copyright 2019 Ettus Research, A National Instruments Brand // Copyright 2021 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: rfnoc_image_core (for e320) // Module: rfnoc_image_core (for e320)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) //
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// File generated on: 2019-11-08T15:58:14.818480 //
// Source: ./e320/e320_rfnoc_image_core.yml // File generated on: 2021-05-03T08:51:10.699215
// Source SHA256: a2a7b213b5764ef6cb83fed9d744a415bf8a7f18a955fbe1f867590f5d8c5142 // Source: e320_rfnoc_image_core.yml
// Source SHA256: 8b38ab7ba86e214c213ab62a63b698739c0858fdf10fcc5b737f87a56fb04454
//
`default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0} parameter CHDR_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) ( ) (
// Clocks // Clocks
input wire chdr_aclk, input wire chdr_aclk,
@@ -22,103 +35,108 @@ module rfnoc_image_core #(
input wire dram_clk, input wire dram_clk,
// Basic // Basic
input wire [ 15:0] device_id, input wire [ 15:0] device_id,
//// IO ports //////////////////////////////////
// IO ports /////////////////////////
// ctrl_port // ctrl_port
output wire [ 1-1:0] m_ctrlport_req_wr, output wire [ 0:0] m_ctrlport_req_wr,
output wire [ 1-1:0] m_ctrlport_req_rd, output wire [ 0:0] m_ctrlport_req_rd,
output wire [ 20-1:0] m_ctrlport_req_addr, output wire [ 19:0] m_ctrlport_req_addr,
output wire [ 32-1:0] m_ctrlport_req_data, output wire [ 31:0] m_ctrlport_req_data,
output wire [ 4-1:0] m_ctrlport_req_byte_en, output wire [ 3:0] m_ctrlport_req_byte_en,
output wire [ 1-1:0] m_ctrlport_req_has_time, output wire [ 0:0] m_ctrlport_req_has_time,
output wire [ 64-1:0] m_ctrlport_req_time, output wire [ 63:0] m_ctrlport_req_time,
input wire [ 1-1:0] m_ctrlport_resp_ack, input wire [ 0:0] m_ctrlport_resp_ack,
input wire [ 2-1:0] m_ctrlport_resp_status, input wire [ 1:0] m_ctrlport_resp_status,
input wire [ 32-1:0] m_ctrlport_resp_data, input wire [ 31:0] m_ctrlport_resp_data,
// time_keeper // time_keeper
input wire [ 64-1:0] radio_time, input wire [ 63:0] radio_time,
// x300_radio // x300_radio
input wire [ 64-1:0] radio_rx_data, input wire [ 63:0] radio_rx_data,
input wire [ 2-1:0] radio_rx_stb, input wire [ 1:0] radio_rx_stb,
output wire [ 2-1:0] radio_rx_running, output wire [ 1:0] radio_rx_running,
output wire [ 64-1:0] radio_tx_data, output wire [ 63:0] radio_tx_data,
input wire [ 2-1:0] radio_tx_stb, input wire [ 1:0] radio_tx_stb,
output wire [ 2-1:0] radio_tx_running, output wire [ 1:0] radio_tx_running,
// dram // dram
input wire [ 1-1:0] axi_rst, input wire [ 0:0] axi_rst,
output wire [ 2-1:0] m_axi_awid, output wire [ 3:0] m_axi_awid,
output wire [ 64-1:0] m_axi_awaddr, output wire [ 127:0] m_axi_awaddr,
output wire [ 16-1:0] m_axi_awlen, output wire [ 31:0] m_axi_awlen,
output wire [ 6-1:0] m_axi_awsize, output wire [ 11:0] m_axi_awsize,
output wire [ 4-1:0] m_axi_awburst, output wire [ 7:0] m_axi_awburst,
output wire [ 2-1:0] m_axi_awlock, output wire [ 3:0] m_axi_awlock,
output wire [ 8-1:0] m_axi_awcache, output wire [ 15:0] m_axi_awcache,
output wire [ 6-1:0] m_axi_awprot, output wire [ 11:0] m_axi_awprot,
output wire [ 8-1:0] m_axi_awqos, output wire [ 15:0] m_axi_awqos,
output wire [ 8-1:0] m_axi_awregion, output wire [ 15:0] m_axi_awregion,
output wire [ 2-1:0] m_axi_awuser, output wire [ 3:0] m_axi_awuser,
output wire [ 2-1:0] m_axi_awvalid, output wire [ 3:0] m_axi_awvalid,
input wire [ 2-1:0] m_axi_awready, input wire [ 3:0] m_axi_awready,
output wire [128-1:0] m_axi_wdata, output wire [ 255:0] m_axi_wdata,
output wire [ 16-1:0] m_axi_wstrb, output wire [ 31:0] m_axi_wstrb,
output wire [ 2-1:0] m_axi_wlast, output wire [ 3:0] m_axi_wlast,
output wire [ 2-1:0] m_axi_wuser, output wire [ 3:0] m_axi_wuser,
output wire [ 2-1:0] m_axi_wvalid, output wire [ 3:0] m_axi_wvalid,
input wire [ 2-1:0] m_axi_wready, input wire [ 3:0] m_axi_wready,
input wire [ 2-1:0] m_axi_bid, input wire [ 3:0] m_axi_bid,
input wire [ 4-1:0] m_axi_bresp, input wire [ 7:0] m_axi_bresp,
input wire [ 2-1:0] m_axi_buser, input wire [ 3:0] m_axi_buser,
input wire [ 2-1:0] m_axi_bvalid, input wire [ 3:0] m_axi_bvalid,
output wire [ 2-1:0] m_axi_bready, output wire [ 3:0] m_axi_bready,
output wire [ 2-1:0] m_axi_arid, output wire [ 3:0] m_axi_arid,
output wire [ 64-1:0] m_axi_araddr, output wire [ 127:0] m_axi_araddr,
output wire [ 16-1:0] m_axi_arlen, output wire [ 31:0] m_axi_arlen,
output wire [ 6-1:0] m_axi_arsize, output wire [ 11:0] m_axi_arsize,
output wire [ 4-1:0] m_axi_arburst, output wire [ 7:0] m_axi_arburst,
output wire [ 2-1:0] m_axi_arlock, output wire [ 3:0] m_axi_arlock,
output wire [ 8-1:0] m_axi_arcache, output wire [ 15:0] m_axi_arcache,
output wire [ 6-1:0] m_axi_arprot, output wire [ 11:0] m_axi_arprot,
output wire [ 8-1:0] m_axi_arqos, output wire [ 15:0] m_axi_arqos,
output wire [ 8-1:0] m_axi_arregion, output wire [ 15:0] m_axi_arregion,
output wire [ 2-1:0] m_axi_aruser, output wire [ 3:0] m_axi_aruser,
output wire [ 2-1:0] m_axi_arvalid, output wire [ 3:0] m_axi_arvalid,
input wire [ 2-1:0] m_axi_arready, input wire [ 3:0] m_axi_arready,
input wire [ 2-1:0] m_axi_rid, input wire [ 3:0] m_axi_rid,
input wire [128-1:0] m_axi_rdata, input wire [ 255:0] m_axi_rdata,
input wire [ 4-1:0] m_axi_rresp, input wire [ 7:0] m_axi_rresp,
input wire [ 2-1:0] m_axi_rlast, input wire [ 3:0] m_axi_rlast,
input wire [ 2-1:0] m_axi_ruser, input wire [ 3:0] m_axi_ruser,
input wire [ 2-1:0] m_axi_rvalid, input wire [ 3:0] m_axi_rvalid,
output wire [ 2-1:0] m_axi_rready, output wire [ 3:0] m_axi_rready,
// Transport 0 (eth 10G)
input wire [64-1:0] s_eth_tdata, // Transport Adapters ///////////////
// Transport 0 (eth)
input wire [CHDR_W-1:0] s_eth_tdata,
input wire s_eth_tlast, input wire s_eth_tlast,
input wire s_eth_tvalid, input wire s_eth_tvalid,
output wire s_eth_tready, output wire s_eth_tready,
output wire [64-1:0] m_eth_tdata, output wire [CHDR_W-1:0] m_eth_tdata,
output wire m_eth_tlast, output wire m_eth_tlast,
output wire m_eth_tvalid, output wire m_eth_tvalid,
input wire m_eth_tready, input wire m_eth_tready,
// Transport 1 (dma dma) // Transport 1 (dma)
input wire [64-1:0] s_dma_tdata, input wire [CHDR_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [64-1:0] m_dma_tdata, output wire [CHDR_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam CHDR_W = 64;
localparam MTU = 10;
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// CHDR Crossbar // CHDR Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
@@ -181,9 +199,18 @@ module rfnoc_image_core #(
.ext_rtcfg_ack () .ext_rtcfg_ack ()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Stream Endpoints // Stream Endpoints
// ---------------------------------------------------- //---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
@@ -207,7 +234,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
@@ -246,6 +273,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 32768;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
@@ -268,7 +303,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
@@ -307,6 +342,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 8192;
localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
@@ -329,7 +372,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (13), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
@@ -368,6 +411,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 8192;
localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
@@ -390,7 +441,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (13), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
@@ -430,10 +481,9 @@ module rfnoc_image_core #(
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Control Crossbar // Control Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast; wire m_core_ctrl_tlast, s_core_ctrl_tlast;
@@ -478,9 +528,11 @@ module rfnoc_image_core #(
.deadlock_detected() .deadlock_detected()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// RFNoC Core Kernel // RFNoC Core Kernel
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [(512*4)-1:0] rfnoc_core_config, rfnoc_core_status; wire [(512*4)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #( rfnoc_core_kernel #(
@@ -518,13 +570,15 @@ module rfnoc_image_core #(
.rfnoc_core_status (rfnoc_core_status) .rfnoc_core_status (rfnoc_core_status)
); );
// ----------------------------------------------------
// Blocks
// ----------------------------------------------------
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// duc0 // duc0
// ---------------------------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ;
wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ;
@@ -535,7 +589,6 @@ module rfnoc_image_core #(
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
wire m_duc0_out_1_tready, m_duc0_out_0_tready; wire m_duc0_out_1_tready, m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -549,8 +602,6 @@ module rfnoc_image_core #(
.ce_clk (duc0_ce_clk), .ce_clk (duc0_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}),
@@ -569,10 +620,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready) .m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// ddc0 // ddc0
// ---------------------------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
@@ -583,7 +634,6 @@ module rfnoc_image_core #(
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -597,8 +647,6 @@ module rfnoc_image_core #(
.ce_clk (ddc0_ce_clk), .ce_clk (ddc0_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
.s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}),
@@ -617,10 +665,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready) .m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// radio0 // radio0
// ---------------------------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
@@ -632,25 +680,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 1-1:0] radio0_m_ctrlport_req_rd; wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 20-1:0] radio0_m_ctrlport_req_addr; wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 32-1:0] radio0_m_ctrlport_req_data; wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio0_m_ctrlport_req_has_time; wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 64-1:0] radio0_m_ctrlport_req_time; wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 1-1:0] radio0_m_ctrlport_resp_ack; wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 2-1:0] radio0_m_ctrlport_resp_status; wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 32-1:0] radio0_m_ctrlport_resp_data; wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio0_radio_time; wire [ 63:0] radio0_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio0_radio_rx_data; wire [ 63:0] radio0_radio_rx_data;
wire [ 2-1:0] radio0_radio_rx_stb; wire [ 1:0] radio0_radio_rx_stb;
wire [ 2-1:0] radio0_radio_rx_running; wire [ 1:0] radio0_radio_rx_running;
wire [ 64-1:0] radio0_radio_tx_data; wire [ 63:0] radio0_radio_tx_data;
wire [ 2-1:0] radio0_radio_tx_stb; wire [ 1:0] radio0_radio_tx_stb;
wire [ 2-1:0] radio0_radio_tx_running; wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
@@ -663,7 +711,6 @@ module rfnoc_image_core #(
.radio_clk (radio0_radio_clk), .radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]),
.rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
@@ -681,7 +728,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio0_radio_tx_data), .radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb), .radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running), .radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
@@ -700,10 +746,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// fifo0 // fifo0
// ---------------------------------------------------- //-----------------------------------
wire fifo0_mem_clk; wire fifo0_mem_clk;
wire [CHDR_W-1:0] s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; wire [CHDR_W-1:0] s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
wire s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; wire s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
@@ -715,51 +761,51 @@ module rfnoc_image_core #(
wire m_fifo0_out_1_tready, m_fifo0_out_0_tready; wire m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram // axi_ram
wire [ 1-1:0] fifo0_axi_rst; wire [ 0:0] fifo0_axi_rst;
wire [ 2-1:0] fifo0_m_axi_awid; wire [ 3:0] fifo0_m_axi_awid;
wire [ 64-1:0] fifo0_m_axi_awaddr; wire [ 127:0] fifo0_m_axi_awaddr;
wire [ 16-1:0] fifo0_m_axi_awlen; wire [ 31:0] fifo0_m_axi_awlen;
wire [ 6-1:0] fifo0_m_axi_awsize; wire [ 11:0] fifo0_m_axi_awsize;
wire [ 4-1:0] fifo0_m_axi_awburst; wire [ 7:0] fifo0_m_axi_awburst;
wire [ 2-1:0] fifo0_m_axi_awlock; wire [ 3:0] fifo0_m_axi_awlock;
wire [ 8-1:0] fifo0_m_axi_awcache; wire [ 15:0] fifo0_m_axi_awcache;
wire [ 6-1:0] fifo0_m_axi_awprot; wire [ 11:0] fifo0_m_axi_awprot;
wire [ 8-1:0] fifo0_m_axi_awqos; wire [ 15:0] fifo0_m_axi_awqos;
wire [ 8-1:0] fifo0_m_axi_awregion; wire [ 15:0] fifo0_m_axi_awregion;
wire [ 2-1:0] fifo0_m_axi_awuser; wire [ 3:0] fifo0_m_axi_awuser;
wire [ 2-1:0] fifo0_m_axi_awvalid; wire [ 3:0] fifo0_m_axi_awvalid;
wire [ 2-1:0] fifo0_m_axi_awready; wire [ 3:0] fifo0_m_axi_awready;
wire [128-1:0] fifo0_m_axi_wdata; wire [ 255:0] fifo0_m_axi_wdata;
wire [ 16-1:0] fifo0_m_axi_wstrb; wire [ 31:0] fifo0_m_axi_wstrb;
wire [ 2-1:0] fifo0_m_axi_wlast; wire [ 3:0] fifo0_m_axi_wlast;
wire [ 2-1:0] fifo0_m_axi_wuser; wire [ 3:0] fifo0_m_axi_wuser;
wire [ 2-1:0] fifo0_m_axi_wvalid; wire [ 3:0] fifo0_m_axi_wvalid;
wire [ 2-1:0] fifo0_m_axi_wready; wire [ 3:0] fifo0_m_axi_wready;
wire [ 2-1:0] fifo0_m_axi_bid; wire [ 3:0] fifo0_m_axi_bid;
wire [ 4-1:0] fifo0_m_axi_bresp; wire [ 7:0] fifo0_m_axi_bresp;
wire [ 2-1:0] fifo0_m_axi_buser; wire [ 3:0] fifo0_m_axi_buser;
wire [ 2-1:0] fifo0_m_axi_bvalid; wire [ 3:0] fifo0_m_axi_bvalid;
wire [ 2-1:0] fifo0_m_axi_bready; wire [ 3:0] fifo0_m_axi_bready;
wire [ 2-1:0] fifo0_m_axi_arid; wire [ 3:0] fifo0_m_axi_arid;
wire [ 64-1:0] fifo0_m_axi_araddr; wire [ 127:0] fifo0_m_axi_araddr;
wire [ 16-1:0] fifo0_m_axi_arlen; wire [ 31:0] fifo0_m_axi_arlen;
wire [ 6-1:0] fifo0_m_axi_arsize; wire [ 11:0] fifo0_m_axi_arsize;
wire [ 4-1:0] fifo0_m_axi_arburst; wire [ 7:0] fifo0_m_axi_arburst;
wire [ 2-1:0] fifo0_m_axi_arlock; wire [ 3:0] fifo0_m_axi_arlock;
wire [ 8-1:0] fifo0_m_axi_arcache; wire [ 15:0] fifo0_m_axi_arcache;
wire [ 6-1:0] fifo0_m_axi_arprot; wire [ 11:0] fifo0_m_axi_arprot;
wire [ 8-1:0] fifo0_m_axi_arqos; wire [ 15:0] fifo0_m_axi_arqos;
wire [ 8-1:0] fifo0_m_axi_arregion; wire [ 15:0] fifo0_m_axi_arregion;
wire [ 2-1:0] fifo0_m_axi_aruser; wire [ 3:0] fifo0_m_axi_aruser;
wire [ 2-1:0] fifo0_m_axi_arvalid; wire [ 3:0] fifo0_m_axi_arvalid;
wire [ 2-1:0] fifo0_m_axi_arready; wire [ 3:0] fifo0_m_axi_arready;
wire [ 2-1:0] fifo0_m_axi_rid; wire [ 3:0] fifo0_m_axi_rid;
wire [128-1:0] fifo0_m_axi_rdata; wire [ 255:0] fifo0_m_axi_rdata;
wire [ 4-1:0] fifo0_m_axi_rresp; wire [ 7:0] fifo0_m_axi_rresp;
wire [ 2-1:0] fifo0_m_axi_rlast; wire [ 3:0] fifo0_m_axi_rlast;
wire [ 2-1:0] fifo0_m_axi_ruser; wire [ 3:0] fifo0_m_axi_ruser;
wire [ 2-1:0] fifo0_m_axi_rvalid; wire [ 3:0] fifo0_m_axi_rvalid;
wire [ 2-1:0] fifo0_m_axi_rready; wire [ 3:0] fifo0_m_axi_rready;
rfnoc_block_axi_ram_fifo #( rfnoc_block_axi_ram_fifo #(
.THIS_PORTID (5), .THIS_PORTID (5),
@@ -777,7 +823,6 @@ module rfnoc_image_core #(
.mem_clk (fifo0_mem_clk), .mem_clk (fifo0_mem_clk),
.rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]),
.rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]),
.axi_rst (fifo0_axi_rst), .axi_rst (fifo0_axi_rst),
.m_axi_awid (fifo0_m_axi_awid), .m_axi_awid (fifo0_m_axi_awid),
.m_axi_awaddr (fifo0_m_axi_awaddr), .m_axi_awaddr (fifo0_m_axi_awaddr),
@@ -823,7 +868,6 @@ module rfnoc_image_core #(
.m_axi_ruser (fifo0_m_axi_ruser), .m_axi_ruser (fifo0_m_axi_ruser),
.m_axi_rvalid (fifo0_m_axi_rvalid), .m_axi_rvalid (fifo0_m_axi_rvalid),
.m_axi_rready (fifo0_m_axi_rready), .m_axi_rready (fifo0_m_axi_rready),
.s_rfnoc_chdr_tdata ({s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}),
@@ -842,10 +886,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready) .m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Static Router // Static Router
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_duc0_in_0_tdata = m_ep0_out0_tdata; assign s_duc0_in_0_tdata = m_ep0_out0_tdata;
assign s_duc0_in_0_tlast = m_ep0_out0_tlast; assign s_duc0_in_0_tlast = m_ep0_out0_tlast;
assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid;
@@ -907,22 +951,26 @@ module rfnoc_image_core #(
assign m_fifo0_out_1_tready = s_ep3_in0_tready; assign m_fifo0_out_1_tready = s_ep3_in0_tready;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Unused Ports // Unused Ports
// ---------------------------------------------------- //---------------------------------------------------------------------------
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains // Clock Domains
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk; assign radio0_radio_clk = radio_clk;
assign duc0_ce_clk = rfnoc_chdr_clk; assign duc0_ce_clk = rfnoc_chdr_clk;
assign ddc0_ce_clk = rfnoc_chdr_clk; assign ddc0_ce_clk = rfnoc_chdr_clk;
assign fifo0_mem_clk = dram_clk; assign fifo0_mem_clk = dram_clk;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// IO Port Connection // IO Port Connection
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Master/Slave Connections: // Master/Slave Connections:
assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd; assign m_ctrlport_req_rd = radio0_m_ctrlport_req_rd;
@@ -992,3 +1040,6 @@ module rfnoc_image_core #(
assign radio0_radio_time = radio_time; assign radio0_radio_time = radio_time;
endmodule endmodule
`default_nettype wire
top/e320/e320_rfnoc_image_core.vh
+21
View File
@@ -0,0 +1,21 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for e320)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:10.746455
// Source: e320_rfnoc_image_core.yml
// Source SHA256: 8b38ab7ba86e214c213ab62a63b698739c0858fdf10fcc5b737f87a56fb04454
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n300_bist_image_core.v
+234 -177
View File
@@ -1,18 +1,31 @@
// //
// Copyright 2019 Ettus Research, A National Instruments Brand // Copyright 2021 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: rfnoc_image_core (for n300) // Module: rfnoc_image_core (for n300)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) //
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// File generated on: 2019-11-08T15:58:13.938765 //
// Source: ./n3xx/n300_bist_image_core.yml // File generated on: 2021-05-03T08:51:04.740210
// Source SHA256: 3bed6bab7b614594eb5ea4e49b34a6e9560b10ff4622c1033c206bec1f4a0f2c // Source: n300_bist_image_core.yml
// Source SHA256: 209edc7c95f0a9fd8b96b6d10a40849f3ee84e5fc85a37696cc7510cd74c4af6
//
`default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0} parameter CHDR_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) ( ) (
// Clocks // Clocks
input wire chdr_aclk, input wire chdr_aclk,
@@ -22,112 +35,117 @@ module rfnoc_image_core #(
input wire dram_clk, input wire dram_clk,
// Basic // Basic
input wire [ 15:0] device_id, input wire [ 15:0] device_id,
//// IO ports //////////////////////////////////
// IO ports /////////////////////////
// ctrlport_radio0 // ctrlport_radio0
output wire [ 1-1:0] m_ctrlport_radio0_req_wr, output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 1-1:0] m_ctrlport_radio0_req_rd, output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire [ 20-1:0] m_ctrlport_radio0_req_addr, output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 32-1:0] m_ctrlport_radio0_req_data, output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio0_req_time, output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio0_resp_status, input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 32-1:0] m_ctrlport_radio0_resp_data, input wire [ 31:0] m_ctrlport_radio0_resp_data,
// time_keeper // time_keeper
input wire [ 64-1:0] radio_time, input wire [ 63:0] radio_time,
// x300_radio0 // x300_radio0
input wire [ 64-1:0] radio_rx_data_radio0, input wire [ 63:0] radio_rx_data_radio0,
input wire [ 2-1:0] radio_rx_stb_radio0, input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 2-1:0] radio_rx_running_radio0, output wire [ 1:0] radio_rx_running_radio0,
output wire [ 64-1:0] radio_tx_data_radio0, output wire [ 63:0] radio_tx_data_radio0,
input wire [ 2-1:0] radio_tx_stb_radio0, input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 2-1:0] radio_tx_running_radio0, output wire [ 1:0] radio_tx_running_radio0,
// dram // dram
input wire [ 1-1:0] axi_rst, input wire [ 0:0] axi_rst,
output wire [ 4-1:0] m_axi_awid, output wire [ 3:0] m_axi_awid,
output wire [128-1:0] m_axi_awaddr, output wire [ 127:0] m_axi_awaddr,
output wire [ 32-1:0] m_axi_awlen, output wire [ 31:0] m_axi_awlen,
output wire [ 12-1:0] m_axi_awsize, output wire [ 11:0] m_axi_awsize,
output wire [ 8-1:0] m_axi_awburst, output wire [ 7:0] m_axi_awburst,
output wire [ 4-1:0] m_axi_awlock, output wire [ 3:0] m_axi_awlock,
output wire [ 16-1:0] m_axi_awcache, output wire [ 15:0] m_axi_awcache,
output wire [ 12-1:0] m_axi_awprot, output wire [ 11:0] m_axi_awprot,
output wire [ 16-1:0] m_axi_awqos, output wire [ 15:0] m_axi_awqos,
output wire [ 16-1:0] m_axi_awregion, output wire [ 15:0] m_axi_awregion,
output wire [ 4-1:0] m_axi_awuser, output wire [ 3:0] m_axi_awuser,
output wire [ 4-1:0] m_axi_awvalid, output wire [ 3:0] m_axi_awvalid,
input wire [ 4-1:0] m_axi_awready, input wire [ 3:0] m_axi_awready,
output wire [256-1:0] m_axi_wdata, output wire [ 255:0] m_axi_wdata,
output wire [ 32-1:0] m_axi_wstrb, output wire [ 31:0] m_axi_wstrb,
output wire [ 4-1:0] m_axi_wlast, output wire [ 3:0] m_axi_wlast,
output wire [ 4-1:0] m_axi_wuser, output wire [ 3:0] m_axi_wuser,
output wire [ 4-1:0] m_axi_wvalid, output wire [ 3:0] m_axi_wvalid,
input wire [ 4-1:0] m_axi_wready, input wire [ 3:0] m_axi_wready,
input wire [ 4-1:0] m_axi_bid, input wire [ 3:0] m_axi_bid,
input wire [ 8-1:0] m_axi_bresp, input wire [ 7:0] m_axi_bresp,
input wire [ 4-1:0] m_axi_buser, input wire [ 3:0] m_axi_buser,
input wire [ 4-1:0] m_axi_bvalid, input wire [ 3:0] m_axi_bvalid,
output wire [ 4-1:0] m_axi_bready, output wire [ 3:0] m_axi_bready,
output wire [ 4-1:0] m_axi_arid, output wire [ 3:0] m_axi_arid,
output wire [128-1:0] m_axi_araddr, output wire [ 127:0] m_axi_araddr,
output wire [ 32-1:0] m_axi_arlen, output wire [ 31:0] m_axi_arlen,
output wire [ 12-1:0] m_axi_arsize, output wire [ 11:0] m_axi_arsize,
output wire [ 8-1:0] m_axi_arburst, output wire [ 7:0] m_axi_arburst,
output wire [ 4-1:0] m_axi_arlock, output wire [ 3:0] m_axi_arlock,
output wire [ 16-1:0] m_axi_arcache, output wire [ 15:0] m_axi_arcache,
output wire [ 12-1:0] m_axi_arprot, output wire [ 11:0] m_axi_arprot,
output wire [ 16-1:0] m_axi_arqos, output wire [ 15:0] m_axi_arqos,
output wire [ 16-1:0] m_axi_arregion, output wire [ 15:0] m_axi_arregion,
output wire [ 4-1:0] m_axi_aruser, output wire [ 3:0] m_axi_aruser,
output wire [ 4-1:0] m_axi_arvalid, output wire [ 3:0] m_axi_arvalid,
input wire [ 4-1:0] m_axi_arready, input wire [ 3:0] m_axi_arready,
input wire [ 4-1:0] m_axi_rid, input wire [ 3:0] m_axi_rid,
input wire [256-1:0] m_axi_rdata, input wire [ 255:0] m_axi_rdata,
input wire [ 8-1:0] m_axi_rresp, input wire [ 7:0] m_axi_rresp,
input wire [ 4-1:0] m_axi_rlast, input wire [ 3:0] m_axi_rlast,
input wire [ 4-1:0] m_axi_ruser, input wire [ 3:0] m_axi_ruser,
input wire [ 4-1:0] m_axi_rvalid, input wire [ 3:0] m_axi_rvalid,
output wire [ 4-1:0] m_axi_rready, output wire [ 3:0] m_axi_rready,
// Transport 0 (eth0 1G)
input wire [64-1:0] s_eth0_tdata, // Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [64-1:0] m_eth0_tdata, output wire [CHDR_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1 10G) // Transport 1 (eth1)
input wire [64-1:0] s_eth1_tdata, input wire [CHDR_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [64-1:0] m_eth1_tdata, output wire [CHDR_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (dma dma) // Transport 2 (dma)
input wire [64-1:0] s_dma_tdata, input wire [CHDR_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [64-1:0] m_dma_tdata, output wire [CHDR_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam CHDR_W = 64;
localparam MTU = 10;
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// CHDR Crossbar // CHDR Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
@@ -190,9 +208,18 @@ module rfnoc_image_core #(
.ext_rtcfg_ack () .ext_rtcfg_ack ()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Stream Endpoints // Stream Endpoints
// ---------------------------------------------------- //---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 16384;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
@@ -216,7 +243,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
@@ -255,6 +282,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 16384;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
@@ -277,7 +312,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
@@ -316,6 +351,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 16384;
localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
@@ -338,7 +381,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
@@ -377,6 +420,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 16384;
localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
@@ -399,7 +450,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
@@ -439,10 +490,9 @@ module rfnoc_image_core #(
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Control Crossbar // Control Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast; wire m_core_ctrl_tlast, s_core_ctrl_tlast;
@@ -479,9 +529,11 @@ module rfnoc_image_core #(
.deadlock_detected() .deadlock_detected()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// RFNoC Core Kernel // RFNoC Core Kernel
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [(512*2)-1:0] rfnoc_core_config, rfnoc_core_status; wire [(512*2)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #( rfnoc_core_kernel #(
@@ -519,13 +571,15 @@ module rfnoc_image_core #(
.rfnoc_core_status (rfnoc_core_status) .rfnoc_core_status (rfnoc_core_status)
); );
// ----------------------------------------------------
// Blocks
// ----------------------------------------------------
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// radio0 // radio0
// ---------------------------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
@@ -537,25 +591,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 1-1:0] radio0_m_ctrlport_req_rd; wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 20-1:0] radio0_m_ctrlport_req_addr; wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 32-1:0] radio0_m_ctrlport_req_data; wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio0_m_ctrlport_req_has_time; wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 64-1:0] radio0_m_ctrlport_req_time; wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 1-1:0] radio0_m_ctrlport_resp_ack; wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 2-1:0] radio0_m_ctrlport_resp_status; wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 32-1:0] radio0_m_ctrlport_resp_data; wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio0_radio_time; wire [ 63:0] radio0_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio0_radio_rx_data; wire [ 63:0] radio0_radio_rx_data;
wire [ 2-1:0] radio0_radio_rx_stb; wire [ 1:0] radio0_radio_rx_stb;
wire [ 2-1:0] radio0_radio_rx_running; wire [ 1:0] radio0_radio_rx_running;
wire [ 64-1:0] radio0_radio_tx_data; wire [ 63:0] radio0_radio_tx_data;
wire [ 2-1:0] radio0_radio_tx_stb; wire [ 1:0] radio0_radio_tx_stb;
wire [ 2-1:0] radio0_radio_tx_running; wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (2), .THIS_PORTID (2),
@@ -568,7 +622,6 @@ module rfnoc_image_core #(
.radio_clk (radio0_radio_clk), .radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
@@ -586,7 +639,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio0_radio_tx_data), .radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb), .radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running), .radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
@@ -605,10 +657,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// fifo0 // fifo0
// ---------------------------------------------------- //-----------------------------------
wire fifo0_mem_clk; wire fifo0_mem_clk;
wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
@@ -620,51 +672,51 @@ module rfnoc_image_core #(
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram // axi_ram
wire [ 1-1:0] fifo0_axi_rst; wire [ 0:0] fifo0_axi_rst;
wire [ 4-1:0] fifo0_m_axi_awid; wire [ 3:0] fifo0_m_axi_awid;
wire [128-1:0] fifo0_m_axi_awaddr; wire [ 127:0] fifo0_m_axi_awaddr;
wire [ 32-1:0] fifo0_m_axi_awlen; wire [ 31:0] fifo0_m_axi_awlen;
wire [ 12-1:0] fifo0_m_axi_awsize; wire [ 11:0] fifo0_m_axi_awsize;
wire [ 8-1:0] fifo0_m_axi_awburst; wire [ 7:0] fifo0_m_axi_awburst;
wire [ 4-1:0] fifo0_m_axi_awlock; wire [ 3:0] fifo0_m_axi_awlock;
wire [ 16-1:0] fifo0_m_axi_awcache; wire [ 15:0] fifo0_m_axi_awcache;
wire [ 12-1:0] fifo0_m_axi_awprot; wire [ 11:0] fifo0_m_axi_awprot;
wire [ 16-1:0] fifo0_m_axi_awqos; wire [ 15:0] fifo0_m_axi_awqos;
wire [ 16-1:0] fifo0_m_axi_awregion; wire [ 15:0] fifo0_m_axi_awregion;
wire [ 4-1:0] fifo0_m_axi_awuser; wire [ 3:0] fifo0_m_axi_awuser;
wire [ 4-1:0] fifo0_m_axi_awvalid; wire [ 3:0] fifo0_m_axi_awvalid;
wire [ 4-1:0] fifo0_m_axi_awready; wire [ 3:0] fifo0_m_axi_awready;
wire [256-1:0] fifo0_m_axi_wdata; wire [ 255:0] fifo0_m_axi_wdata;
wire [ 32-1:0] fifo0_m_axi_wstrb; wire [ 31:0] fifo0_m_axi_wstrb;
wire [ 4-1:0] fifo0_m_axi_wlast; wire [ 3:0] fifo0_m_axi_wlast;
wire [ 4-1:0] fifo0_m_axi_wuser; wire [ 3:0] fifo0_m_axi_wuser;
wire [ 4-1:0] fifo0_m_axi_wvalid; wire [ 3:0] fifo0_m_axi_wvalid;
wire [ 4-1:0] fifo0_m_axi_wready; wire [ 3:0] fifo0_m_axi_wready;
wire [ 4-1:0] fifo0_m_axi_bid; wire [ 3:0] fifo0_m_axi_bid;
wire [ 8-1:0] fifo0_m_axi_bresp; wire [ 7:0] fifo0_m_axi_bresp;
wire [ 4-1:0] fifo0_m_axi_buser; wire [ 3:0] fifo0_m_axi_buser;
wire [ 4-1:0] fifo0_m_axi_bvalid; wire [ 3:0] fifo0_m_axi_bvalid;
wire [ 4-1:0] fifo0_m_axi_bready; wire [ 3:0] fifo0_m_axi_bready;
wire [ 4-1:0] fifo0_m_axi_arid; wire [ 3:0] fifo0_m_axi_arid;
wire [128-1:0] fifo0_m_axi_araddr; wire [ 127:0] fifo0_m_axi_araddr;
wire [ 32-1:0] fifo0_m_axi_arlen; wire [ 31:0] fifo0_m_axi_arlen;
wire [ 12-1:0] fifo0_m_axi_arsize; wire [ 11:0] fifo0_m_axi_arsize;
wire [ 8-1:0] fifo0_m_axi_arburst; wire [ 7:0] fifo0_m_axi_arburst;
wire [ 4-1:0] fifo0_m_axi_arlock; wire [ 3:0] fifo0_m_axi_arlock;
wire [ 16-1:0] fifo0_m_axi_arcache; wire [ 15:0] fifo0_m_axi_arcache;
wire [ 12-1:0] fifo0_m_axi_arprot; wire [ 11:0] fifo0_m_axi_arprot;
wire [ 16-1:0] fifo0_m_axi_arqos; wire [ 15:0] fifo0_m_axi_arqos;
wire [ 16-1:0] fifo0_m_axi_arregion; wire [ 15:0] fifo0_m_axi_arregion;
wire [ 4-1:0] fifo0_m_axi_aruser; wire [ 3:0] fifo0_m_axi_aruser;
wire [ 4-1:0] fifo0_m_axi_arvalid; wire [ 3:0] fifo0_m_axi_arvalid;
wire [ 4-1:0] fifo0_m_axi_arready; wire [ 3:0] fifo0_m_axi_arready;
wire [ 4-1:0] fifo0_m_axi_rid; wire [ 3:0] fifo0_m_axi_rid;
wire [256-1:0] fifo0_m_axi_rdata; wire [ 255:0] fifo0_m_axi_rdata;
wire [ 8-1:0] fifo0_m_axi_rresp; wire [ 7:0] fifo0_m_axi_rresp;
wire [ 4-1:0] fifo0_m_axi_rlast; wire [ 3:0] fifo0_m_axi_rlast;
wire [ 4-1:0] fifo0_m_axi_ruser; wire [ 3:0] fifo0_m_axi_ruser;
wire [ 4-1:0] fifo0_m_axi_rvalid; wire [ 3:0] fifo0_m_axi_rvalid;
wire [ 4-1:0] fifo0_m_axi_rready; wire [ 3:0] fifo0_m_axi_rready;
rfnoc_block_axi_ram_fifo #( rfnoc_block_axi_ram_fifo #(
.THIS_PORTID (3), .THIS_PORTID (3),
@@ -682,7 +734,6 @@ module rfnoc_image_core #(
.mem_clk (fifo0_mem_clk), .mem_clk (fifo0_mem_clk),
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
.axi_rst (fifo0_axi_rst), .axi_rst (fifo0_axi_rst),
.m_axi_awid (fifo0_m_axi_awid), .m_axi_awid (fifo0_m_axi_awid),
.m_axi_awaddr (fifo0_m_axi_awaddr), .m_axi_awaddr (fifo0_m_axi_awaddr),
@@ -728,7 +779,6 @@ module rfnoc_image_core #(
.m_axi_ruser (fifo0_m_axi_ruser), .m_axi_ruser (fifo0_m_axi_ruser),
.m_axi_rvalid (fifo0_m_axi_rvalid), .m_axi_rvalid (fifo0_m_axi_rvalid),
.m_axi_rready (fifo0_m_axi_rready), .m_axi_rready (fifo0_m_axi_rready),
.s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}),
@@ -747,10 +797,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready) .m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Static Router // Static Router
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_radio0_in_0_tdata = m_ep0_out0_tdata; assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
assign s_radio0_in_0_tlast = m_ep0_out0_tlast; assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
@@ -792,9 +842,10 @@ module rfnoc_image_core #(
assign m_fifo0_out_1_tready = s_ep5_in0_tready; assign m_fifo0_out_1_tready = s_ep5_in0_tready;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Unused Ports // Unused Ports
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}}; assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}};
assign s_fifo0_in_2_tlast = 1'b0; assign s_fifo0_in_2_tlast = 1'b0;
assign s_fifo0_in_2_tvalid = 1'b0; assign s_fifo0_in_2_tvalid = 1'b0;
@@ -804,16 +855,19 @@ module rfnoc_image_core #(
assign m_fifo0_out_2_tready = 1'b1; assign m_fifo0_out_2_tready = 1'b1;
assign m_fifo0_out_3_tready = 1'b1; assign m_fifo0_out_3_tready = 1'b1;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains // Clock Domains
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk; assign radio0_radio_clk = radio_clk;
assign fifo0_mem_clk = dram_clk; assign fifo0_mem_clk = dram_clk;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// IO Port Connection // IO Port Connection
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Master/Slave Connections: // Master/Slave Connections:
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
@@ -883,3 +937,6 @@ module rfnoc_image_core #(
assign radio0_radio_time = radio_time; assign radio0_radio_time = radio_time;
endmodule endmodule
`default_nettype wire
top/n3xx/n300_rfnoc_image_core.v
+240 -189
View File
@@ -1,18 +1,31 @@
// //
// Copyright 2020 Ettus Research, A National Instruments Brand // Copyright 2021 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: rfnoc_image_core (for n300) // Module: rfnoc_image_core (for n300)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) //
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// File generated on: 2020-09-02T12:02:55.936585 //
// Source: ./n300_rfnoc_image_core.yml // File generated on: 2021-05-03T08:51:08.459279
// Source SHA256: e9dd3107c1f434abca5d183f64dfc5e53d52192f5d488cab07b239c3b44b2593 // Source: n300_rfnoc_image_core.yml
// Source SHA256: 64f2b862b3e60cb0456befb88ea28825b6bba271ff4e86a24ab618932773a861
//
`default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0} parameter CHDR_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) ( ) (
// Clocks // Clocks
input wire chdr_aclk, input wire chdr_aclk,
@@ -22,112 +35,117 @@ module rfnoc_image_core #(
input wire dram_clk, input wire dram_clk,
// Basic // Basic
input wire [ 15:0] device_id, input wire [ 15:0] device_id,
//// IO ports //////////////////////////////////
// IO ports /////////////////////////
// ctrlport_radio0 // ctrlport_radio0
output wire [ 1-1:0] m_ctrlport_radio0_req_wr, output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 1-1:0] m_ctrlport_radio0_req_rd, output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire [ 20-1:0] m_ctrlport_radio0_req_addr, output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 32-1:0] m_ctrlport_radio0_req_data, output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio0_req_time, output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio0_resp_status, input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 32-1:0] m_ctrlport_radio0_resp_data, input wire [ 31:0] m_ctrlport_radio0_resp_data,
// time_keeper // time_keeper
input wire [ 64-1:0] radio_time, input wire [ 63:0] radio_time,
// x300_radio0 // x300_radio0
input wire [ 64-1:0] radio_rx_data_radio0, input wire [ 63:0] radio_rx_data_radio0,
input wire [ 2-1:0] radio_rx_stb_radio0, input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 2-1:0] radio_rx_running_radio0, output wire [ 1:0] radio_rx_running_radio0,
output wire [ 64-1:0] radio_tx_data_radio0, output wire [ 63:0] radio_tx_data_radio0,
input wire [ 2-1:0] radio_tx_stb_radio0, input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 2-1:0] radio_tx_running_radio0, output wire [ 1:0] radio_tx_running_radio0,
// dram // dram
input wire [ 1-1:0] axi_rst, input wire [ 0:0] axi_rst,
output wire [ 4-1:0] m_axi_awid, output wire [ 3:0] m_axi_awid,
output wire [128-1:0] m_axi_awaddr, output wire [ 127:0] m_axi_awaddr,
output wire [ 32-1:0] m_axi_awlen, output wire [ 31:0] m_axi_awlen,
output wire [ 12-1:0] m_axi_awsize, output wire [ 11:0] m_axi_awsize,
output wire [ 8-1:0] m_axi_awburst, output wire [ 7:0] m_axi_awburst,
output wire [ 4-1:0] m_axi_awlock, output wire [ 3:0] m_axi_awlock,
output wire [ 16-1:0] m_axi_awcache, output wire [ 15:0] m_axi_awcache,
output wire [ 12-1:0] m_axi_awprot, output wire [ 11:0] m_axi_awprot,
output wire [ 16-1:0] m_axi_awqos, output wire [ 15:0] m_axi_awqos,
output wire [ 16-1:0] m_axi_awregion, output wire [ 15:0] m_axi_awregion,
output wire [ 4-1:0] m_axi_awuser, output wire [ 3:0] m_axi_awuser,
output wire [ 4-1:0] m_axi_awvalid, output wire [ 3:0] m_axi_awvalid,
input wire [ 4-1:0] m_axi_awready, input wire [ 3:0] m_axi_awready,
output wire [256-1:0] m_axi_wdata, output wire [ 255:0] m_axi_wdata,
output wire [ 32-1:0] m_axi_wstrb, output wire [ 31:0] m_axi_wstrb,
output wire [ 4-1:0] m_axi_wlast, output wire [ 3:0] m_axi_wlast,
output wire [ 4-1:0] m_axi_wuser, output wire [ 3:0] m_axi_wuser,
output wire [ 4-1:0] m_axi_wvalid, output wire [ 3:0] m_axi_wvalid,
input wire [ 4-1:0] m_axi_wready, input wire [ 3:0] m_axi_wready,
input wire [ 4-1:0] m_axi_bid, input wire [ 3:0] m_axi_bid,
input wire [ 8-1:0] m_axi_bresp, input wire [ 7:0] m_axi_bresp,
input wire [ 4-1:0] m_axi_buser, input wire [ 3:0] m_axi_buser,
input wire [ 4-1:0] m_axi_bvalid, input wire [ 3:0] m_axi_bvalid,
output wire [ 4-1:0] m_axi_bready, output wire [ 3:0] m_axi_bready,
output wire [ 4-1:0] m_axi_arid, output wire [ 3:0] m_axi_arid,
output wire [128-1:0] m_axi_araddr, output wire [ 127:0] m_axi_araddr,
output wire [ 32-1:0] m_axi_arlen, output wire [ 31:0] m_axi_arlen,
output wire [ 12-1:0] m_axi_arsize, output wire [ 11:0] m_axi_arsize,
output wire [ 8-1:0] m_axi_arburst, output wire [ 7:0] m_axi_arburst,
output wire [ 4-1:0] m_axi_arlock, output wire [ 3:0] m_axi_arlock,
output wire [ 16-1:0] m_axi_arcache, output wire [ 15:0] m_axi_arcache,
output wire [ 12-1:0] m_axi_arprot, output wire [ 11:0] m_axi_arprot,
output wire [ 16-1:0] m_axi_arqos, output wire [ 15:0] m_axi_arqos,
output wire [ 16-1:0] m_axi_arregion, output wire [ 15:0] m_axi_arregion,
output wire [ 4-1:0] m_axi_aruser, output wire [ 3:0] m_axi_aruser,
output wire [ 4-1:0] m_axi_arvalid, output wire [ 3:0] m_axi_arvalid,
input wire [ 4-1:0] m_axi_arready, input wire [ 3:0] m_axi_arready,
input wire [ 4-1:0] m_axi_rid, input wire [ 3:0] m_axi_rid,
input wire [256-1:0] m_axi_rdata, input wire [ 255:0] m_axi_rdata,
input wire [ 8-1:0] m_axi_rresp, input wire [ 7:0] m_axi_rresp,
input wire [ 4-1:0] m_axi_rlast, input wire [ 3:0] m_axi_rlast,
input wire [ 4-1:0] m_axi_ruser, input wire [ 3:0] m_axi_ruser,
input wire [ 4-1:0] m_axi_rvalid, input wire [ 3:0] m_axi_rvalid,
output wire [ 4-1:0] m_axi_rready, output wire [ 3:0] m_axi_rready,
// Transport 0 (eth0 1G)
input wire [64-1:0] s_eth0_tdata, // Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [64-1:0] m_eth0_tdata, output wire [CHDR_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1 10G) // Transport 1 (eth1)
input wire [64-1:0] s_eth1_tdata, input wire [CHDR_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [64-1:0] m_eth1_tdata, output wire [CHDR_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (dma dma) // Transport 2 (dma)
input wire [64-1:0] s_dma_tdata, input wire [CHDR_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [64-1:0] m_dma_tdata, output wire [CHDR_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam CHDR_W = 64;
localparam MTU = 10;
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// CHDR Crossbar // CHDR Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
@@ -190,9 +208,18 @@ module rfnoc_image_core #(
.ext_rtcfg_ack () .ext_rtcfg_ack ()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Stream Endpoints // Stream Endpoints
// ---------------------------------------------------- //---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
@@ -216,7 +243,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
@@ -255,6 +282,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 32768;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
@@ -277,7 +312,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
@@ -316,6 +351,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 4096;
localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
@@ -338,7 +381,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (12), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
@@ -377,6 +420,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 4096;
localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
@@ -399,7 +450,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (12), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
@@ -439,10 +490,9 @@ module rfnoc_image_core #(
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Control Crossbar // Control Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast; wire m_core_ctrl_tlast, s_core_ctrl_tlast;
@@ -487,9 +537,11 @@ module rfnoc_image_core #(
.deadlock_detected() .deadlock_detected()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// RFNoC Core Kernel // RFNoC Core Kernel
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [(512*4)-1:0] rfnoc_core_config, rfnoc_core_status; wire [(512*4)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #( rfnoc_core_kernel #(
@@ -527,13 +579,15 @@ module rfnoc_image_core #(
.rfnoc_core_status (rfnoc_core_status) .rfnoc_core_status (rfnoc_core_status)
); );
// ----------------------------------------------------
// Blocks
// ----------------------------------------------------
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// duc0 // duc0
// ---------------------------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ;
wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ;
@@ -544,7 +598,6 @@ module rfnoc_image_core #(
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
wire m_duc0_out_1_tready, m_duc0_out_0_tready; wire m_duc0_out_1_tready, m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -558,8 +611,6 @@ module rfnoc_image_core #(
.ce_clk (duc0_ce_clk), .ce_clk (duc0_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}),
@@ -578,10 +629,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready) .m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// ddc0 // ddc0
// ---------------------------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
@@ -592,7 +643,6 @@ module rfnoc_image_core #(
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -606,8 +656,6 @@ module rfnoc_image_core #(
.ce_clk (ddc0_ce_clk), .ce_clk (ddc0_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
.s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}),
@@ -626,10 +674,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready) .m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// radio0 // radio0
// ---------------------------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
@@ -641,25 +689,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 1-1:0] radio0_m_ctrlport_req_rd; wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 20-1:0] radio0_m_ctrlport_req_addr; wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 32-1:0] radio0_m_ctrlport_req_data; wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio0_m_ctrlport_req_has_time; wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 64-1:0] radio0_m_ctrlport_req_time; wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 1-1:0] radio0_m_ctrlport_resp_ack; wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 2-1:0] radio0_m_ctrlport_resp_status; wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 32-1:0] radio0_m_ctrlport_resp_data; wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio0_radio_time; wire [ 63:0] radio0_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio0_radio_rx_data; wire [ 63:0] radio0_radio_rx_data;
wire [ 2-1:0] radio0_radio_rx_stb; wire [ 1:0] radio0_radio_rx_stb;
wire [ 2-1:0] radio0_radio_rx_running; wire [ 1:0] radio0_radio_rx_running;
wire [ 64-1:0] radio0_radio_tx_data; wire [ 63:0] radio0_radio_tx_data;
wire [ 2-1:0] radio0_radio_tx_stb; wire [ 1:0] radio0_radio_tx_stb;
wire [ 2-1:0] radio0_radio_tx_running; wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
@@ -672,7 +720,6 @@ module rfnoc_image_core #(
.radio_clk (radio0_radio_clk), .radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]),
.rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
@@ -690,7 +737,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio0_radio_tx_data), .radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb), .radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running), .radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
@@ -709,10 +755,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// replay0 // replay0
// ---------------------------------------------------- //-----------------------------------
wire replay0_mem_clk; wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ; wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
@@ -724,51 +770,51 @@ module rfnoc_image_core #(
wire m_replay0_out_1_tready, m_replay0_out_0_tready; wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram // axi_ram
wire [ 1-1:0] replay0_axi_rst; wire [ 0:0] replay0_axi_rst;
wire [ 4-1:0] replay0_m_axi_awid; wire [ 3:0] replay0_m_axi_awid;
wire [128-1:0] replay0_m_axi_awaddr; wire [ 127:0] replay0_m_axi_awaddr;
wire [ 32-1:0] replay0_m_axi_awlen; wire [ 31:0] replay0_m_axi_awlen;
wire [ 12-1:0] replay0_m_axi_awsize; wire [ 11:0] replay0_m_axi_awsize;
wire [ 8-1:0] replay0_m_axi_awburst; wire [ 7:0] replay0_m_axi_awburst;
wire [ 4-1:0] replay0_m_axi_awlock; wire [ 3:0] replay0_m_axi_awlock;
wire [ 16-1:0] replay0_m_axi_awcache; wire [ 15:0] replay0_m_axi_awcache;
wire [ 12-1:0] replay0_m_axi_awprot; wire [ 11:0] replay0_m_axi_awprot;
wire [ 16-1:0] replay0_m_axi_awqos; wire [ 15:0] replay0_m_axi_awqos;
wire [ 16-1:0] replay0_m_axi_awregion; wire [ 15:0] replay0_m_axi_awregion;
wire [ 4-1:0] replay0_m_axi_awuser; wire [ 3:0] replay0_m_axi_awuser;
wire [ 4-1:0] replay0_m_axi_awvalid; wire [ 3:0] replay0_m_axi_awvalid;
wire [ 4-1:0] replay0_m_axi_awready; wire [ 3:0] replay0_m_axi_awready;
wire [256-1:0] replay0_m_axi_wdata; wire [ 255:0] replay0_m_axi_wdata;
wire [ 32-1:0] replay0_m_axi_wstrb; wire [ 31:0] replay0_m_axi_wstrb;
wire [ 4-1:0] replay0_m_axi_wlast; wire [ 3:0] replay0_m_axi_wlast;
wire [ 4-1:0] replay0_m_axi_wuser; wire [ 3:0] replay0_m_axi_wuser;
wire [ 4-1:0] replay0_m_axi_wvalid; wire [ 3:0] replay0_m_axi_wvalid;
wire [ 4-1:0] replay0_m_axi_wready; wire [ 3:0] replay0_m_axi_wready;
wire [ 4-1:0] replay0_m_axi_bid; wire [ 3:0] replay0_m_axi_bid;
wire [ 8-1:0] replay0_m_axi_bresp; wire [ 7:0] replay0_m_axi_bresp;
wire [ 4-1:0] replay0_m_axi_buser; wire [ 3:0] replay0_m_axi_buser;
wire [ 4-1:0] replay0_m_axi_bvalid; wire [ 3:0] replay0_m_axi_bvalid;
wire [ 4-1:0] replay0_m_axi_bready; wire [ 3:0] replay0_m_axi_bready;
wire [ 4-1:0] replay0_m_axi_arid; wire [ 3:0] replay0_m_axi_arid;
wire [128-1:0] replay0_m_axi_araddr; wire [ 127:0] replay0_m_axi_araddr;
wire [ 32-1:0] replay0_m_axi_arlen; wire [ 31:0] replay0_m_axi_arlen;
wire [ 12-1:0] replay0_m_axi_arsize; wire [ 11:0] replay0_m_axi_arsize;
wire [ 8-1:0] replay0_m_axi_arburst; wire [ 7:0] replay0_m_axi_arburst;
wire [ 4-1:0] replay0_m_axi_arlock; wire [ 3:0] replay0_m_axi_arlock;
wire [ 16-1:0] replay0_m_axi_arcache; wire [ 15:0] replay0_m_axi_arcache;
wire [ 12-1:0] replay0_m_axi_arprot; wire [ 11:0] replay0_m_axi_arprot;
wire [ 16-1:0] replay0_m_axi_arqos; wire [ 15:0] replay0_m_axi_arqos;
wire [ 16-1:0] replay0_m_axi_arregion; wire [ 15:0] replay0_m_axi_arregion;
wire [ 4-1:0] replay0_m_axi_aruser; wire [ 3:0] replay0_m_axi_aruser;
wire [ 4-1:0] replay0_m_axi_arvalid; wire [ 3:0] replay0_m_axi_arvalid;
wire [ 4-1:0] replay0_m_axi_arready; wire [ 3:0] replay0_m_axi_arready;
wire [ 4-1:0] replay0_m_axi_rid; wire [ 3:0] replay0_m_axi_rid;
wire [256-1:0] replay0_m_axi_rdata; wire [ 255:0] replay0_m_axi_rdata;
wire [ 8-1:0] replay0_m_axi_rresp; wire [ 7:0] replay0_m_axi_rresp;
wire [ 4-1:0] replay0_m_axi_rlast; wire [ 3:0] replay0_m_axi_rlast;
wire [ 4-1:0] replay0_m_axi_ruser; wire [ 3:0] replay0_m_axi_ruser;
wire [ 4-1:0] replay0_m_axi_rvalid; wire [ 3:0] replay0_m_axi_rvalid;
wire [ 4-1:0] replay0_m_axi_rready; wire [ 3:0] replay0_m_axi_rready;
rfnoc_block_replay #( rfnoc_block_replay #(
.THIS_PORTID (5), .THIS_PORTID (5),
@@ -783,7 +829,6 @@ module rfnoc_image_core #(
.mem_clk (replay0_mem_clk), .mem_clk (replay0_mem_clk),
.rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]),
.rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]),
.axi_rst (replay0_axi_rst), .axi_rst (replay0_axi_rst),
.m_axi_awid (replay0_m_axi_awid), .m_axi_awid (replay0_m_axi_awid),
.m_axi_awaddr (replay0_m_axi_awaddr), .m_axi_awaddr (replay0_m_axi_awaddr),
@@ -829,7 +874,6 @@ module rfnoc_image_core #(
.m_axi_ruser (replay0_m_axi_ruser), .m_axi_ruser (replay0_m_axi_ruser),
.m_axi_rvalid (replay0_m_axi_rvalid), .m_axi_rvalid (replay0_m_axi_rvalid),
.m_axi_rready (replay0_m_axi_rready), .m_axi_rready (replay0_m_axi_rready),
.s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
@@ -848,10 +892,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready) .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Static Router // Static Router
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_duc0_in_0_tdata = m_ep0_out0_tdata; assign s_duc0_in_0_tdata = m_ep0_out0_tdata;
assign s_duc0_in_0_tlast = m_ep0_out0_tlast; assign s_duc0_in_0_tlast = m_ep0_out0_tlast;
assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid;
@@ -913,22 +957,26 @@ module rfnoc_image_core #(
assign m_replay0_out_1_tready = s_ep3_in0_tready; assign m_replay0_out_1_tready = s_ep3_in0_tready;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Unused Ports // Unused Ports
// ---------------------------------------------------- //---------------------------------------------------------------------------
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains // Clock Domains
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk; assign radio0_radio_clk = radio_clk;
assign ddc0_ce_clk = rfnoc_chdr_clk; assign ddc0_ce_clk = rfnoc_chdr_clk;
assign duc0_ce_clk = rfnoc_chdr_clk; assign duc0_ce_clk = rfnoc_chdr_clk;
assign replay0_mem_clk = dram_clk; assign replay0_mem_clk = dram_clk;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// IO Port Connection // IO Port Connection
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Master/Slave Connections: // Master/Slave Connections:
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
@@ -998,3 +1046,6 @@ module rfnoc_image_core #(
assign radio0_radio_time = radio_time; assign radio0_radio_time = radio_time;
endmodule endmodule
`default_nettype wire
top/n3xx/n300_rfnoc_image_core.vh
+21
View File
@@ -0,0 +1,21 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n300)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:08.505495
// Source: n300_rfnoc_image_core.yml
// Source SHA256: 64f2b862b3e60cb0456befb88ea28825b6bba271ff4e86a24ab618932773a861
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n310_bist_image_core.v
+288 -217
View File
@@ -1,18 +1,31 @@
// //
// Copyright 2019 Ettus Research, A National Instruments Brand // Copyright 2021 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: rfnoc_image_core (for n310) // Module: rfnoc_image_core (for n310)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) //
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// File generated on: 2019-11-08T15:58:14.371732 //
// Source: ./n3xx/n310_bist_image_core.yml // File generated on: 2021-05-03T08:51:05.500549
// Source SHA256: 1a9ffb97d9678e700ad2aa172d206b6be9af30c7c0b014c21007d1de028a59d4 // Source: n310_bist_image_core.yml
// Source SHA256: fe5a985fa2e6edde671a8fb818d11a583d818a74f707df9bb107901060780eea
//
`default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0} parameter CHDR_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) ( ) (
// Clocks // Clocks
input wire chdr_aclk, input wire chdr_aclk,
@@ -22,130 +35,135 @@ module rfnoc_image_core #(
input wire dram_clk, input wire dram_clk,
// Basic // Basic
input wire [ 15:0] device_id, input wire [ 15:0] device_id,
//// IO ports //////////////////////////////////
// IO ports /////////////////////////
// ctrlport_radio0 // ctrlport_radio0
output wire [ 1-1:0] m_ctrlport_radio0_req_wr, output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 1-1:0] m_ctrlport_radio0_req_rd, output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire [ 20-1:0] m_ctrlport_radio0_req_addr, output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 32-1:0] m_ctrlport_radio0_req_data, output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio0_req_time, output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio0_resp_status, input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 32-1:0] m_ctrlport_radio0_resp_data, input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1 // ctrlport_radio1
output wire [ 1-1:0] m_ctrlport_radio1_req_wr, output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 1-1:0] m_ctrlport_radio1_req_rd, output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire [ 20-1:0] m_ctrlport_radio1_req_addr, output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 32-1:0] m_ctrlport_radio1_req_data, output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio1_req_time, output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio1_resp_status, input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 32-1:0] m_ctrlport_radio1_resp_data, input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time_keeper // time_keeper
input wire [ 64-1:0] radio_time, input wire [ 63:0] radio_time,
// x300_radio0 // x300_radio0
input wire [ 64-1:0] radio_rx_data_radio0, input wire [ 63:0] radio_rx_data_radio0,
input wire [ 2-1:0] radio_rx_stb_radio0, input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 2-1:0] radio_rx_running_radio0, output wire [ 1:0] radio_rx_running_radio0,
output wire [ 64-1:0] radio_tx_data_radio0, output wire [ 63:0] radio_tx_data_radio0,
input wire [ 2-1:0] radio_tx_stb_radio0, input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 2-1:0] radio_tx_running_radio0, output wire [ 1:0] radio_tx_running_radio0,
// x300_radio1 // x300_radio1
input wire [ 64-1:0] radio_rx_data_radio1, input wire [ 63:0] radio_rx_data_radio1,
input wire [ 2-1:0] radio_rx_stb_radio1, input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 2-1:0] radio_rx_running_radio1, output wire [ 1:0] radio_rx_running_radio1,
output wire [ 64-1:0] radio_tx_data_radio1, output wire [ 63:0] radio_tx_data_radio1,
input wire [ 2-1:0] radio_tx_stb_radio1, input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 2-1:0] radio_tx_running_radio1, output wire [ 1:0] radio_tx_running_radio1,
// dram // dram
input wire [ 1-1:0] axi_rst, input wire [ 0:0] axi_rst,
output wire [ 4-1:0] m_axi_awid, output wire [ 3:0] m_axi_awid,
output wire [128-1:0] m_axi_awaddr, output wire [ 127:0] m_axi_awaddr,
output wire [ 32-1:0] m_axi_awlen, output wire [ 31:0] m_axi_awlen,
output wire [ 12-1:0] m_axi_awsize, output wire [ 11:0] m_axi_awsize,
output wire [ 8-1:0] m_axi_awburst, output wire [ 7:0] m_axi_awburst,
output wire [ 4-1:0] m_axi_awlock, output wire [ 3:0] m_axi_awlock,
output wire [ 16-1:0] m_axi_awcache, output wire [ 15:0] m_axi_awcache,
output wire [ 12-1:0] m_axi_awprot, output wire [ 11:0] m_axi_awprot,
output wire [ 16-1:0] m_axi_awqos, output wire [ 15:0] m_axi_awqos,
output wire [ 16-1:0] m_axi_awregion, output wire [ 15:0] m_axi_awregion,
output wire [ 4-1:0] m_axi_awuser, output wire [ 3:0] m_axi_awuser,
output wire [ 4-1:0] m_axi_awvalid, output wire [ 3:0] m_axi_awvalid,
input wire [ 4-1:0] m_axi_awready, input wire [ 3:0] m_axi_awready,
output wire [256-1:0] m_axi_wdata, output wire [ 255:0] m_axi_wdata,
output wire [ 32-1:0] m_axi_wstrb, output wire [ 31:0] m_axi_wstrb,
output wire [ 4-1:0] m_axi_wlast, output wire [ 3:0] m_axi_wlast,
output wire [ 4-1:0] m_axi_wuser, output wire [ 3:0] m_axi_wuser,
output wire [ 4-1:0] m_axi_wvalid, output wire [ 3:0] m_axi_wvalid,
input wire [ 4-1:0] m_axi_wready, input wire [ 3:0] m_axi_wready,
input wire [ 4-1:0] m_axi_bid, input wire [ 3:0] m_axi_bid,
input wire [ 8-1:0] m_axi_bresp, input wire [ 7:0] m_axi_bresp,
input wire [ 4-1:0] m_axi_buser, input wire [ 3:0] m_axi_buser,
input wire [ 4-1:0] m_axi_bvalid, input wire [ 3:0] m_axi_bvalid,
output wire [ 4-1:0] m_axi_bready, output wire [ 3:0] m_axi_bready,
output wire [ 4-1:0] m_axi_arid, output wire [ 3:0] m_axi_arid,
output wire [128-1:0] m_axi_araddr, output wire [ 127:0] m_axi_araddr,
output wire [ 32-1:0] m_axi_arlen, output wire [ 31:0] m_axi_arlen,
output wire [ 12-1:0] m_axi_arsize, output wire [ 11:0] m_axi_arsize,
output wire [ 8-1:0] m_axi_arburst, output wire [ 7:0] m_axi_arburst,
output wire [ 4-1:0] m_axi_arlock, output wire [ 3:0] m_axi_arlock,
output wire [ 16-1:0] m_axi_arcache, output wire [ 15:0] m_axi_arcache,
output wire [ 12-1:0] m_axi_arprot, output wire [ 11:0] m_axi_arprot,
output wire [ 16-1:0] m_axi_arqos, output wire [ 15:0] m_axi_arqos,
output wire [ 16-1:0] m_axi_arregion, output wire [ 15:0] m_axi_arregion,
output wire [ 4-1:0] m_axi_aruser, output wire [ 3:0] m_axi_aruser,
output wire [ 4-1:0] m_axi_arvalid, output wire [ 3:0] m_axi_arvalid,
input wire [ 4-1:0] m_axi_arready, input wire [ 3:0] m_axi_arready,
input wire [ 4-1:0] m_axi_rid, input wire [ 3:0] m_axi_rid,
input wire [256-1:0] m_axi_rdata, input wire [ 255:0] m_axi_rdata,
input wire [ 8-1:0] m_axi_rresp, input wire [ 7:0] m_axi_rresp,
input wire [ 4-1:0] m_axi_rlast, input wire [ 3:0] m_axi_rlast,
input wire [ 4-1:0] m_axi_ruser, input wire [ 3:0] m_axi_ruser,
input wire [ 4-1:0] m_axi_rvalid, input wire [ 3:0] m_axi_rvalid,
output wire [ 4-1:0] m_axi_rready, output wire [ 3:0] m_axi_rready,
// Transport 0 (eth0 1G)
input wire [64-1:0] s_eth0_tdata, // Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [64-1:0] m_eth0_tdata, output wire [CHDR_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1 10G) // Transport 1 (eth1)
input wire [64-1:0] s_eth1_tdata, input wire [CHDR_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [64-1:0] m_eth1_tdata, output wire [CHDR_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (dma dma) // Transport 2 (dma)
input wire [64-1:0] s_dma_tdata, input wire [CHDR_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [64-1:0] m_dma_tdata, output wire [CHDR_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam CHDR_W = 64;
localparam MTU = 10;
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// CHDR Crossbar // CHDR Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
@@ -224,9 +242,18 @@ module rfnoc_image_core #(
.ext_rtcfg_ack () .ext_rtcfg_ack ()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Stream Endpoints // Stream Endpoints
// ---------------------------------------------------- //---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 16384;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
@@ -250,7 +277,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
@@ -289,6 +316,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 16384;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
@@ -311,7 +346,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
@@ -350,6 +385,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 16384;
localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
@@ -372,7 +415,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
@@ -411,6 +454,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 16384;
localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
@@ -433,7 +484,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
@@ -472,6 +523,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 16384;
localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
@@ -494,7 +553,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (4), .INST_NUM (4),
.CTRL_XBAR_PORT (5), .CTRL_XBAR_PORT (5),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
@@ -533,6 +592,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 16384;
localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
@@ -555,7 +622,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (5), .INST_NUM (5),
.CTRL_XBAR_PORT (6), .CTRL_XBAR_PORT (6),
.INGRESS_BUFF_SIZE (14), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
@@ -595,10 +662,9 @@ module rfnoc_image_core #(
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Control Crossbar // Control Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast; wire m_core_ctrl_tlast, s_core_ctrl_tlast;
@@ -639,9 +705,11 @@ module rfnoc_image_core #(
.deadlock_detected() .deadlock_detected()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// RFNoC Core Kernel // RFNoC Core Kernel
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status; wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #( rfnoc_core_kernel #(
@@ -679,13 +747,15 @@ module rfnoc_image_core #(
.rfnoc_core_status (rfnoc_core_status) .rfnoc_core_status (rfnoc_core_status)
); );
// ----------------------------------------------------
// Blocks
// ----------------------------------------------------
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// radio0 // radio0
// ---------------------------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
@@ -697,25 +767,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 1-1:0] radio0_m_ctrlport_req_rd; wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 20-1:0] radio0_m_ctrlport_req_addr; wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 32-1:0] radio0_m_ctrlport_req_data; wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio0_m_ctrlport_req_has_time; wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 64-1:0] radio0_m_ctrlport_req_time; wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 1-1:0] radio0_m_ctrlport_resp_ack; wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 2-1:0] radio0_m_ctrlport_resp_status; wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 32-1:0] radio0_m_ctrlport_resp_data; wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio0_radio_time; wire [ 63:0] radio0_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio0_radio_rx_data; wire [ 63:0] radio0_radio_rx_data;
wire [ 2-1:0] radio0_radio_rx_stb; wire [ 1:0] radio0_radio_rx_stb;
wire [ 2-1:0] radio0_radio_rx_running; wire [ 1:0] radio0_radio_rx_running;
wire [ 64-1:0] radio0_radio_tx_data; wire [ 63:0] radio0_radio_tx_data;
wire [ 2-1:0] radio0_radio_tx_stb; wire [ 1:0] radio0_radio_tx_stb;
wire [ 2-1:0] radio0_radio_tx_running; wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (2), .THIS_PORTID (2),
@@ -728,7 +798,6 @@ module rfnoc_image_core #(
.radio_clk (radio0_radio_clk), .radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
@@ -746,7 +815,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio0_radio_tx_data), .radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb), .radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running), .radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
@@ -765,10 +833,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// radio1 // radio1
// ---------------------------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
@@ -780,25 +848,25 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tready, m_radio1_out_0_tready; wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 1-1:0] radio1_m_ctrlport_req_rd; wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 20-1:0] radio1_m_ctrlport_req_addr; wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 32-1:0] radio1_m_ctrlport_req_data; wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio1_m_ctrlport_req_has_time; wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire [ 64-1:0] radio1_m_ctrlport_req_time; wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 1-1:0] radio1_m_ctrlport_resp_ack; wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 2-1:0] radio1_m_ctrlport_resp_status; wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 32-1:0] radio1_m_ctrlport_resp_data; wire [ 31:0] radio1_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio1_radio_time; wire [ 63:0] radio1_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio1_radio_rx_data; wire [ 63:0] radio1_radio_rx_data;
wire [ 2-1:0] radio1_radio_rx_stb; wire [ 1:0] radio1_radio_rx_stb;
wire [ 2-1:0] radio1_radio_rx_running; wire [ 1:0] radio1_radio_rx_running;
wire [ 64-1:0] radio1_radio_tx_data; wire [ 63:0] radio1_radio_tx_data;
wire [ 2-1:0] radio1_radio_tx_stb; wire [ 1:0] radio1_radio_tx_stb;
wire [ 2-1:0] radio1_radio_tx_running; wire [ 1:0] radio1_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (3), .THIS_PORTID (3),
@@ -811,7 +879,6 @@ module rfnoc_image_core #(
.radio_clk (radio1_radio_clk), .radio_clk (radio1_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
.m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr),
@@ -829,7 +896,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio1_radio_tx_data), .radio_tx_data (radio1_radio_tx_data),
.radio_tx_stb (radio1_radio_tx_stb), .radio_tx_stb (radio1_radio_tx_stb),
.radio_tx_running (radio1_radio_tx_running), .radio_tx_running (radio1_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}),
@@ -848,10 +914,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// fifo0 // fifo0
// ---------------------------------------------------- //-----------------------------------
wire fifo0_mem_clk; wire fifo0_mem_clk;
wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
@@ -863,51 +929,51 @@ module rfnoc_image_core #(
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram // axi_ram
wire [ 1-1:0] fifo0_axi_rst; wire [ 0:0] fifo0_axi_rst;
wire [ 4-1:0] fifo0_m_axi_awid; wire [ 3:0] fifo0_m_axi_awid;
wire [128-1:0] fifo0_m_axi_awaddr; wire [ 127:0] fifo0_m_axi_awaddr;
wire [ 32-1:0] fifo0_m_axi_awlen; wire [ 31:0] fifo0_m_axi_awlen;
wire [ 12-1:0] fifo0_m_axi_awsize; wire [ 11:0] fifo0_m_axi_awsize;
wire [ 8-1:0] fifo0_m_axi_awburst; wire [ 7:0] fifo0_m_axi_awburst;
wire [ 4-1:0] fifo0_m_axi_awlock; wire [ 3:0] fifo0_m_axi_awlock;
wire [ 16-1:0] fifo0_m_axi_awcache; wire [ 15:0] fifo0_m_axi_awcache;
wire [ 12-1:0] fifo0_m_axi_awprot; wire [ 11:0] fifo0_m_axi_awprot;
wire [ 16-1:0] fifo0_m_axi_awqos; wire [ 15:0] fifo0_m_axi_awqos;
wire [ 16-1:0] fifo0_m_axi_awregion; wire [ 15:0] fifo0_m_axi_awregion;
wire [ 4-1:0] fifo0_m_axi_awuser; wire [ 3:0] fifo0_m_axi_awuser;
wire [ 4-1:0] fifo0_m_axi_awvalid; wire [ 3:0] fifo0_m_axi_awvalid;
wire [ 4-1:0] fifo0_m_axi_awready; wire [ 3:0] fifo0_m_axi_awready;
wire [256-1:0] fifo0_m_axi_wdata; wire [ 255:0] fifo0_m_axi_wdata;
wire [ 32-1:0] fifo0_m_axi_wstrb; wire [ 31:0] fifo0_m_axi_wstrb;
wire [ 4-1:0] fifo0_m_axi_wlast; wire [ 3:0] fifo0_m_axi_wlast;
wire [ 4-1:0] fifo0_m_axi_wuser; wire [ 3:0] fifo0_m_axi_wuser;
wire [ 4-1:0] fifo0_m_axi_wvalid; wire [ 3:0] fifo0_m_axi_wvalid;
wire [ 4-1:0] fifo0_m_axi_wready; wire [ 3:0] fifo0_m_axi_wready;
wire [ 4-1:0] fifo0_m_axi_bid; wire [ 3:0] fifo0_m_axi_bid;
wire [ 8-1:0] fifo0_m_axi_bresp; wire [ 7:0] fifo0_m_axi_bresp;
wire [ 4-1:0] fifo0_m_axi_buser; wire [ 3:0] fifo0_m_axi_buser;
wire [ 4-1:0] fifo0_m_axi_bvalid; wire [ 3:0] fifo0_m_axi_bvalid;
wire [ 4-1:0] fifo0_m_axi_bready; wire [ 3:0] fifo0_m_axi_bready;
wire [ 4-1:0] fifo0_m_axi_arid; wire [ 3:0] fifo0_m_axi_arid;
wire [128-1:0] fifo0_m_axi_araddr; wire [ 127:0] fifo0_m_axi_araddr;
wire [ 32-1:0] fifo0_m_axi_arlen; wire [ 31:0] fifo0_m_axi_arlen;
wire [ 12-1:0] fifo0_m_axi_arsize; wire [ 11:0] fifo0_m_axi_arsize;
wire [ 8-1:0] fifo0_m_axi_arburst; wire [ 7:0] fifo0_m_axi_arburst;
wire [ 4-1:0] fifo0_m_axi_arlock; wire [ 3:0] fifo0_m_axi_arlock;
wire [ 16-1:0] fifo0_m_axi_arcache; wire [ 15:0] fifo0_m_axi_arcache;
wire [ 12-1:0] fifo0_m_axi_arprot; wire [ 11:0] fifo0_m_axi_arprot;
wire [ 16-1:0] fifo0_m_axi_arqos; wire [ 15:0] fifo0_m_axi_arqos;
wire [ 16-1:0] fifo0_m_axi_arregion; wire [ 15:0] fifo0_m_axi_arregion;
wire [ 4-1:0] fifo0_m_axi_aruser; wire [ 3:0] fifo0_m_axi_aruser;
wire [ 4-1:0] fifo0_m_axi_arvalid; wire [ 3:0] fifo0_m_axi_arvalid;
wire [ 4-1:0] fifo0_m_axi_arready; wire [ 3:0] fifo0_m_axi_arready;
wire [ 4-1:0] fifo0_m_axi_rid; wire [ 3:0] fifo0_m_axi_rid;
wire [256-1:0] fifo0_m_axi_rdata; wire [ 255:0] fifo0_m_axi_rdata;
wire [ 8-1:0] fifo0_m_axi_rresp; wire [ 7:0] fifo0_m_axi_rresp;
wire [ 4-1:0] fifo0_m_axi_rlast; wire [ 3:0] fifo0_m_axi_rlast;
wire [ 4-1:0] fifo0_m_axi_ruser; wire [ 3:0] fifo0_m_axi_ruser;
wire [ 4-1:0] fifo0_m_axi_rvalid; wire [ 3:0] fifo0_m_axi_rvalid;
wire [ 4-1:0] fifo0_m_axi_rready; wire [ 3:0] fifo0_m_axi_rready;
rfnoc_block_axi_ram_fifo #( rfnoc_block_axi_ram_fifo #(
.THIS_PORTID (4), .THIS_PORTID (4),
@@ -925,7 +991,6 @@ module rfnoc_image_core #(
.mem_clk (fifo0_mem_clk), .mem_clk (fifo0_mem_clk),
.rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]),
.rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]),
.axi_rst (fifo0_axi_rst), .axi_rst (fifo0_axi_rst),
.m_axi_awid (fifo0_m_axi_awid), .m_axi_awid (fifo0_m_axi_awid),
.m_axi_awaddr (fifo0_m_axi_awaddr), .m_axi_awaddr (fifo0_m_axi_awaddr),
@@ -971,7 +1036,6 @@ module rfnoc_image_core #(
.m_axi_ruser (fifo0_m_axi_ruser), .m_axi_ruser (fifo0_m_axi_ruser),
.m_axi_rvalid (fifo0_m_axi_rvalid), .m_axi_rvalid (fifo0_m_axi_rvalid),
.m_axi_rready (fifo0_m_axi_rready), .m_axi_rready (fifo0_m_axi_rready),
.s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}),
@@ -990,10 +1054,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready) .m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Static Router // Static Router
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_radio0_in_0_tdata = m_ep0_out0_tdata; assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
assign s_radio0_in_0_tlast = m_ep0_out0_tlast; assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
@@ -1055,9 +1119,10 @@ module rfnoc_image_core #(
assign m_fifo0_out_1_tready = s_ep5_in0_tready; assign m_fifo0_out_1_tready = s_ep5_in0_tready;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Unused Ports // Unused Ports
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}}; assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}};
assign s_fifo0_in_2_tlast = 1'b0; assign s_fifo0_in_2_tlast = 1'b0;
assign s_fifo0_in_2_tvalid = 1'b0; assign s_fifo0_in_2_tvalid = 1'b0;
@@ -1067,17 +1132,20 @@ module rfnoc_image_core #(
assign m_fifo0_out_2_tready = 1'b1; assign m_fifo0_out_2_tready = 1'b1;
assign m_fifo0_out_3_tready = 1'b1; assign m_fifo0_out_3_tready = 1'b1;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains // Clock Domains
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk; assign radio0_radio_clk = radio_clk;
assign radio1_radio_clk = radio_clk; assign radio1_radio_clk = radio_clk;
assign fifo0_mem_clk = dram_clk; assign fifo0_mem_clk = dram_clk;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// IO Port Connection // IO Port Connection
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Master/Slave Connections: // Master/Slave Connections:
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
@@ -1167,3 +1235,6 @@ module rfnoc_image_core #(
assign radio1_radio_time = radio_time; assign radio1_radio_time = radio_time;
endmodule endmodule
`default_nettype wire
top/n3xx/n310_rfnoc_image_core.v
+318 -243
View File
@@ -1,18 +1,31 @@
// //
// Copyright 2020 Ettus Research, A National Instruments Brand // Copyright 2021 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: rfnoc_image_core (for n310) // Module: rfnoc_image_core (for n310)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) //
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// File generated on: 2020-09-02T12:03:00.129190 //
// Source: ./n310_rfnoc_image_core.yml // File generated on: 2021-05-03T08:51:09.232810
// Source SHA256: 39427a6d2533bc5342e99d75d7eaff9368e89ab8ff639821d333143af5ace45b // Source: n310_rfnoc_image_core.yml
// Source SHA256: cc561a3de48fea9e224425413802738d125393f55f6dd46e196db8fdabe09284
//
`default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0} parameter CHDR_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) ( ) (
// Clocks // Clocks
input wire chdr_aclk, input wire chdr_aclk,
@@ -22,130 +35,135 @@ module rfnoc_image_core #(
input wire dram_clk, input wire dram_clk,
// Basic // Basic
input wire [ 15:0] device_id, input wire [ 15:0] device_id,
//// IO ports //////////////////////////////////
// IO ports /////////////////////////
// ctrlport_radio0 // ctrlport_radio0
output wire [ 1-1:0] m_ctrlport_radio0_req_wr, output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 1-1:0] m_ctrlport_radio0_req_rd, output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire [ 20-1:0] m_ctrlport_radio0_req_addr, output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 32-1:0] m_ctrlport_radio0_req_data, output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio0_req_time, output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio0_resp_status, input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 32-1:0] m_ctrlport_radio0_resp_data, input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1 // ctrlport_radio1
output wire [ 1-1:0] m_ctrlport_radio1_req_wr, output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 1-1:0] m_ctrlport_radio1_req_rd, output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire [ 20-1:0] m_ctrlport_radio1_req_addr, output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 32-1:0] m_ctrlport_radio1_req_data, output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio1_req_time, output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio1_resp_status, input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 32-1:0] m_ctrlport_radio1_resp_data, input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time_keeper // time_keeper
input wire [ 64-1:0] radio_time, input wire [ 63:0] radio_time,
// x300_radio0 // x300_radio0
input wire [ 64-1:0] radio_rx_data_radio0, input wire [ 63:0] radio_rx_data_radio0,
input wire [ 2-1:0] radio_rx_stb_radio0, input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 2-1:0] radio_rx_running_radio0, output wire [ 1:0] radio_rx_running_radio0,
output wire [ 64-1:0] radio_tx_data_radio0, output wire [ 63:0] radio_tx_data_radio0,
input wire [ 2-1:0] radio_tx_stb_radio0, input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 2-1:0] radio_tx_running_radio0, output wire [ 1:0] radio_tx_running_radio0,
// x300_radio1 // x300_radio1
input wire [ 64-1:0] radio_rx_data_radio1, input wire [ 63:0] radio_rx_data_radio1,
input wire [ 2-1:0] radio_rx_stb_radio1, input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 2-1:0] radio_rx_running_radio1, output wire [ 1:0] radio_rx_running_radio1,
output wire [ 64-1:0] radio_tx_data_radio1, output wire [ 63:0] radio_tx_data_radio1,
input wire [ 2-1:0] radio_tx_stb_radio1, input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 2-1:0] radio_tx_running_radio1, output wire [ 1:0] radio_tx_running_radio1,
// dram // dram
input wire [ 1-1:0] axi_rst, input wire [ 0:0] axi_rst,
output wire [ 4-1:0] m_axi_awid, output wire [ 3:0] m_axi_awid,
output wire [128-1:0] m_axi_awaddr, output wire [ 127:0] m_axi_awaddr,
output wire [ 32-1:0] m_axi_awlen, output wire [ 31:0] m_axi_awlen,
output wire [ 12-1:0] m_axi_awsize, output wire [ 11:0] m_axi_awsize,
output wire [ 8-1:0] m_axi_awburst, output wire [ 7:0] m_axi_awburst,
output wire [ 4-1:0] m_axi_awlock, output wire [ 3:0] m_axi_awlock,
output wire [ 16-1:0] m_axi_awcache, output wire [ 15:0] m_axi_awcache,
output wire [ 12-1:0] m_axi_awprot, output wire [ 11:0] m_axi_awprot,
output wire [ 16-1:0] m_axi_awqos, output wire [ 15:0] m_axi_awqos,
output wire [ 16-1:0] m_axi_awregion, output wire [ 15:0] m_axi_awregion,
output wire [ 4-1:0] m_axi_awuser, output wire [ 3:0] m_axi_awuser,
output wire [ 4-1:0] m_axi_awvalid, output wire [ 3:0] m_axi_awvalid,
input wire [ 4-1:0] m_axi_awready, input wire [ 3:0] m_axi_awready,
output wire [256-1:0] m_axi_wdata, output wire [ 255:0] m_axi_wdata,
output wire [ 32-1:0] m_axi_wstrb, output wire [ 31:0] m_axi_wstrb,
output wire [ 4-1:0] m_axi_wlast, output wire [ 3:0] m_axi_wlast,
output wire [ 4-1:0] m_axi_wuser, output wire [ 3:0] m_axi_wuser,
output wire [ 4-1:0] m_axi_wvalid, output wire [ 3:0] m_axi_wvalid,
input wire [ 4-1:0] m_axi_wready, input wire [ 3:0] m_axi_wready,
input wire [ 4-1:0] m_axi_bid, input wire [ 3:0] m_axi_bid,
input wire [ 8-1:0] m_axi_bresp, input wire [ 7:0] m_axi_bresp,
input wire [ 4-1:0] m_axi_buser, input wire [ 3:0] m_axi_buser,
input wire [ 4-1:0] m_axi_bvalid, input wire [ 3:0] m_axi_bvalid,
output wire [ 4-1:0] m_axi_bready, output wire [ 3:0] m_axi_bready,
output wire [ 4-1:0] m_axi_arid, output wire [ 3:0] m_axi_arid,
output wire [128-1:0] m_axi_araddr, output wire [ 127:0] m_axi_araddr,
output wire [ 32-1:0] m_axi_arlen, output wire [ 31:0] m_axi_arlen,
output wire [ 12-1:0] m_axi_arsize, output wire [ 11:0] m_axi_arsize,
output wire [ 8-1:0] m_axi_arburst, output wire [ 7:0] m_axi_arburst,
output wire [ 4-1:0] m_axi_arlock, output wire [ 3:0] m_axi_arlock,
output wire [ 16-1:0] m_axi_arcache, output wire [ 15:0] m_axi_arcache,
output wire [ 12-1:0] m_axi_arprot, output wire [ 11:0] m_axi_arprot,
output wire [ 16-1:0] m_axi_arqos, output wire [ 15:0] m_axi_arqos,
output wire [ 16-1:0] m_axi_arregion, output wire [ 15:0] m_axi_arregion,
output wire [ 4-1:0] m_axi_aruser, output wire [ 3:0] m_axi_aruser,
output wire [ 4-1:0] m_axi_arvalid, output wire [ 3:0] m_axi_arvalid,
input wire [ 4-1:0] m_axi_arready, input wire [ 3:0] m_axi_arready,
input wire [ 4-1:0] m_axi_rid, input wire [ 3:0] m_axi_rid,
input wire [256-1:0] m_axi_rdata, input wire [ 255:0] m_axi_rdata,
input wire [ 8-1:0] m_axi_rresp, input wire [ 7:0] m_axi_rresp,
input wire [ 4-1:0] m_axi_rlast, input wire [ 3:0] m_axi_rlast,
input wire [ 4-1:0] m_axi_ruser, input wire [ 3:0] m_axi_ruser,
input wire [ 4-1:0] m_axi_rvalid, input wire [ 3:0] m_axi_rvalid,
output wire [ 4-1:0] m_axi_rready, output wire [ 3:0] m_axi_rready,
// Transport 0 (eth0 1G)
input wire [64-1:0] s_eth0_tdata, // Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [64-1:0] m_eth0_tdata, output wire [CHDR_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1 10G) // Transport 1 (eth1)
input wire [64-1:0] s_eth1_tdata, input wire [CHDR_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [64-1:0] m_eth1_tdata, output wire [CHDR_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (dma dma) // Transport 2 (dma)
input wire [64-1:0] s_dma_tdata, input wire [CHDR_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [64-1:0] m_dma_tdata, output wire [CHDR_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam CHDR_W = 64;
localparam MTU = 10;
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// CHDR Crossbar // CHDR Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
@@ -240,9 +258,18 @@ module rfnoc_image_core #(
.ext_rtcfg_ack () .ext_rtcfg_ack ()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Stream Endpoints // Stream Endpoints
// ---------------------------------------------------- //---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
@@ -266,7 +293,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
@@ -305,6 +332,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 32768;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
@@ -327,7 +362,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
@@ -366,6 +401,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 32768;
localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
@@ -388,7 +431,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
@@ -427,6 +470,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 32768;
localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
@@ -449,7 +500,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
@@ -488,6 +539,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 4096;
localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
@@ -510,7 +569,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (4), .INST_NUM (4),
.CTRL_XBAR_PORT (5), .CTRL_XBAR_PORT (5),
.INGRESS_BUFF_SIZE (12), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
@@ -549,6 +608,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 4096;
localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
@@ -571,7 +638,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (5), .INST_NUM (5),
.CTRL_XBAR_PORT (6), .CTRL_XBAR_PORT (6),
.INGRESS_BUFF_SIZE (12), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
@@ -610,6 +677,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP6 = 4096;
localparam INGRESS_BUFF_SIZE_EP6 =
REQ_BUFF_SIZE_EP6 == 0 ? 5 :
REQ_BUFF_SIZE_EP6 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP6);
wire [CHDR_W-1:0] m_ep6_out0_tdata; wire [CHDR_W-1:0] m_ep6_out0_tdata;
wire m_ep6_out0_tlast; wire m_ep6_out0_tlast;
wire m_ep6_out0_tvalid; wire m_ep6_out0_tvalid;
@@ -632,7 +707,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (6), .INST_NUM (6),
.CTRL_XBAR_PORT (7), .CTRL_XBAR_PORT (7),
.INGRESS_BUFF_SIZE (12), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP6),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep6_i ( ) ep6_i (
@@ -671,6 +746,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP7 = 4096;
localparam INGRESS_BUFF_SIZE_EP7 =
REQ_BUFF_SIZE_EP7 == 0 ? 5 :
REQ_BUFF_SIZE_EP7 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP7);
wire [CHDR_W-1:0] m_ep7_out0_tdata; wire [CHDR_W-1:0] m_ep7_out0_tdata;
wire m_ep7_out0_tlast; wire m_ep7_out0_tlast;
wire m_ep7_out0_tvalid; wire m_ep7_out0_tvalid;
@@ -693,7 +776,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (7), .INST_NUM (7),
.CTRL_XBAR_PORT (8), .CTRL_XBAR_PORT (8),
.INGRESS_BUFF_SIZE (12), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP7),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep7_i ( ) ep7_i (
@@ -733,10 +816,9 @@ module rfnoc_image_core #(
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Control Crossbar // Control Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast; wire m_core_ctrl_tlast, s_core_ctrl_tlast;
@@ -793,9 +875,11 @@ module rfnoc_image_core #(
.deadlock_detected() .deadlock_detected()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// RFNoC Core Kernel // RFNoC Core Kernel
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status; wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #( rfnoc_core_kernel #(
@@ -833,13 +917,15 @@ module rfnoc_image_core #(
.rfnoc_core_status (rfnoc_core_status) .rfnoc_core_status (rfnoc_core_status)
); );
// ----------------------------------------------------
// Blocks
// ----------------------------------------------------
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// duc0 // duc0
// ---------------------------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ; wire [CHDR_W-1:0] s_duc0_in_1_tdata , s_duc0_in_0_tdata ;
wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ; wire s_duc0_in_1_tlast , s_duc0_in_0_tlast ;
@@ -850,7 +936,6 @@ module rfnoc_image_core #(
wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid; wire m_duc0_out_1_tvalid, m_duc0_out_0_tvalid;
wire m_duc0_out_1_tready, m_duc0_out_0_tready; wire m_duc0_out_1_tready, m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -864,8 +949,6 @@ module rfnoc_image_core #(
.ce_clk (duc0_ce_clk), .ce_clk (duc0_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_duc0_in_1_tdata , s_duc0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_duc0_in_1_tlast , s_duc0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_duc0_in_1_tvalid, s_duc0_in_0_tvalid}),
@@ -884,10 +967,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready) .m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// ddc0 // ddc0
// ---------------------------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
@@ -898,7 +981,6 @@ module rfnoc_image_core #(
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -912,8 +994,6 @@ module rfnoc_image_core #(
.ce_clk (ddc0_ce_clk), .ce_clk (ddc0_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
.s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}),
@@ -932,10 +1012,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready) .m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// radio0 // radio0
// ---------------------------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
@@ -947,25 +1027,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 1-1:0] radio0_m_ctrlport_req_rd; wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 20-1:0] radio0_m_ctrlport_req_addr; wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 32-1:0] radio0_m_ctrlport_req_data; wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio0_m_ctrlport_req_has_time; wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 64-1:0] radio0_m_ctrlport_req_time; wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 1-1:0] radio0_m_ctrlport_resp_ack; wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 2-1:0] radio0_m_ctrlport_resp_status; wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 32-1:0] radio0_m_ctrlport_resp_data; wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio0_radio_time; wire [ 63:0] radio0_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio0_radio_rx_data; wire [ 63:0] radio0_radio_rx_data;
wire [ 2-1:0] radio0_radio_rx_stb; wire [ 1:0] radio0_radio_rx_stb;
wire [ 2-1:0] radio0_radio_rx_running; wire [ 1:0] radio0_radio_rx_running;
wire [ 64-1:0] radio0_radio_tx_data; wire [ 63:0] radio0_radio_tx_data;
wire [ 2-1:0] radio0_radio_tx_stb; wire [ 1:0] radio0_radio_tx_stb;
wire [ 2-1:0] radio0_radio_tx_running; wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
@@ -978,7 +1058,6 @@ module rfnoc_image_core #(
.radio_clk (radio0_radio_clk), .radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]),
.rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
@@ -996,7 +1075,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio0_radio_tx_data), .radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb), .radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running), .radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
@@ -1015,10 +1093,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// duc1 // duc1
// ---------------------------------------------------- //-----------------------------------
wire duc1_ce_clk; wire duc1_ce_clk;
wire [CHDR_W-1:0] s_duc1_in_1_tdata , s_duc1_in_0_tdata ; wire [CHDR_W-1:0] s_duc1_in_1_tdata , s_duc1_in_0_tdata ;
wire s_duc1_in_1_tlast , s_duc1_in_0_tlast ; wire s_duc1_in_1_tlast , s_duc1_in_0_tlast ;
@@ -1029,7 +1107,6 @@ module rfnoc_image_core #(
wire m_duc1_out_1_tvalid, m_duc1_out_0_tvalid; wire m_duc1_out_1_tvalid, m_duc1_out_0_tvalid;
wire m_duc1_out_1_tready, m_duc1_out_0_tready; wire m_duc1_out_1_tready, m_duc1_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (5), .THIS_PORTID (5),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -1043,8 +1120,6 @@ module rfnoc_image_core #(
.ce_clk (duc1_ce_clk), .ce_clk (duc1_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]),
.rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]),
.s_rfnoc_chdr_tdata ({s_duc1_in_1_tdata , s_duc1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_duc1_in_1_tdata , s_duc1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_duc1_in_1_tlast , s_duc1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_duc1_in_1_tlast , s_duc1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_duc1_in_1_tvalid, s_duc1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_duc1_in_1_tvalid, s_duc1_in_0_tvalid}),
@@ -1063,10 +1138,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_duc1_ctrl_tready) .m_rfnoc_ctrl_tready (m_duc1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// ddc1 // ddc1
// ---------------------------------------------------- //-----------------------------------
wire ddc1_ce_clk; wire ddc1_ce_clk;
wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ;
wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ;
@@ -1077,7 +1152,6 @@ module rfnoc_image_core #(
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready; wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (6), .THIS_PORTID (6),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -1091,8 +1165,6 @@ module rfnoc_image_core #(
.ce_clk (ddc1_ce_clk), .ce_clk (ddc1_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]),
.rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]),
.s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}),
@@ -1111,10 +1183,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready) .m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// radio1 // radio1
// ---------------------------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
@@ -1126,25 +1198,25 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tready, m_radio1_out_0_tready; wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 1-1:0] radio1_m_ctrlport_req_rd; wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 20-1:0] radio1_m_ctrlport_req_addr; wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 32-1:0] radio1_m_ctrlport_req_data; wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio1_m_ctrlport_req_has_time; wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire [ 64-1:0] radio1_m_ctrlport_req_time; wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 1-1:0] radio1_m_ctrlport_resp_ack; wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 2-1:0] radio1_m_ctrlport_resp_status; wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 32-1:0] radio1_m_ctrlport_resp_data; wire [ 31:0] radio1_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio1_radio_time; wire [ 63:0] radio1_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio1_radio_rx_data; wire [ 63:0] radio1_radio_rx_data;
wire [ 2-1:0] radio1_radio_rx_stb; wire [ 1:0] radio1_radio_rx_stb;
wire [ 2-1:0] radio1_radio_rx_running; wire [ 1:0] radio1_radio_rx_running;
wire [ 64-1:0] radio1_radio_tx_data; wire [ 63:0] radio1_radio_tx_data;
wire [ 2-1:0] radio1_radio_tx_stb; wire [ 1:0] radio1_radio_tx_stb;
wire [ 2-1:0] radio1_radio_tx_running; wire [ 1:0] radio1_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (7), .THIS_PORTID (7),
@@ -1157,7 +1229,6 @@ module rfnoc_image_core #(
.radio_clk (radio1_radio_clk), .radio_clk (radio1_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]),
.rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]),
.m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr),
@@ -1175,7 +1246,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio1_radio_tx_data), .radio_tx_data (radio1_radio_tx_data),
.radio_tx_stb (radio1_radio_tx_stb), .radio_tx_stb (radio1_radio_tx_stb),
.radio_tx_running (radio1_radio_tx_running), .radio_tx_running (radio1_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}),
@@ -1194,10 +1264,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// replay0 // replay0
// ---------------------------------------------------- //-----------------------------------
wire replay0_mem_clk; wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire [CHDR_W-1:0] s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ; wire s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
@@ -1209,51 +1279,51 @@ module rfnoc_image_core #(
wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready; wire m_replay0_out_3_tready, m_replay0_out_2_tready, m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram // axi_ram
wire [ 1-1:0] replay0_axi_rst; wire [ 0:0] replay0_axi_rst;
wire [ 4-1:0] replay0_m_axi_awid; wire [ 3:0] replay0_m_axi_awid;
wire [128-1:0] replay0_m_axi_awaddr; wire [ 127:0] replay0_m_axi_awaddr;
wire [ 32-1:0] replay0_m_axi_awlen; wire [ 31:0] replay0_m_axi_awlen;
wire [ 12-1:0] replay0_m_axi_awsize; wire [ 11:0] replay0_m_axi_awsize;
wire [ 8-1:0] replay0_m_axi_awburst; wire [ 7:0] replay0_m_axi_awburst;
wire [ 4-1:0] replay0_m_axi_awlock; wire [ 3:0] replay0_m_axi_awlock;
wire [ 16-1:0] replay0_m_axi_awcache; wire [ 15:0] replay0_m_axi_awcache;
wire [ 12-1:0] replay0_m_axi_awprot; wire [ 11:0] replay0_m_axi_awprot;
wire [ 16-1:0] replay0_m_axi_awqos; wire [ 15:0] replay0_m_axi_awqos;
wire [ 16-1:0] replay0_m_axi_awregion; wire [ 15:0] replay0_m_axi_awregion;
wire [ 4-1:0] replay0_m_axi_awuser; wire [ 3:0] replay0_m_axi_awuser;
wire [ 4-1:0] replay0_m_axi_awvalid; wire [ 3:0] replay0_m_axi_awvalid;
wire [ 4-1:0] replay0_m_axi_awready; wire [ 3:0] replay0_m_axi_awready;
wire [256-1:0] replay0_m_axi_wdata; wire [ 255:0] replay0_m_axi_wdata;
wire [ 32-1:0] replay0_m_axi_wstrb; wire [ 31:0] replay0_m_axi_wstrb;
wire [ 4-1:0] replay0_m_axi_wlast; wire [ 3:0] replay0_m_axi_wlast;
wire [ 4-1:0] replay0_m_axi_wuser; wire [ 3:0] replay0_m_axi_wuser;
wire [ 4-1:0] replay0_m_axi_wvalid; wire [ 3:0] replay0_m_axi_wvalid;
wire [ 4-1:0] replay0_m_axi_wready; wire [ 3:0] replay0_m_axi_wready;
wire [ 4-1:0] replay0_m_axi_bid; wire [ 3:0] replay0_m_axi_bid;
wire [ 8-1:0] replay0_m_axi_bresp; wire [ 7:0] replay0_m_axi_bresp;
wire [ 4-1:0] replay0_m_axi_buser; wire [ 3:0] replay0_m_axi_buser;
wire [ 4-1:0] replay0_m_axi_bvalid; wire [ 3:0] replay0_m_axi_bvalid;
wire [ 4-1:0] replay0_m_axi_bready; wire [ 3:0] replay0_m_axi_bready;
wire [ 4-1:0] replay0_m_axi_arid; wire [ 3:0] replay0_m_axi_arid;
wire [128-1:0] replay0_m_axi_araddr; wire [ 127:0] replay0_m_axi_araddr;
wire [ 32-1:0] replay0_m_axi_arlen; wire [ 31:0] replay0_m_axi_arlen;
wire [ 12-1:0] replay0_m_axi_arsize; wire [ 11:0] replay0_m_axi_arsize;
wire [ 8-1:0] replay0_m_axi_arburst; wire [ 7:0] replay0_m_axi_arburst;
wire [ 4-1:0] replay0_m_axi_arlock; wire [ 3:0] replay0_m_axi_arlock;
wire [ 16-1:0] replay0_m_axi_arcache; wire [ 15:0] replay0_m_axi_arcache;
wire [ 12-1:0] replay0_m_axi_arprot; wire [ 11:0] replay0_m_axi_arprot;
wire [ 16-1:0] replay0_m_axi_arqos; wire [ 15:0] replay0_m_axi_arqos;
wire [ 16-1:0] replay0_m_axi_arregion; wire [ 15:0] replay0_m_axi_arregion;
wire [ 4-1:0] replay0_m_axi_aruser; wire [ 3:0] replay0_m_axi_aruser;
wire [ 4-1:0] replay0_m_axi_arvalid; wire [ 3:0] replay0_m_axi_arvalid;
wire [ 4-1:0] replay0_m_axi_arready; wire [ 3:0] replay0_m_axi_arready;
wire [ 4-1:0] replay0_m_axi_rid; wire [ 3:0] replay0_m_axi_rid;
wire [256-1:0] replay0_m_axi_rdata; wire [ 255:0] replay0_m_axi_rdata;
wire [ 8-1:0] replay0_m_axi_rresp; wire [ 7:0] replay0_m_axi_rresp;
wire [ 4-1:0] replay0_m_axi_rlast; wire [ 3:0] replay0_m_axi_rlast;
wire [ 4-1:0] replay0_m_axi_ruser; wire [ 3:0] replay0_m_axi_ruser;
wire [ 4-1:0] replay0_m_axi_rvalid; wire [ 3:0] replay0_m_axi_rvalid;
wire [ 4-1:0] replay0_m_axi_rready; wire [ 3:0] replay0_m_axi_rready;
rfnoc_block_replay #( rfnoc_block_replay #(
.THIS_PORTID (8), .THIS_PORTID (8),
@@ -1268,7 +1338,6 @@ module rfnoc_image_core #(
.mem_clk (replay0_mem_clk), .mem_clk (replay0_mem_clk),
.rfnoc_core_config (rfnoc_core_config[512*7-1:512*6]), .rfnoc_core_config (rfnoc_core_config[512*7-1:512*6]),
.rfnoc_core_status (rfnoc_core_status[512*7-1:512*6]), .rfnoc_core_status (rfnoc_core_status[512*7-1:512*6]),
.axi_rst (replay0_axi_rst), .axi_rst (replay0_axi_rst),
.m_axi_awid (replay0_m_axi_awid), .m_axi_awid (replay0_m_axi_awid),
.m_axi_awaddr (replay0_m_axi_awaddr), .m_axi_awaddr (replay0_m_axi_awaddr),
@@ -1314,7 +1383,6 @@ module rfnoc_image_core #(
.m_axi_ruser (replay0_m_axi_ruser), .m_axi_ruser (replay0_m_axi_ruser),
.m_axi_rvalid (replay0_m_axi_rvalid), .m_axi_rvalid (replay0_m_axi_rvalid),
.m_axi_rready (replay0_m_axi_rready), .m_axi_rready (replay0_m_axi_rready),
.s_rfnoc_chdr_tdata ({s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_replay0_in_3_tdata , s_replay0_in_2_tdata , s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_replay0_in_3_tlast , s_replay0_in_2_tlast , s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_replay0_in_3_tvalid, s_replay0_in_2_tvalid, s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
@@ -1333,10 +1401,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready) .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Static Router // Static Router
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_duc0_in_0_tdata = m_ep0_out0_tdata; assign s_duc0_in_0_tdata = m_ep0_out0_tdata;
assign s_duc0_in_0_tlast = m_ep0_out0_tlast; assign s_duc0_in_0_tlast = m_ep0_out0_tlast;
assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid;
@@ -1458,13 +1526,16 @@ module rfnoc_image_core #(
assign m_replay0_out_3_tready = s_ep7_in0_tready; assign m_replay0_out_3_tready = s_ep7_in0_tready;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Unused Ports // Unused Ports
// ---------------------------------------------------- //---------------------------------------------------------------------------
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains // Clock Domains
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk; assign radio0_radio_clk = radio_clk;
assign ddc0_ce_clk = rfnoc_chdr_clk; assign ddc0_ce_clk = rfnoc_chdr_clk;
assign duc0_ce_clk = rfnoc_chdr_clk; assign duc0_ce_clk = rfnoc_chdr_clk;
@@ -1474,9 +1545,10 @@ module rfnoc_image_core #(
assign replay0_mem_clk = dram_clk; assign replay0_mem_clk = dram_clk;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// IO Port Connection // IO Port Connection
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Master/Slave Connections: // Master/Slave Connections:
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
@@ -1566,3 +1638,6 @@ module rfnoc_image_core #(
assign radio1_radio_time = radio_time; assign radio1_radio_time = radio_time;
endmodule endmodule
`default_nettype wire
top/n3xx/n310_rfnoc_image_core.vh
+21
View File
@@ -0,0 +1,21 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n310)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:09.279594
// Source: n310_rfnoc_image_core.yml
// Source SHA256: cc561a3de48fea9e224425413802738d125393f55f6dd46e196db8fdabe09284
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/n3xx/n320_bist_image_core.v
+269 -214
View File
@@ -1,18 +1,31 @@
// //
// Copyright 2020 Ettus Research, A National Instruments Brand // Copyright 2021 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: rfnoc_image_core (for n320) // Module: rfnoc_image_core (for n320)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) //
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// File generated on: 2020-07-27T12:39:13.318449 //
// File generated on: 2021-05-03T08:51:06.226381
// Source: n320_bist_image_core.yml // Source: n320_bist_image_core.yml
// Source SHA256: b5d9a0fb5302f7bfadf36c9d6cdcc70814aa1062f82396378a2976faba6ba010 // Source SHA256: d384cf18372dd4b674466793e7cf30abeb4f3ef658d466be7007a9b7b8af7241
//
`default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0} parameter CHDR_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) ( ) (
// Clocks // Clocks
input wire chdr_aclk, input wire chdr_aclk,
@@ -22,130 +35,135 @@ module rfnoc_image_core #(
input wire dram_clk, input wire dram_clk,
// Basic // Basic
input wire [ 15:0] device_id, input wire [ 15:0] device_id,
//// IO ports //////////////////////////////////
// IO ports /////////////////////////
// ctrlport_radio0 // ctrlport_radio0
output wire [ 1-1:0] m_ctrlport_radio0_req_wr, output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 1-1:0] m_ctrlport_radio0_req_rd, output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire [ 20-1:0] m_ctrlport_radio0_req_addr, output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 32-1:0] m_ctrlport_radio0_req_data, output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio0_req_time, output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio0_resp_status, input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 32-1:0] m_ctrlport_radio0_resp_data, input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1 // ctrlport_radio1
output wire [ 1-1:0] m_ctrlport_radio1_req_wr, output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 1-1:0] m_ctrlport_radio1_req_rd, output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire [ 20-1:0] m_ctrlport_radio1_req_addr, output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 32-1:0] m_ctrlport_radio1_req_data, output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio1_req_time, output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio1_resp_status, input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 32-1:0] m_ctrlport_radio1_resp_data, input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time_keeper // time_keeper
input wire [ 64-1:0] radio_time, input wire [ 63:0] radio_time,
// radio_ch0 // radio_ch0
input wire [ 32-1:0] radio_rx_data_radio0, input wire [ 31:0] radio_rx_data_radio0,
input wire [ 1-1:0] radio_rx_stb_radio0, input wire [ 0:0] radio_rx_stb_radio0,
output wire [ 1-1:0] radio_rx_running_radio0, output wire [ 0:0] radio_rx_running_radio0,
output wire [ 32-1:0] radio_tx_data_radio0, output wire [ 31:0] radio_tx_data_radio0,
input wire [ 1-1:0] radio_tx_stb_radio0, input wire [ 0:0] radio_tx_stb_radio0,
output wire [ 1-1:0] radio_tx_running_radio0, output wire [ 0:0] radio_tx_running_radio0,
// radio_ch1 // radio_ch1
input wire [ 32-1:0] radio_rx_data_radio1, input wire [ 31:0] radio_rx_data_radio1,
input wire [ 1-1:0] radio_rx_stb_radio1, input wire [ 0:0] radio_rx_stb_radio1,
output wire [ 1-1:0] radio_rx_running_radio1, output wire [ 0:0] radio_rx_running_radio1,
output wire [ 32-1:0] radio_tx_data_radio1, output wire [ 31:0] radio_tx_data_radio1,
input wire [ 1-1:0] radio_tx_stb_radio1, input wire [ 0:0] radio_tx_stb_radio1,
output wire [ 1-1:0] radio_tx_running_radio1, output wire [ 0:0] radio_tx_running_radio1,
// dram // dram
input wire [ 1-1:0] axi_rst, input wire [ 0:0] axi_rst,
output wire [ 4-1:0] m_axi_awid, output wire [ 3:0] m_axi_awid,
output wire [128-1:0] m_axi_awaddr, output wire [ 127:0] m_axi_awaddr,
output wire [ 32-1:0] m_axi_awlen, output wire [ 31:0] m_axi_awlen,
output wire [ 12-1:0] m_axi_awsize, output wire [ 11:0] m_axi_awsize,
output wire [ 8-1:0] m_axi_awburst, output wire [ 7:0] m_axi_awburst,
output wire [ 4-1:0] m_axi_awlock, output wire [ 3:0] m_axi_awlock,
output wire [ 16-1:0] m_axi_awcache, output wire [ 15:0] m_axi_awcache,
output wire [ 12-1:0] m_axi_awprot, output wire [ 11:0] m_axi_awprot,
output wire [ 16-1:0] m_axi_awqos, output wire [ 15:0] m_axi_awqos,
output wire [ 16-1:0] m_axi_awregion, output wire [ 15:0] m_axi_awregion,
output wire [ 4-1:0] m_axi_awuser, output wire [ 3:0] m_axi_awuser,
output wire [ 4-1:0] m_axi_awvalid, output wire [ 3:0] m_axi_awvalid,
input wire [ 4-1:0] m_axi_awready, input wire [ 3:0] m_axi_awready,
output wire [256-1:0] m_axi_wdata, output wire [ 255:0] m_axi_wdata,
output wire [ 32-1:0] m_axi_wstrb, output wire [ 31:0] m_axi_wstrb,
output wire [ 4-1:0] m_axi_wlast, output wire [ 3:0] m_axi_wlast,
output wire [ 4-1:0] m_axi_wuser, output wire [ 3:0] m_axi_wuser,
output wire [ 4-1:0] m_axi_wvalid, output wire [ 3:0] m_axi_wvalid,
input wire [ 4-1:0] m_axi_wready, input wire [ 3:0] m_axi_wready,
input wire [ 4-1:0] m_axi_bid, input wire [ 3:0] m_axi_bid,
input wire [ 8-1:0] m_axi_bresp, input wire [ 7:0] m_axi_bresp,
input wire [ 4-1:0] m_axi_buser, input wire [ 3:0] m_axi_buser,
input wire [ 4-1:0] m_axi_bvalid, input wire [ 3:0] m_axi_bvalid,
output wire [ 4-1:0] m_axi_bready, output wire [ 3:0] m_axi_bready,
output wire [ 4-1:0] m_axi_arid, output wire [ 3:0] m_axi_arid,
output wire [128-1:0] m_axi_araddr, output wire [ 127:0] m_axi_araddr,
output wire [ 32-1:0] m_axi_arlen, output wire [ 31:0] m_axi_arlen,
output wire [ 12-1:0] m_axi_arsize, output wire [ 11:0] m_axi_arsize,
output wire [ 8-1:0] m_axi_arburst, output wire [ 7:0] m_axi_arburst,
output wire [ 4-1:0] m_axi_arlock, output wire [ 3:0] m_axi_arlock,
output wire [ 16-1:0] m_axi_arcache, output wire [ 15:0] m_axi_arcache,
output wire [ 12-1:0] m_axi_arprot, output wire [ 11:0] m_axi_arprot,
output wire [ 16-1:0] m_axi_arqos, output wire [ 15:0] m_axi_arqos,
output wire [ 16-1:0] m_axi_arregion, output wire [ 15:0] m_axi_arregion,
output wire [ 4-1:0] m_axi_aruser, output wire [ 3:0] m_axi_aruser,
output wire [ 4-1:0] m_axi_arvalid, output wire [ 3:0] m_axi_arvalid,
input wire [ 4-1:0] m_axi_arready, input wire [ 3:0] m_axi_arready,
input wire [ 4-1:0] m_axi_rid, input wire [ 3:0] m_axi_rid,
input wire [256-1:0] m_axi_rdata, input wire [ 255:0] m_axi_rdata,
input wire [ 8-1:0] m_axi_rresp, input wire [ 7:0] m_axi_rresp,
input wire [ 4-1:0] m_axi_rlast, input wire [ 3:0] m_axi_rlast,
input wire [ 4-1:0] m_axi_ruser, input wire [ 3:0] m_axi_ruser,
input wire [ 4-1:0] m_axi_rvalid, input wire [ 3:0] m_axi_rvalid,
output wire [ 4-1:0] m_axi_rready, output wire [ 3:0] m_axi_rready,
// Transport 0 (eth0 1G)
input wire [64-1:0] s_eth0_tdata, // Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [64-1:0] m_eth0_tdata, output wire [CHDR_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1 10G) // Transport 1 (eth1)
input wire [64-1:0] s_eth1_tdata, input wire [CHDR_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [64-1:0] m_eth1_tdata, output wire [CHDR_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (dma dma) // Transport 2 (dma)
input wire [64-1:0] s_dma_tdata, input wire [CHDR_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [64-1:0] m_dma_tdata, output wire [CHDR_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam CHDR_W = 64;
localparam MTU = 10;
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// CHDR Crossbar // CHDR Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
@@ -208,9 +226,18 @@ module rfnoc_image_core #(
.ext_rtcfg_ack () .ext_rtcfg_ack ()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Stream Endpoints // Stream Endpoints
// ---------------------------------------------------- //---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
@@ -234,7 +261,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
@@ -273,6 +300,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 32768;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
@@ -295,7 +330,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
@@ -334,6 +369,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 32768;
localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
@@ -356,7 +399,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
@@ -395,6 +438,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 32768;
localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
@@ -417,7 +468,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
@@ -457,10 +508,9 @@ module rfnoc_image_core #(
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Control Crossbar // Control Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast; wire m_core_ctrl_tlast, s_core_ctrl_tlast;
@@ -501,9 +551,11 @@ module rfnoc_image_core #(
.deadlock_detected() .deadlock_detected()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// RFNoC Core Kernel // RFNoC Core Kernel
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status; wire [(512*3)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #( rfnoc_core_kernel #(
@@ -541,13 +593,15 @@ module rfnoc_image_core #(
.rfnoc_core_status (rfnoc_core_status) .rfnoc_core_status (rfnoc_core_status)
); );
// ----------------------------------------------------
// Blocks
// ----------------------------------------------------
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// radio0 // radio0
// ---------------------------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_0_tdata ; wire [CHDR_W-1:0] s_radio0_in_0_tdata ;
wire s_radio0_in_0_tlast ; wire s_radio0_in_0_tlast ;
@@ -559,25 +613,25 @@ module rfnoc_image_core #(
wire m_radio0_out_0_tready; wire m_radio0_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 1-1:0] radio0_m_ctrlport_req_rd; wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 20-1:0] radio0_m_ctrlport_req_addr; wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 32-1:0] radio0_m_ctrlport_req_data; wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio0_m_ctrlport_req_has_time; wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 64-1:0] radio0_m_ctrlport_req_time; wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 1-1:0] radio0_m_ctrlport_resp_ack; wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 2-1:0] radio0_m_ctrlport_resp_status; wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 32-1:0] radio0_m_ctrlport_resp_data; wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio0_radio_time; wire [ 63:0] radio0_radio_time;
// radio_iface // radio_iface
wire [ 32-1:0] radio0_radio_rx_data; wire [ 31:0] radio0_radio_rx_data;
wire [ 1-1:0] radio0_radio_rx_stb; wire [ 0:0] radio0_radio_rx_stb;
wire [ 1-1:0] radio0_radio_rx_running; wire [ 0:0] radio0_radio_rx_running;
wire [ 32-1:0] radio0_radio_tx_data; wire [ 31:0] radio0_radio_tx_data;
wire [ 1-1:0] radio0_radio_tx_stb; wire [ 0:0] radio0_radio_tx_stb;
wire [ 1-1:0] radio0_radio_tx_running; wire [ 0:0] radio0_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (2), .THIS_PORTID (2),
@@ -590,7 +644,6 @@ module rfnoc_image_core #(
.radio_clk (radio0_radio_clk), .radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
@@ -608,7 +661,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio0_radio_tx_data), .radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb), .radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running), .radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio0_in_0_tvalid}),
@@ -627,10 +679,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// radio1 // radio1
// ---------------------------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_0_tdata ; wire [CHDR_W-1:0] s_radio1_in_0_tdata ;
wire s_radio1_in_0_tlast ; wire s_radio1_in_0_tlast ;
@@ -642,25 +694,25 @@ module rfnoc_image_core #(
wire m_radio1_out_0_tready; wire m_radio1_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 1-1:0] radio1_m_ctrlport_req_rd; wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 20-1:0] radio1_m_ctrlport_req_addr; wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 32-1:0] radio1_m_ctrlport_req_data; wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio1_m_ctrlport_req_has_time; wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire [ 64-1:0] radio1_m_ctrlport_req_time; wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 1-1:0] radio1_m_ctrlport_resp_ack; wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 2-1:0] radio1_m_ctrlport_resp_status; wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 32-1:0] radio1_m_ctrlport_resp_data; wire [ 31:0] radio1_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio1_radio_time; wire [ 63:0] radio1_radio_time;
// radio_iface // radio_iface
wire [ 32-1:0] radio1_radio_rx_data; wire [ 31:0] radio1_radio_rx_data;
wire [ 1-1:0] radio1_radio_rx_stb; wire [ 0:0] radio1_radio_rx_stb;
wire [ 1-1:0] radio1_radio_rx_running; wire [ 0:0] radio1_radio_rx_running;
wire [ 32-1:0] radio1_radio_tx_data; wire [ 31:0] radio1_radio_tx_data;
wire [ 1-1:0] radio1_radio_tx_stb; wire [ 0:0] radio1_radio_tx_stb;
wire [ 1-1:0] radio1_radio_tx_running; wire [ 0:0] radio1_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (3), .THIS_PORTID (3),
@@ -673,7 +725,6 @@ module rfnoc_image_core #(
.radio_clk (radio1_radio_clk), .radio_clk (radio1_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
.m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr),
@@ -691,7 +742,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio1_radio_tx_data), .radio_tx_data (radio1_radio_tx_data),
.radio_tx_stb (radio1_radio_tx_stb), .radio_tx_stb (radio1_radio_tx_stb),
.radio_tx_running (radio1_radio_tx_running), .radio_tx_running (radio1_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio1_in_0_tvalid}),
@@ -710,10 +760,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// fifo0 // fifo0
// ---------------------------------------------------- //-----------------------------------
wire fifo0_mem_clk; wire fifo0_mem_clk;
wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ; wire [CHDR_W-1:0] s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata ;
wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ; wire s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast ;
@@ -725,51 +775,51 @@ module rfnoc_image_core #(
wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready; wire m_fifo0_out_3_tready, m_fifo0_out_2_tready, m_fifo0_out_1_tready, m_fifo0_out_0_tready;
// axi_ram // axi_ram
wire [ 1-1:0] fifo0_axi_rst; wire [ 0:0] fifo0_axi_rst;
wire [ 4-1:0] fifo0_m_axi_awid; wire [ 3:0] fifo0_m_axi_awid;
wire [128-1:0] fifo0_m_axi_awaddr; wire [ 127:0] fifo0_m_axi_awaddr;
wire [ 32-1:0] fifo0_m_axi_awlen; wire [ 31:0] fifo0_m_axi_awlen;
wire [ 12-1:0] fifo0_m_axi_awsize; wire [ 11:0] fifo0_m_axi_awsize;
wire [ 8-1:0] fifo0_m_axi_awburst; wire [ 7:0] fifo0_m_axi_awburst;
wire [ 4-1:0] fifo0_m_axi_awlock; wire [ 3:0] fifo0_m_axi_awlock;
wire [ 16-1:0] fifo0_m_axi_awcache; wire [ 15:0] fifo0_m_axi_awcache;
wire [ 12-1:0] fifo0_m_axi_awprot; wire [ 11:0] fifo0_m_axi_awprot;
wire [ 16-1:0] fifo0_m_axi_awqos; wire [ 15:0] fifo0_m_axi_awqos;
wire [ 16-1:0] fifo0_m_axi_awregion; wire [ 15:0] fifo0_m_axi_awregion;
wire [ 4-1:0] fifo0_m_axi_awuser; wire [ 3:0] fifo0_m_axi_awuser;
wire [ 4-1:0] fifo0_m_axi_awvalid; wire [ 3:0] fifo0_m_axi_awvalid;
wire [ 4-1:0] fifo0_m_axi_awready; wire [ 3:0] fifo0_m_axi_awready;
wire [256-1:0] fifo0_m_axi_wdata; wire [ 255:0] fifo0_m_axi_wdata;
wire [ 32-1:0] fifo0_m_axi_wstrb; wire [ 31:0] fifo0_m_axi_wstrb;
wire [ 4-1:0] fifo0_m_axi_wlast; wire [ 3:0] fifo0_m_axi_wlast;
wire [ 4-1:0] fifo0_m_axi_wuser; wire [ 3:0] fifo0_m_axi_wuser;
wire [ 4-1:0] fifo0_m_axi_wvalid; wire [ 3:0] fifo0_m_axi_wvalid;
wire [ 4-1:0] fifo0_m_axi_wready; wire [ 3:0] fifo0_m_axi_wready;
wire [ 4-1:0] fifo0_m_axi_bid; wire [ 3:0] fifo0_m_axi_bid;
wire [ 8-1:0] fifo0_m_axi_bresp; wire [ 7:0] fifo0_m_axi_bresp;
wire [ 4-1:0] fifo0_m_axi_buser; wire [ 3:0] fifo0_m_axi_buser;
wire [ 4-1:0] fifo0_m_axi_bvalid; wire [ 3:0] fifo0_m_axi_bvalid;
wire [ 4-1:0] fifo0_m_axi_bready; wire [ 3:0] fifo0_m_axi_bready;
wire [ 4-1:0] fifo0_m_axi_arid; wire [ 3:0] fifo0_m_axi_arid;
wire [128-1:0] fifo0_m_axi_araddr; wire [ 127:0] fifo0_m_axi_araddr;
wire [ 32-1:0] fifo0_m_axi_arlen; wire [ 31:0] fifo0_m_axi_arlen;
wire [ 12-1:0] fifo0_m_axi_arsize; wire [ 11:0] fifo0_m_axi_arsize;
wire [ 8-1:0] fifo0_m_axi_arburst; wire [ 7:0] fifo0_m_axi_arburst;
wire [ 4-1:0] fifo0_m_axi_arlock; wire [ 3:0] fifo0_m_axi_arlock;
wire [ 16-1:0] fifo0_m_axi_arcache; wire [ 15:0] fifo0_m_axi_arcache;
wire [ 12-1:0] fifo0_m_axi_arprot; wire [ 11:0] fifo0_m_axi_arprot;
wire [ 16-1:0] fifo0_m_axi_arqos; wire [ 15:0] fifo0_m_axi_arqos;
wire [ 16-1:0] fifo0_m_axi_arregion; wire [ 15:0] fifo0_m_axi_arregion;
wire [ 4-1:0] fifo0_m_axi_aruser; wire [ 3:0] fifo0_m_axi_aruser;
wire [ 4-1:0] fifo0_m_axi_arvalid; wire [ 3:0] fifo0_m_axi_arvalid;
wire [ 4-1:0] fifo0_m_axi_arready; wire [ 3:0] fifo0_m_axi_arready;
wire [ 4-1:0] fifo0_m_axi_rid; wire [ 3:0] fifo0_m_axi_rid;
wire [256-1:0] fifo0_m_axi_rdata; wire [ 255:0] fifo0_m_axi_rdata;
wire [ 8-1:0] fifo0_m_axi_rresp; wire [ 7:0] fifo0_m_axi_rresp;
wire [ 4-1:0] fifo0_m_axi_rlast; wire [ 3:0] fifo0_m_axi_rlast;
wire [ 4-1:0] fifo0_m_axi_ruser; wire [ 3:0] fifo0_m_axi_ruser;
wire [ 4-1:0] fifo0_m_axi_rvalid; wire [ 3:0] fifo0_m_axi_rvalid;
wire [ 4-1:0] fifo0_m_axi_rready; wire [ 3:0] fifo0_m_axi_rready;
rfnoc_block_axi_ram_fifo #( rfnoc_block_axi_ram_fifo #(
.THIS_PORTID (4), .THIS_PORTID (4),
@@ -787,7 +837,6 @@ module rfnoc_image_core #(
.mem_clk (fifo0_mem_clk), .mem_clk (fifo0_mem_clk),
.rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]),
.rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]),
.axi_rst (fifo0_axi_rst), .axi_rst (fifo0_axi_rst),
.m_axi_awid (fifo0_m_axi_awid), .m_axi_awid (fifo0_m_axi_awid),
.m_axi_awaddr (fifo0_m_axi_awaddr), .m_axi_awaddr (fifo0_m_axi_awaddr),
@@ -833,7 +882,6 @@ module rfnoc_image_core #(
.m_axi_ruser (fifo0_m_axi_ruser), .m_axi_ruser (fifo0_m_axi_ruser),
.m_axi_rvalid (fifo0_m_axi_rvalid), .m_axi_rvalid (fifo0_m_axi_rvalid),
.m_axi_rready (fifo0_m_axi_rready), .m_axi_rready (fifo0_m_axi_rready),
.s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_fifo0_in_3_tdata , s_fifo0_in_2_tdata , s_fifo0_in_1_tdata , s_fifo0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_fifo0_in_3_tlast , s_fifo0_in_2_tlast , s_fifo0_in_1_tlast , s_fifo0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_fifo0_in_3_tvalid, s_fifo0_in_2_tvalid, s_fifo0_in_1_tvalid, s_fifo0_in_0_tvalid}),
@@ -852,10 +900,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready) .m_rfnoc_ctrl_tready (m_fifo0_ctrl_tready)
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Static Router // Static Router
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_radio0_in_0_tdata = m_ep0_out0_tdata; assign s_radio0_in_0_tdata = m_ep0_out0_tdata;
assign s_radio0_in_0_tlast = m_ep0_out0_tlast; assign s_radio0_in_0_tlast = m_ep0_out0_tlast;
assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid; assign s_radio0_in_0_tvalid = m_ep0_out0_tvalid;
@@ -897,9 +945,10 @@ module rfnoc_image_core #(
assign m_fifo0_out_1_tready = s_ep5_in0_tready; assign m_fifo0_out_1_tready = s_ep5_in0_tready;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Unused Ports // Unused Ports
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}}; assign s_fifo0_in_2_tdata = {CHDR_W{1'b0}};
assign s_fifo0_in_2_tlast = 1'b0; assign s_fifo0_in_2_tlast = 1'b0;
assign s_fifo0_in_2_tvalid = 1'b0; assign s_fifo0_in_2_tvalid = 1'b0;
@@ -909,17 +958,20 @@ module rfnoc_image_core #(
assign m_fifo0_out_2_tready = 1'b1; assign m_fifo0_out_2_tready = 1'b1;
assign m_fifo0_out_3_tready = 1'b1; assign m_fifo0_out_3_tready = 1'b1;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains // Clock Domains
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk; assign radio0_radio_clk = radio_clk;
assign radio1_radio_clk = radio_clk; assign radio1_radio_clk = radio_clk;
assign fifo0_mem_clk = dram_clk; assign fifo0_mem_clk = dram_clk;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// IO Port Connection // IO Port Connection
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Master/Slave Connections: // Master/Slave Connections:
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
@@ -1009,3 +1061,6 @@ module rfnoc_image_core #(
assign radio1_radio_time = radio_time; assign radio1_radio_time = radio_time;
endmodule endmodule
`default_nettype wire
top/n3xx/n320_rfnoc_image_core.v
+282 -239
View File
@@ -1,18 +1,31 @@
// //
// Copyright 2020 Ettus Research, A National Instruments Brand // Copyright 2021 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: rfnoc_image_core (for n320) // Module: rfnoc_image_core (for n320)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) //
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// File generated on: 2020-09-02T12:03:04.264797 //
// Source: ./n320_rfnoc_image_core.yml // File generated on: 2021-05-03T08:51:09.950905
// Source SHA256: a059eb9043ce1c034abc0a0db7daad88a5e584207994c53030a98b3bea1bce39 // Source: n320_rfnoc_image_core.yml
// Source SHA256: 3c3a33be8bc2e3b3a7268ba3e07001c6dc6c21af4c9027309a787ac8404e5e8f
//
`default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0} parameter CHDR_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) ( ) (
// Clocks // Clocks
input wire chdr_aclk, input wire chdr_aclk,
@@ -22,130 +35,135 @@ module rfnoc_image_core #(
input wire dram_clk, input wire dram_clk,
// Basic // Basic
input wire [ 15:0] device_id, input wire [ 15:0] device_id,
//// IO ports //////////////////////////////////
// IO ports /////////////////////////
// ctrlport_radio0 // ctrlport_radio0
output wire [ 1-1:0] m_ctrlport_radio0_req_wr, output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 1-1:0] m_ctrlport_radio0_req_rd, output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire [ 20-1:0] m_ctrlport_radio0_req_addr, output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 32-1:0] m_ctrlport_radio0_req_data, output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio0_req_time, output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio0_resp_status, input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 32-1:0] m_ctrlport_radio0_resp_data, input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1 // ctrlport_radio1
output wire [ 1-1:0] m_ctrlport_radio1_req_wr, output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 1-1:0] m_ctrlport_radio1_req_rd, output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire [ 20-1:0] m_ctrlport_radio1_req_addr, output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 32-1:0] m_ctrlport_radio1_req_data, output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio1_req_time, output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio1_resp_status, input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 32-1:0] m_ctrlport_radio1_resp_data, input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time_keeper // time_keeper
input wire [ 64-1:0] radio_time, input wire [ 63:0] radio_time,
// radio_ch0 // radio_ch0
input wire [ 32-1:0] radio_rx_data_radio0, input wire [ 31:0] radio_rx_data_radio0,
input wire [ 1-1:0] radio_rx_stb_radio0, input wire [ 0:0] radio_rx_stb_radio0,
output wire [ 1-1:0] radio_rx_running_radio0, output wire [ 0:0] radio_rx_running_radio0,
output wire [ 32-1:0] radio_tx_data_radio0, output wire [ 31:0] radio_tx_data_radio0,
input wire [ 1-1:0] radio_tx_stb_radio0, input wire [ 0:0] radio_tx_stb_radio0,
output wire [ 1-1:0] radio_tx_running_radio0, output wire [ 0:0] radio_tx_running_radio0,
// radio_ch1 // radio_ch1
input wire [ 32-1:0] radio_rx_data_radio1, input wire [ 31:0] radio_rx_data_radio1,
input wire [ 1-1:0] radio_rx_stb_radio1, input wire [ 0:0] radio_rx_stb_radio1,
output wire [ 1-1:0] radio_rx_running_radio1, output wire [ 0:0] radio_rx_running_radio1,
output wire [ 32-1:0] radio_tx_data_radio1, output wire [ 31:0] radio_tx_data_radio1,
input wire [ 1-1:0] radio_tx_stb_radio1, input wire [ 0:0] radio_tx_stb_radio1,
output wire [ 1-1:0] radio_tx_running_radio1, output wire [ 0:0] radio_tx_running_radio1,
// dram // dram
input wire [ 1-1:0] axi_rst, input wire [ 0:0] axi_rst,
output wire [ 4-1:0] m_axi_awid, output wire [ 3:0] m_axi_awid,
output wire [128-1:0] m_axi_awaddr, output wire [ 127:0] m_axi_awaddr,
output wire [ 32-1:0] m_axi_awlen, output wire [ 31:0] m_axi_awlen,
output wire [ 12-1:0] m_axi_awsize, output wire [ 11:0] m_axi_awsize,
output wire [ 8-1:0] m_axi_awburst, output wire [ 7:0] m_axi_awburst,
output wire [ 4-1:0] m_axi_awlock, output wire [ 3:0] m_axi_awlock,
output wire [ 16-1:0] m_axi_awcache, output wire [ 15:0] m_axi_awcache,
output wire [ 12-1:0] m_axi_awprot, output wire [ 11:0] m_axi_awprot,
output wire [ 16-1:0] m_axi_awqos, output wire [ 15:0] m_axi_awqos,
output wire [ 16-1:0] m_axi_awregion, output wire [ 15:0] m_axi_awregion,
output wire [ 4-1:0] m_axi_awuser, output wire [ 3:0] m_axi_awuser,
output wire [ 4-1:0] m_axi_awvalid, output wire [ 3:0] m_axi_awvalid,
input wire [ 4-1:0] m_axi_awready, input wire [ 3:0] m_axi_awready,
output wire [256-1:0] m_axi_wdata, output wire [ 255:0] m_axi_wdata,
output wire [ 32-1:0] m_axi_wstrb, output wire [ 31:0] m_axi_wstrb,
output wire [ 4-1:0] m_axi_wlast, output wire [ 3:0] m_axi_wlast,
output wire [ 4-1:0] m_axi_wuser, output wire [ 3:0] m_axi_wuser,
output wire [ 4-1:0] m_axi_wvalid, output wire [ 3:0] m_axi_wvalid,
input wire [ 4-1:0] m_axi_wready, input wire [ 3:0] m_axi_wready,
input wire [ 4-1:0] m_axi_bid, input wire [ 3:0] m_axi_bid,
input wire [ 8-1:0] m_axi_bresp, input wire [ 7:0] m_axi_bresp,
input wire [ 4-1:0] m_axi_buser, input wire [ 3:0] m_axi_buser,
input wire [ 4-1:0] m_axi_bvalid, input wire [ 3:0] m_axi_bvalid,
output wire [ 4-1:0] m_axi_bready, output wire [ 3:0] m_axi_bready,
output wire [ 4-1:0] m_axi_arid, output wire [ 3:0] m_axi_arid,
output wire [128-1:0] m_axi_araddr, output wire [ 127:0] m_axi_araddr,
output wire [ 32-1:0] m_axi_arlen, output wire [ 31:0] m_axi_arlen,
output wire [ 12-1:0] m_axi_arsize, output wire [ 11:0] m_axi_arsize,
output wire [ 8-1:0] m_axi_arburst, output wire [ 7:0] m_axi_arburst,
output wire [ 4-1:0] m_axi_arlock, output wire [ 3:0] m_axi_arlock,
output wire [ 16-1:0] m_axi_arcache, output wire [ 15:0] m_axi_arcache,
output wire [ 12-1:0] m_axi_arprot, output wire [ 11:0] m_axi_arprot,
output wire [ 16-1:0] m_axi_arqos, output wire [ 15:0] m_axi_arqos,
output wire [ 16-1:0] m_axi_arregion, output wire [ 15:0] m_axi_arregion,
output wire [ 4-1:0] m_axi_aruser, output wire [ 3:0] m_axi_aruser,
output wire [ 4-1:0] m_axi_arvalid, output wire [ 3:0] m_axi_arvalid,
input wire [ 4-1:0] m_axi_arready, input wire [ 3:0] m_axi_arready,
input wire [ 4-1:0] m_axi_rid, input wire [ 3:0] m_axi_rid,
input wire [256-1:0] m_axi_rdata, input wire [ 255:0] m_axi_rdata,
input wire [ 8-1:0] m_axi_rresp, input wire [ 7:0] m_axi_rresp,
input wire [ 4-1:0] m_axi_rlast, input wire [ 3:0] m_axi_rlast,
input wire [ 4-1:0] m_axi_ruser, input wire [ 3:0] m_axi_ruser,
input wire [ 4-1:0] m_axi_rvalid, input wire [ 3:0] m_axi_rvalid,
output wire [ 4-1:0] m_axi_rready, output wire [ 3:0] m_axi_rready,
// Transport 0 (eth0 1G)
input wire [64-1:0] s_eth0_tdata, // Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [64-1:0] m_eth0_tdata, output wire [CHDR_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1 10G) // Transport 1 (eth1)
input wire [64-1:0] s_eth1_tdata, input wire [CHDR_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [64-1:0] m_eth1_tdata, output wire [CHDR_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (dma dma) // Transport 2 (dma)
input wire [64-1:0] s_dma_tdata, input wire [CHDR_W-1:0] s_dma_tdata,
input wire s_dma_tlast, input wire s_dma_tlast,
input wire s_dma_tvalid, input wire s_dma_tvalid,
output wire s_dma_tready, output wire s_dma_tready,
output wire [64-1:0] m_dma_tdata, output wire [CHDR_W-1:0] m_dma_tdata,
output wire m_dma_tlast, output wire m_dma_tlast,
output wire m_dma_tvalid, output wire m_dma_tvalid,
input wire m_dma_tready input wire m_dma_tready
); );
localparam CHDR_W = 64;
localparam MTU = 10;
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// CHDR Crossbar // CHDR Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
@@ -208,9 +226,18 @@ module rfnoc_image_core #(
.ext_rtcfg_ack () .ext_rtcfg_ack ()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Stream Endpoints // Stream Endpoints
// ---------------------------------------------------- //---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 65536;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
@@ -234,7 +261,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (16), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
@@ -273,6 +300,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 65536;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
@@ -295,7 +330,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (16), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
@@ -334,6 +369,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 4096;
localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
@@ -356,7 +399,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (12), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
@@ -395,6 +438,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 4096;
localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
@@ -417,7 +468,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (12), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
@@ -457,10 +508,9 @@ module rfnoc_image_core #(
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Control Crossbar // Control Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast; wire m_core_ctrl_tlast, s_core_ctrl_tlast;
@@ -517,9 +567,11 @@ module rfnoc_image_core #(
.deadlock_detected() .deadlock_detected()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// RFNoC Core Kernel // RFNoC Core Kernel
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status; wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #( rfnoc_core_kernel #(
@@ -557,13 +609,15 @@ module rfnoc_image_core #(
.rfnoc_core_status (rfnoc_core_status) .rfnoc_core_status (rfnoc_core_status)
); );
// ----------------------------------------------------
// Blocks
// ----------------------------------------------------
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// duc0 // duc0
// ---------------------------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_0_tdata ; wire [CHDR_W-1:0] s_duc0_in_0_tdata ;
wire s_duc0_in_0_tlast ; wire s_duc0_in_0_tlast ;
@@ -574,7 +628,6 @@ module rfnoc_image_core #(
wire m_duc0_out_0_tvalid; wire m_duc0_out_0_tvalid;
wire m_duc0_out_0_tready; wire m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -588,8 +641,6 @@ module rfnoc_image_core #(
.ce_clk (duc0_ce_clk), .ce_clk (duc0_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.s_rfnoc_chdr_tdata ({s_duc0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_duc0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_duc0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_duc0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_duc0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_duc0_in_0_tvalid}),
@@ -608,10 +659,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready) .m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// ddc0 // ddc0
// ---------------------------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_0_tdata ; wire [CHDR_W-1:0] s_ddc0_in_0_tdata ;
wire s_ddc0_in_0_tlast ; wire s_ddc0_in_0_tlast ;
@@ -622,7 +673,6 @@ module rfnoc_image_core #(
wire m_ddc0_out_0_tvalid; wire m_ddc0_out_0_tvalid;
wire m_ddc0_out_0_tready; wire m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -636,8 +686,6 @@ module rfnoc_image_core #(
.ce_clk (ddc0_ce_clk), .ce_clk (ddc0_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
.s_rfnoc_chdr_tdata ({s_ddc0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_ddc0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_ddc0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_ddc0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_ddc0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_ddc0_in_0_tvalid}),
@@ -656,10 +704,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready) .m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// radio0 // radio0
// ---------------------------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_0_tdata ; wire [CHDR_W-1:0] s_radio0_in_0_tdata ;
wire s_radio0_in_0_tlast ; wire s_radio0_in_0_tlast ;
@@ -671,25 +719,25 @@ module rfnoc_image_core #(
wire m_radio0_out_0_tready; wire m_radio0_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 1-1:0] radio0_m_ctrlport_req_rd; wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 20-1:0] radio0_m_ctrlport_req_addr; wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 32-1:0] radio0_m_ctrlport_req_data; wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio0_m_ctrlport_req_has_time; wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 64-1:0] radio0_m_ctrlport_req_time; wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 1-1:0] radio0_m_ctrlport_resp_ack; wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 2-1:0] radio0_m_ctrlport_resp_status; wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 32-1:0] radio0_m_ctrlport_resp_data; wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio0_radio_time; wire [ 63:0] radio0_radio_time;
// radio_iface // radio_iface
wire [ 32-1:0] radio0_radio_rx_data; wire [ 31:0] radio0_radio_rx_data;
wire [ 1-1:0] radio0_radio_rx_stb; wire [ 0:0] radio0_radio_rx_stb;
wire [ 1-1:0] radio0_radio_rx_running; wire [ 0:0] radio0_radio_rx_running;
wire [ 32-1:0] radio0_radio_tx_data; wire [ 31:0] radio0_radio_tx_data;
wire [ 1-1:0] radio0_radio_tx_stb; wire [ 0:0] radio0_radio_tx_stb;
wire [ 1-1:0] radio0_radio_tx_running; wire [ 0:0] radio0_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
@@ -702,7 +750,6 @@ module rfnoc_image_core #(
.radio_clk (radio0_radio_clk), .radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]),
.rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
@@ -720,7 +767,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio0_radio_tx_data), .radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb), .radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running), .radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio0_in_0_tvalid}),
@@ -739,10 +785,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// duc1 // duc1
// ---------------------------------------------------- //-----------------------------------
wire duc1_ce_clk; wire duc1_ce_clk;
wire [CHDR_W-1:0] s_duc1_in_0_tdata ; wire [CHDR_W-1:0] s_duc1_in_0_tdata ;
wire s_duc1_in_0_tlast ; wire s_duc1_in_0_tlast ;
@@ -753,7 +799,6 @@ module rfnoc_image_core #(
wire m_duc1_out_0_tvalid; wire m_duc1_out_0_tvalid;
wire m_duc1_out_0_tready; wire m_duc1_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (5), .THIS_PORTID (5),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -767,8 +812,6 @@ module rfnoc_image_core #(
.ce_clk (duc1_ce_clk), .ce_clk (duc1_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]),
.rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]),
.s_rfnoc_chdr_tdata ({s_duc1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_duc1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_duc1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_duc1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_duc1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_duc1_in_0_tvalid}),
@@ -787,10 +830,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_duc1_ctrl_tready) .m_rfnoc_ctrl_tready (m_duc1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// ddc1 // ddc1
// ---------------------------------------------------- //-----------------------------------
wire ddc1_ce_clk; wire ddc1_ce_clk;
wire [CHDR_W-1:0] s_ddc1_in_0_tdata ; wire [CHDR_W-1:0] s_ddc1_in_0_tdata ;
wire s_ddc1_in_0_tlast ; wire s_ddc1_in_0_tlast ;
@@ -801,7 +844,6 @@ module rfnoc_image_core #(
wire m_ddc1_out_0_tvalid; wire m_ddc1_out_0_tvalid;
wire m_ddc1_out_0_tready; wire m_ddc1_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (6), .THIS_PORTID (6),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -815,8 +857,6 @@ module rfnoc_image_core #(
.ce_clk (ddc1_ce_clk), .ce_clk (ddc1_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]),
.rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]),
.s_rfnoc_chdr_tdata ({s_ddc1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_ddc1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_ddc1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_ddc1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_ddc1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_ddc1_in_0_tvalid}),
@@ -835,10 +875,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready) .m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// radio1 // radio1
// ---------------------------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_0_tdata ; wire [CHDR_W-1:0] s_radio1_in_0_tdata ;
wire s_radio1_in_0_tlast ; wire s_radio1_in_0_tlast ;
@@ -850,25 +890,25 @@ module rfnoc_image_core #(
wire m_radio1_out_0_tready; wire m_radio1_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 1-1:0] radio1_m_ctrlport_req_rd; wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 20-1:0] radio1_m_ctrlport_req_addr; wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 32-1:0] radio1_m_ctrlport_req_data; wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio1_m_ctrlport_req_has_time; wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire [ 64-1:0] radio1_m_ctrlport_req_time; wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 1-1:0] radio1_m_ctrlport_resp_ack; wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 2-1:0] radio1_m_ctrlport_resp_status; wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 32-1:0] radio1_m_ctrlport_resp_data; wire [ 31:0] radio1_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio1_radio_time; wire [ 63:0] radio1_radio_time;
// radio_iface // radio_iface
wire [ 32-1:0] radio1_radio_rx_data; wire [ 31:0] radio1_radio_rx_data;
wire [ 1-1:0] radio1_radio_rx_stb; wire [ 0:0] radio1_radio_rx_stb;
wire [ 1-1:0] radio1_radio_rx_running; wire [ 0:0] radio1_radio_rx_running;
wire [ 32-1:0] radio1_radio_tx_data; wire [ 31:0] radio1_radio_tx_data;
wire [ 1-1:0] radio1_radio_tx_stb; wire [ 0:0] radio1_radio_tx_stb;
wire [ 1-1:0] radio1_radio_tx_running; wire [ 0:0] radio1_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (7), .THIS_PORTID (7),
@@ -881,7 +921,6 @@ module rfnoc_image_core #(
.radio_clk (radio1_radio_clk), .radio_clk (radio1_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]),
.rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]),
.m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr),
@@ -899,7 +938,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio1_radio_tx_data), .radio_tx_data (radio1_radio_tx_data),
.radio_tx_stb (radio1_radio_tx_stb), .radio_tx_stb (radio1_radio_tx_stb),
.radio_tx_running (radio1_radio_tx_running), .radio_tx_running (radio1_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio1_in_0_tvalid}),
@@ -918,10 +956,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// replay0 // replay0
// ---------------------------------------------------- //-----------------------------------
wire replay0_mem_clk; wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ; wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
@@ -933,51 +971,51 @@ module rfnoc_image_core #(
wire m_replay0_out_1_tready, m_replay0_out_0_tready; wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram // axi_ram
wire [ 1-1:0] replay0_axi_rst; wire [ 0:0] replay0_axi_rst;
wire [ 4-1:0] replay0_m_axi_awid; wire [ 3:0] replay0_m_axi_awid;
wire [128-1:0] replay0_m_axi_awaddr; wire [ 127:0] replay0_m_axi_awaddr;
wire [ 32-1:0] replay0_m_axi_awlen; wire [ 31:0] replay0_m_axi_awlen;
wire [ 12-1:0] replay0_m_axi_awsize; wire [ 11:0] replay0_m_axi_awsize;
wire [ 8-1:0] replay0_m_axi_awburst; wire [ 7:0] replay0_m_axi_awburst;
wire [ 4-1:0] replay0_m_axi_awlock; wire [ 3:0] replay0_m_axi_awlock;
wire [ 16-1:0] replay0_m_axi_awcache; wire [ 15:0] replay0_m_axi_awcache;
wire [ 12-1:0] replay0_m_axi_awprot; wire [ 11:0] replay0_m_axi_awprot;
wire [ 16-1:0] replay0_m_axi_awqos; wire [ 15:0] replay0_m_axi_awqos;
wire [ 16-1:0] replay0_m_axi_awregion; wire [ 15:0] replay0_m_axi_awregion;
wire [ 4-1:0] replay0_m_axi_awuser; wire [ 3:0] replay0_m_axi_awuser;
wire [ 4-1:0] replay0_m_axi_awvalid; wire [ 3:0] replay0_m_axi_awvalid;
wire [ 4-1:0] replay0_m_axi_awready; wire [ 3:0] replay0_m_axi_awready;
wire [256-1:0] replay0_m_axi_wdata; wire [ 255:0] replay0_m_axi_wdata;
wire [ 32-1:0] replay0_m_axi_wstrb; wire [ 31:0] replay0_m_axi_wstrb;
wire [ 4-1:0] replay0_m_axi_wlast; wire [ 3:0] replay0_m_axi_wlast;
wire [ 4-1:0] replay0_m_axi_wuser; wire [ 3:0] replay0_m_axi_wuser;
wire [ 4-1:0] replay0_m_axi_wvalid; wire [ 3:0] replay0_m_axi_wvalid;
wire [ 4-1:0] replay0_m_axi_wready; wire [ 3:0] replay0_m_axi_wready;
wire [ 4-1:0] replay0_m_axi_bid; wire [ 3:0] replay0_m_axi_bid;
wire [ 8-1:0] replay0_m_axi_bresp; wire [ 7:0] replay0_m_axi_bresp;
wire [ 4-1:0] replay0_m_axi_buser; wire [ 3:0] replay0_m_axi_buser;
wire [ 4-1:0] replay0_m_axi_bvalid; wire [ 3:0] replay0_m_axi_bvalid;
wire [ 4-1:0] replay0_m_axi_bready; wire [ 3:0] replay0_m_axi_bready;
wire [ 4-1:0] replay0_m_axi_arid; wire [ 3:0] replay0_m_axi_arid;
wire [128-1:0] replay0_m_axi_araddr; wire [ 127:0] replay0_m_axi_araddr;
wire [ 32-1:0] replay0_m_axi_arlen; wire [ 31:0] replay0_m_axi_arlen;
wire [ 12-1:0] replay0_m_axi_arsize; wire [ 11:0] replay0_m_axi_arsize;
wire [ 8-1:0] replay0_m_axi_arburst; wire [ 7:0] replay0_m_axi_arburst;
wire [ 4-1:0] replay0_m_axi_arlock; wire [ 3:0] replay0_m_axi_arlock;
wire [ 16-1:0] replay0_m_axi_arcache; wire [ 15:0] replay0_m_axi_arcache;
wire [ 12-1:0] replay0_m_axi_arprot; wire [ 11:0] replay0_m_axi_arprot;
wire [ 16-1:0] replay0_m_axi_arqos; wire [ 15:0] replay0_m_axi_arqos;
wire [ 16-1:0] replay0_m_axi_arregion; wire [ 15:0] replay0_m_axi_arregion;
wire [ 4-1:0] replay0_m_axi_aruser; wire [ 3:0] replay0_m_axi_aruser;
wire [ 4-1:0] replay0_m_axi_arvalid; wire [ 3:0] replay0_m_axi_arvalid;
wire [ 4-1:0] replay0_m_axi_arready; wire [ 3:0] replay0_m_axi_arready;
wire [ 4-1:0] replay0_m_axi_rid; wire [ 3:0] replay0_m_axi_rid;
wire [256-1:0] replay0_m_axi_rdata; wire [ 255:0] replay0_m_axi_rdata;
wire [ 8-1:0] replay0_m_axi_rresp; wire [ 7:0] replay0_m_axi_rresp;
wire [ 4-1:0] replay0_m_axi_rlast; wire [ 3:0] replay0_m_axi_rlast;
wire [ 4-1:0] replay0_m_axi_ruser; wire [ 3:0] replay0_m_axi_ruser;
wire [ 4-1:0] replay0_m_axi_rvalid; wire [ 3:0] replay0_m_axi_rvalid;
wire [ 4-1:0] replay0_m_axi_rready; wire [ 3:0] replay0_m_axi_rready;
rfnoc_block_replay #( rfnoc_block_replay #(
.THIS_PORTID (8), .THIS_PORTID (8),
@@ -992,7 +1030,6 @@ module rfnoc_image_core #(
.mem_clk (replay0_mem_clk), .mem_clk (replay0_mem_clk),
.rfnoc_core_config (rfnoc_core_config[512*7-1:512*6]), .rfnoc_core_config (rfnoc_core_config[512*7-1:512*6]),
.rfnoc_core_status (rfnoc_core_status[512*7-1:512*6]), .rfnoc_core_status (rfnoc_core_status[512*7-1:512*6]),
.axi_rst (replay0_axi_rst), .axi_rst (replay0_axi_rst),
.m_axi_awid (replay0_m_axi_awid), .m_axi_awid (replay0_m_axi_awid),
.m_axi_awaddr (replay0_m_axi_awaddr), .m_axi_awaddr (replay0_m_axi_awaddr),
@@ -1038,7 +1075,6 @@ module rfnoc_image_core #(
.m_axi_ruser (replay0_m_axi_ruser), .m_axi_ruser (replay0_m_axi_ruser),
.m_axi_rvalid (replay0_m_axi_rvalid), .m_axi_rvalid (replay0_m_axi_rvalid),
.m_axi_rready (replay0_m_axi_rready), .m_axi_rready (replay0_m_axi_rready),
.s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
@@ -1057,10 +1093,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready) .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Static Router // Static Router
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_duc0_in_0_tdata = m_ep0_out0_tdata; assign s_duc0_in_0_tdata = m_ep0_out0_tdata;
assign s_duc0_in_0_tlast = m_ep0_out0_tlast; assign s_duc0_in_0_tlast = m_ep0_out0_tlast;
assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid;
@@ -1122,13 +1158,16 @@ module rfnoc_image_core #(
assign m_replay0_out_1_tready = s_ep3_in0_tready; assign m_replay0_out_1_tready = s_ep3_in0_tready;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Unused Ports // Unused Ports
// ---------------------------------------------------- //---------------------------------------------------------------------------
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains // Clock Domains
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk; assign radio0_radio_clk = radio_clk;
assign ddc0_ce_clk = radio_clk; assign ddc0_ce_clk = radio_clk;
assign duc0_ce_clk = radio_clk; assign duc0_ce_clk = radio_clk;
@@ -1138,9 +1177,10 @@ module rfnoc_image_core #(
assign replay0_mem_clk = dram_clk; assign replay0_mem_clk = dram_clk;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// IO Port Connection // IO Port Connection
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Master/Slave Connections: // Master/Slave Connections:
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
@@ -1230,3 +1270,6 @@ module rfnoc_image_core #(
assign radio1_radio_time = radio_time; assign radio1_radio_time = radio_time;
endmodule endmodule
`default_nettype wire
top/n3xx/n320_rfnoc_image_core.vh
+21
View File
@@ -0,0 +1,21 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for n320)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:09.997079
// Source: n320_rfnoc_image_core.yml
// Source SHA256: 3c3a33be8bc2e3b3a7268ba3e07001c6dc6c21af4c9027309a787ac8404e5e8f
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x300/x300_rfnoc_image_core.v
+300 -241
View File
@@ -1,18 +1,31 @@
// //
// Copyright 2020 Ettus Research, A National Instruments Brand // Copyright 2021 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: rfnoc_image_core (for x300) // Module: rfnoc_image_core (for x300)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) //
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// File generated on: 2020-09-02T12:02:29.163114 //
// Source: ./x300_rfnoc_image_core.yml // File generated on: 2021-05-03T08:51:06.967425
// Source SHA256: f64f8b03f805ae93e92c29cbdf8874c497d7ad93d546947e26fa8da501df6e18 // Source: x300_rfnoc_image_core.yml
// Source SHA256: 32a28be8a0bcbe6bb9a5df0058b3c813741fa80c1faafd11270d8b500d7d9b85
//
`default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0} parameter CHDR_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) ( ) (
// Clocks // Clocks
input wire chdr_aclk, input wire chdr_aclk,
@@ -23,130 +36,135 @@ module rfnoc_image_core #(
input wire dram_clk, input wire dram_clk,
// Basic // Basic
input wire [ 15:0] device_id, input wire [ 15:0] device_id,
//// IO ports //////////////////////////////////
// IO ports /////////////////////////
// ctrlport_radio0 // ctrlport_radio0
output wire [ 1-1:0] m_ctrlport_radio0_req_wr, output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 1-1:0] m_ctrlport_radio0_req_rd, output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire [ 20-1:0] m_ctrlport_radio0_req_addr, output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 32-1:0] m_ctrlport_radio0_req_data, output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio0_req_time, output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio0_resp_status, input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 32-1:0] m_ctrlport_radio0_resp_data, input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1 // ctrlport_radio1
output wire [ 1-1:0] m_ctrlport_radio1_req_wr, output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 1-1:0] m_ctrlport_radio1_req_rd, output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire [ 20-1:0] m_ctrlport_radio1_req_addr, output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 32-1:0] m_ctrlport_radio1_req_data, output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio1_req_time, output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio1_resp_status, input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 32-1:0] m_ctrlport_radio1_resp_data, input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time_keeper // time_keeper
input wire [ 64-1:0] radio_time, input wire [ 63:0] radio_time,
// x300_radio0 // x300_radio0
input wire [ 64-1:0] radio_rx_data_radio0, input wire [ 63:0] radio_rx_data_radio0,
input wire [ 2-1:0] radio_rx_stb_radio0, input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 2-1:0] radio_rx_running_radio0, output wire [ 1:0] radio_rx_running_radio0,
output wire [ 64-1:0] radio_tx_data_radio0, output wire [ 63:0] radio_tx_data_radio0,
input wire [ 2-1:0] radio_tx_stb_radio0, input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 2-1:0] radio_tx_running_radio0, output wire [ 1:0] radio_tx_running_radio0,
// x300_radio1 // x300_radio1
input wire [ 64-1:0] radio_rx_data_radio1, input wire [ 63:0] radio_rx_data_radio1,
input wire [ 2-1:0] radio_rx_stb_radio1, input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 2-1:0] radio_rx_running_radio1, output wire [ 1:0] radio_rx_running_radio1,
output wire [ 64-1:0] radio_tx_data_radio1, output wire [ 63:0] radio_tx_data_radio1,
input wire [ 2-1:0] radio_tx_stb_radio1, input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 2-1:0] radio_tx_running_radio1, output wire [ 1:0] radio_tx_running_radio1,
// dram // dram
input wire [ 1-1:0] axi_rst, input wire [ 0:0] axi_rst,
output wire [ 4-1:0] m_axi_awid, output wire [ 3:0] m_axi_awid,
output wire [128-1:0] m_axi_awaddr, output wire [ 127:0] m_axi_awaddr,
output wire [ 32-1:0] m_axi_awlen, output wire [ 31:0] m_axi_awlen,
output wire [ 12-1:0] m_axi_awsize, output wire [ 11:0] m_axi_awsize,
output wire [ 8-1:0] m_axi_awburst, output wire [ 7:0] m_axi_awburst,
output wire [ 4-1:0] m_axi_awlock, output wire [ 3:0] m_axi_awlock,
output wire [ 16-1:0] m_axi_awcache, output wire [ 15:0] m_axi_awcache,
output wire [ 12-1:0] m_axi_awprot, output wire [ 11:0] m_axi_awprot,
output wire [ 16-1:0] m_axi_awqos, output wire [ 15:0] m_axi_awqos,
output wire [ 16-1:0] m_axi_awregion, output wire [ 15:0] m_axi_awregion,
output wire [ 4-1:0] m_axi_awuser, output wire [ 3:0] m_axi_awuser,
output wire [ 4-1:0] m_axi_awvalid, output wire [ 3:0] m_axi_awvalid,
input wire [ 4-1:0] m_axi_awready, input wire [ 3:0] m_axi_awready,
output wire [256-1:0] m_axi_wdata, output wire [ 255:0] m_axi_wdata,
output wire [ 32-1:0] m_axi_wstrb, output wire [ 31:0] m_axi_wstrb,
output wire [ 4-1:0] m_axi_wlast, output wire [ 3:0] m_axi_wlast,
output wire [ 4-1:0] m_axi_wuser, output wire [ 3:0] m_axi_wuser,
output wire [ 4-1:0] m_axi_wvalid, output wire [ 3:0] m_axi_wvalid,
input wire [ 4-1:0] m_axi_wready, input wire [ 3:0] m_axi_wready,
input wire [ 4-1:0] m_axi_bid, input wire [ 3:0] m_axi_bid,
input wire [ 8-1:0] m_axi_bresp, input wire [ 7:0] m_axi_bresp,
input wire [ 4-1:0] m_axi_buser, input wire [ 3:0] m_axi_buser,
input wire [ 4-1:0] m_axi_bvalid, input wire [ 3:0] m_axi_bvalid,
output wire [ 4-1:0] m_axi_bready, output wire [ 3:0] m_axi_bready,
output wire [ 4-1:0] m_axi_arid, output wire [ 3:0] m_axi_arid,
output wire [128-1:0] m_axi_araddr, output wire [ 127:0] m_axi_araddr,
output wire [ 32-1:0] m_axi_arlen, output wire [ 31:0] m_axi_arlen,
output wire [ 12-1:0] m_axi_arsize, output wire [ 11:0] m_axi_arsize,
output wire [ 8-1:0] m_axi_arburst, output wire [ 7:0] m_axi_arburst,
output wire [ 4-1:0] m_axi_arlock, output wire [ 3:0] m_axi_arlock,
output wire [ 16-1:0] m_axi_arcache, output wire [ 15:0] m_axi_arcache,
output wire [ 12-1:0] m_axi_arprot, output wire [ 11:0] m_axi_arprot,
output wire [ 16-1:0] m_axi_arqos, output wire [ 15:0] m_axi_arqos,
output wire [ 16-1:0] m_axi_arregion, output wire [ 15:0] m_axi_arregion,
output wire [ 4-1:0] m_axi_aruser, output wire [ 3:0] m_axi_aruser,
output wire [ 4-1:0] m_axi_arvalid, output wire [ 3:0] m_axi_arvalid,
input wire [ 4-1:0] m_axi_arready, input wire [ 3:0] m_axi_arready,
input wire [ 4-1:0] m_axi_rid, input wire [ 3:0] m_axi_rid,
input wire [256-1:0] m_axi_rdata, input wire [ 255:0] m_axi_rdata,
input wire [ 8-1:0] m_axi_rresp, input wire [ 7:0] m_axi_rresp,
input wire [ 4-1:0] m_axi_rlast, input wire [ 3:0] m_axi_rlast,
input wire [ 4-1:0] m_axi_ruser, input wire [ 3:0] m_axi_ruser,
input wire [ 4-1:0] m_axi_rvalid, input wire [ 3:0] m_axi_rvalid,
output wire [ 4-1:0] m_axi_rready, output wire [ 3:0] m_axi_rready,
// Transport 0 (eth0 10G)
input wire [64-1:0] s_eth0_tdata, // Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [64-1:0] m_eth0_tdata, output wire [CHDR_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1 1G) // Transport 1 (eth1)
input wire [64-1:0] s_eth1_tdata, input wire [CHDR_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [64-1:0] m_eth1_tdata, output wire [CHDR_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (pcie PCIe) // Transport 2 (pcie)
input wire [64-1:0] s_pcie_tdata, input wire [CHDR_W-1:0] s_pcie_tdata,
input wire s_pcie_tlast, input wire s_pcie_tlast,
input wire s_pcie_tvalid, input wire s_pcie_tvalid,
output wire s_pcie_tready, output wire s_pcie_tready,
output wire [64-1:0] m_pcie_tdata, output wire [CHDR_W-1:0] m_pcie_tdata,
output wire m_pcie_tlast, output wire m_pcie_tlast,
output wire m_pcie_tvalid, output wire m_pcie_tvalid,
input wire m_pcie_tready input wire m_pcie_tready
); );
localparam CHDR_W = 64;
localparam MTU = 10;
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// CHDR Crossbar // CHDR Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
@@ -225,9 +243,18 @@ module rfnoc_image_core #(
.ext_rtcfg_ack () .ext_rtcfg_ack ()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Stream Endpoints // Stream Endpoints
// ---------------------------------------------------- //---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 32768;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
@@ -251,7 +278,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
@@ -290,6 +317,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 0;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
@@ -312,7 +347,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (5), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
@@ -351,6 +386,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 32768;
localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
@@ -373,7 +416,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (15), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
@@ -412,6 +455,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 0;
localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
@@ -434,7 +485,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (5), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
@@ -473,6 +524,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 4096;
localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
@@ -495,7 +554,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (4), .INST_NUM (4),
.CTRL_XBAR_PORT (5), .CTRL_XBAR_PORT (5),
.INGRESS_BUFF_SIZE (12), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
@@ -534,6 +593,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 4096;
localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
@@ -556,7 +623,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (5), .INST_NUM (5),
.CTRL_XBAR_PORT (6), .CTRL_XBAR_PORT (6),
.INGRESS_BUFF_SIZE (12), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
@@ -596,10 +663,9 @@ module rfnoc_image_core #(
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Control Crossbar // Control Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast; wire m_core_ctrl_tlast, s_core_ctrl_tlast;
@@ -656,9 +722,11 @@ module rfnoc_image_core #(
.deadlock_detected() .deadlock_detected()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// RFNoC Core Kernel // RFNoC Core Kernel
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status; wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #( rfnoc_core_kernel #(
@@ -696,13 +764,15 @@ module rfnoc_image_core #(
.rfnoc_core_status (rfnoc_core_status) .rfnoc_core_status (rfnoc_core_status)
); );
// ----------------------------------------------------
// Blocks
// ----------------------------------------------------
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// duc0 // duc0
// ---------------------------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_0_tdata ; wire [CHDR_W-1:0] s_duc0_in_0_tdata ;
wire s_duc0_in_0_tlast ; wire s_duc0_in_0_tlast ;
@@ -713,7 +783,6 @@ module rfnoc_image_core #(
wire m_duc0_out_0_tvalid; wire m_duc0_out_0_tvalid;
wire m_duc0_out_0_tready; wire m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -727,8 +796,6 @@ module rfnoc_image_core #(
.ce_clk (duc0_ce_clk), .ce_clk (duc0_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.s_rfnoc_chdr_tdata ({s_duc0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_duc0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_duc0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_duc0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_duc0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_duc0_in_0_tvalid}),
@@ -747,10 +814,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready) .m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// ddc0 // ddc0
// ---------------------------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
@@ -761,7 +828,6 @@ module rfnoc_image_core #(
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -775,8 +841,6 @@ module rfnoc_image_core #(
.ce_clk (ddc0_ce_clk), .ce_clk (ddc0_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
.s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}),
@@ -795,10 +859,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready) .m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// radio0 // radio0
// ---------------------------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
@@ -810,25 +874,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 1-1:0] radio0_m_ctrlport_req_rd; wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 20-1:0] radio0_m_ctrlport_req_addr; wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 32-1:0] radio0_m_ctrlport_req_data; wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio0_m_ctrlport_req_has_time; wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 64-1:0] radio0_m_ctrlport_req_time; wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 1-1:0] radio0_m_ctrlport_resp_ack; wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 2-1:0] radio0_m_ctrlport_resp_status; wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 32-1:0] radio0_m_ctrlport_resp_data; wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio0_radio_time; wire [ 63:0] radio0_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio0_radio_rx_data; wire [ 63:0] radio0_radio_rx_data;
wire [ 2-1:0] radio0_radio_rx_stb; wire [ 1:0] radio0_radio_rx_stb;
wire [ 2-1:0] radio0_radio_rx_running; wire [ 1:0] radio0_radio_rx_running;
wire [ 64-1:0] radio0_radio_tx_data; wire [ 63:0] radio0_radio_tx_data;
wire [ 2-1:0] radio0_radio_tx_stb; wire [ 1:0] radio0_radio_tx_stb;
wire [ 2-1:0] radio0_radio_tx_running; wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
@@ -841,7 +905,6 @@ module rfnoc_image_core #(
.radio_clk (radio0_radio_clk), .radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]),
.rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
@@ -859,7 +922,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio0_radio_tx_data), .radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb), .radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running), .radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
@@ -878,10 +940,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// duc1 // duc1
// ---------------------------------------------------- //-----------------------------------
wire duc1_ce_clk; wire duc1_ce_clk;
wire [CHDR_W-1:0] s_duc1_in_0_tdata ; wire [CHDR_W-1:0] s_duc1_in_0_tdata ;
wire s_duc1_in_0_tlast ; wire s_duc1_in_0_tlast ;
@@ -892,7 +954,6 @@ module rfnoc_image_core #(
wire m_duc1_out_0_tvalid; wire m_duc1_out_0_tvalid;
wire m_duc1_out_0_tready; wire m_duc1_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (5), .THIS_PORTID (5),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -906,8 +967,6 @@ module rfnoc_image_core #(
.ce_clk (duc1_ce_clk), .ce_clk (duc1_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]),
.rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]),
.s_rfnoc_chdr_tdata ({s_duc1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_duc1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_duc1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_duc1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_duc1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_duc1_in_0_tvalid}),
@@ -926,10 +985,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_duc1_ctrl_tready) .m_rfnoc_ctrl_tready (m_duc1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// ddc1 // ddc1
// ---------------------------------------------------- //-----------------------------------
wire ddc1_ce_clk; wire ddc1_ce_clk;
wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ;
wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ;
@@ -940,7 +999,6 @@ module rfnoc_image_core #(
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready; wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (6), .THIS_PORTID (6),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -954,8 +1012,6 @@ module rfnoc_image_core #(
.ce_clk (ddc1_ce_clk), .ce_clk (ddc1_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]),
.rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]),
.s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}),
@@ -974,10 +1030,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready) .m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// radio1 // radio1
// ---------------------------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
@@ -989,25 +1045,25 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tready, m_radio1_out_0_tready; wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 1-1:0] radio1_m_ctrlport_req_rd; wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 20-1:0] radio1_m_ctrlport_req_addr; wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 32-1:0] radio1_m_ctrlport_req_data; wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio1_m_ctrlport_req_has_time; wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire [ 64-1:0] radio1_m_ctrlport_req_time; wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 1-1:0] radio1_m_ctrlport_resp_ack; wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 2-1:0] radio1_m_ctrlport_resp_status; wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 32-1:0] radio1_m_ctrlport_resp_data; wire [ 31:0] radio1_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio1_radio_time; wire [ 63:0] radio1_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio1_radio_rx_data; wire [ 63:0] radio1_radio_rx_data;
wire [ 2-1:0] radio1_radio_rx_stb; wire [ 1:0] radio1_radio_rx_stb;
wire [ 2-1:0] radio1_radio_rx_running; wire [ 1:0] radio1_radio_rx_running;
wire [ 64-1:0] radio1_radio_tx_data; wire [ 63:0] radio1_radio_tx_data;
wire [ 2-1:0] radio1_radio_tx_stb; wire [ 1:0] radio1_radio_tx_stb;
wire [ 2-1:0] radio1_radio_tx_running; wire [ 1:0] radio1_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (7), .THIS_PORTID (7),
@@ -1020,7 +1076,6 @@ module rfnoc_image_core #(
.radio_clk (radio1_radio_clk), .radio_clk (radio1_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]),
.rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]),
.m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr),
@@ -1038,7 +1093,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio1_radio_tx_data), .radio_tx_data (radio1_radio_tx_data),
.radio_tx_stb (radio1_radio_tx_stb), .radio_tx_stb (radio1_radio_tx_stb),
.radio_tx_running (radio1_radio_tx_running), .radio_tx_running (radio1_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}),
@@ -1057,10 +1111,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// replay0 // replay0
// ---------------------------------------------------- //-----------------------------------
wire replay0_mem_clk; wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ; wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
@@ -1072,51 +1126,51 @@ module rfnoc_image_core #(
wire m_replay0_out_1_tready, m_replay0_out_0_tready; wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram // axi_ram
wire [ 1-1:0] replay0_axi_rst; wire [ 0:0] replay0_axi_rst;
wire [ 4-1:0] replay0_m_axi_awid; wire [ 3:0] replay0_m_axi_awid;
wire [128-1:0] replay0_m_axi_awaddr; wire [ 127:0] replay0_m_axi_awaddr;
wire [ 32-1:0] replay0_m_axi_awlen; wire [ 31:0] replay0_m_axi_awlen;
wire [ 12-1:0] replay0_m_axi_awsize; wire [ 11:0] replay0_m_axi_awsize;
wire [ 8-1:0] replay0_m_axi_awburst; wire [ 7:0] replay0_m_axi_awburst;
wire [ 4-1:0] replay0_m_axi_awlock; wire [ 3:0] replay0_m_axi_awlock;
wire [ 16-1:0] replay0_m_axi_awcache; wire [ 15:0] replay0_m_axi_awcache;
wire [ 12-1:0] replay0_m_axi_awprot; wire [ 11:0] replay0_m_axi_awprot;
wire [ 16-1:0] replay0_m_axi_awqos; wire [ 15:0] replay0_m_axi_awqos;
wire [ 16-1:0] replay0_m_axi_awregion; wire [ 15:0] replay0_m_axi_awregion;
wire [ 4-1:0] replay0_m_axi_awuser; wire [ 3:0] replay0_m_axi_awuser;
wire [ 4-1:0] replay0_m_axi_awvalid; wire [ 3:0] replay0_m_axi_awvalid;
wire [ 4-1:0] replay0_m_axi_awready; wire [ 3:0] replay0_m_axi_awready;
wire [256-1:0] replay0_m_axi_wdata; wire [ 255:0] replay0_m_axi_wdata;
wire [ 32-1:0] replay0_m_axi_wstrb; wire [ 31:0] replay0_m_axi_wstrb;
wire [ 4-1:0] replay0_m_axi_wlast; wire [ 3:0] replay0_m_axi_wlast;
wire [ 4-1:0] replay0_m_axi_wuser; wire [ 3:0] replay0_m_axi_wuser;
wire [ 4-1:0] replay0_m_axi_wvalid; wire [ 3:0] replay0_m_axi_wvalid;
wire [ 4-1:0] replay0_m_axi_wready; wire [ 3:0] replay0_m_axi_wready;
wire [ 4-1:0] replay0_m_axi_bid; wire [ 3:0] replay0_m_axi_bid;
wire [ 8-1:0] replay0_m_axi_bresp; wire [ 7:0] replay0_m_axi_bresp;
wire [ 4-1:0] replay0_m_axi_buser; wire [ 3:0] replay0_m_axi_buser;
wire [ 4-1:0] replay0_m_axi_bvalid; wire [ 3:0] replay0_m_axi_bvalid;
wire [ 4-1:0] replay0_m_axi_bready; wire [ 3:0] replay0_m_axi_bready;
wire [ 4-1:0] replay0_m_axi_arid; wire [ 3:0] replay0_m_axi_arid;
wire [128-1:0] replay0_m_axi_araddr; wire [ 127:0] replay0_m_axi_araddr;
wire [ 32-1:0] replay0_m_axi_arlen; wire [ 31:0] replay0_m_axi_arlen;
wire [ 12-1:0] replay0_m_axi_arsize; wire [ 11:0] replay0_m_axi_arsize;
wire [ 8-1:0] replay0_m_axi_arburst; wire [ 7:0] replay0_m_axi_arburst;
wire [ 4-1:0] replay0_m_axi_arlock; wire [ 3:0] replay0_m_axi_arlock;
wire [ 16-1:0] replay0_m_axi_arcache; wire [ 15:0] replay0_m_axi_arcache;
wire [ 12-1:0] replay0_m_axi_arprot; wire [ 11:0] replay0_m_axi_arprot;
wire [ 16-1:0] replay0_m_axi_arqos; wire [ 15:0] replay0_m_axi_arqos;
wire [ 16-1:0] replay0_m_axi_arregion; wire [ 15:0] replay0_m_axi_arregion;
wire [ 4-1:0] replay0_m_axi_aruser; wire [ 3:0] replay0_m_axi_aruser;
wire [ 4-1:0] replay0_m_axi_arvalid; wire [ 3:0] replay0_m_axi_arvalid;
wire [ 4-1:0] replay0_m_axi_arready; wire [ 3:0] replay0_m_axi_arready;
wire [ 4-1:0] replay0_m_axi_rid; wire [ 3:0] replay0_m_axi_rid;
wire [256-1:0] replay0_m_axi_rdata; wire [ 255:0] replay0_m_axi_rdata;
wire [ 8-1:0] replay0_m_axi_rresp; wire [ 7:0] replay0_m_axi_rresp;
wire [ 4-1:0] replay0_m_axi_rlast; wire [ 3:0] replay0_m_axi_rlast;
wire [ 4-1:0] replay0_m_axi_ruser; wire [ 3:0] replay0_m_axi_ruser;
wire [ 4-1:0] replay0_m_axi_rvalid; wire [ 3:0] replay0_m_axi_rvalid;
wire [ 4-1:0] replay0_m_axi_rready; wire [ 3:0] replay0_m_axi_rready;
rfnoc_block_replay #( rfnoc_block_replay #(
.THIS_PORTID (8), .THIS_PORTID (8),
@@ -1131,7 +1185,6 @@ module rfnoc_image_core #(
.mem_clk (replay0_mem_clk), .mem_clk (replay0_mem_clk),
.rfnoc_core_config (rfnoc_core_config[512*7-1:512*6]), .rfnoc_core_config (rfnoc_core_config[512*7-1:512*6]),
.rfnoc_core_status (rfnoc_core_status[512*7-1:512*6]), .rfnoc_core_status (rfnoc_core_status[512*7-1:512*6]),
.axi_rst (replay0_axi_rst), .axi_rst (replay0_axi_rst),
.m_axi_awid (replay0_m_axi_awid), .m_axi_awid (replay0_m_axi_awid),
.m_axi_awaddr (replay0_m_axi_awaddr), .m_axi_awaddr (replay0_m_axi_awaddr),
@@ -1177,7 +1230,6 @@ module rfnoc_image_core #(
.m_axi_ruser (replay0_m_axi_ruser), .m_axi_ruser (replay0_m_axi_ruser),
.m_axi_rvalid (replay0_m_axi_rvalid), .m_axi_rvalid (replay0_m_axi_rvalid),
.m_axi_rready (replay0_m_axi_rready), .m_axi_rready (replay0_m_axi_rready),
.s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
@@ -1196,10 +1248,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready) .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Static Router // Static Router
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_duc0_in_0_tdata = m_ep0_out0_tdata; assign s_duc0_in_0_tdata = m_ep0_out0_tdata;
assign s_duc0_in_0_tlast = m_ep0_out0_tlast; assign s_duc0_in_0_tlast = m_ep0_out0_tlast;
assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid;
@@ -1281,9 +1333,10 @@ module rfnoc_image_core #(
assign m_replay0_out_1_tready = s_ep5_in0_tready; assign m_replay0_out_1_tready = s_ep5_in0_tready;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Unused Ports // Unused Ports
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_radio0_in_1_tdata = {CHDR_W{1'b0}}; assign s_radio0_in_1_tdata = {CHDR_W{1'b0}};
assign s_radio0_in_1_tlast = 1'b0; assign s_radio0_in_1_tlast = 1'b0;
assign s_radio0_in_1_tvalid = 1'b0; assign s_radio0_in_1_tvalid = 1'b0;
@@ -1293,9 +1346,11 @@ module rfnoc_image_core #(
assign m_ep1_out0_tready = 1'b1; assign m_ep1_out0_tready = 1'b1;
assign m_ep3_out0_tready = 1'b1; assign m_ep3_out0_tready = 1'b1;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains // Clock Domains
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk; assign radio0_radio_clk = radio_clk;
assign ddc0_ce_clk = ce_clk; assign ddc0_ce_clk = ce_clk;
assign duc0_ce_clk = ce_clk; assign duc0_ce_clk = ce_clk;
@@ -1305,9 +1360,10 @@ module rfnoc_image_core #(
assign replay0_mem_clk = dram_clk; assign replay0_mem_clk = dram_clk;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// IO Port Connection // IO Port Connection
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Master/Slave Connections: // Master/Slave Connections:
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
@@ -1397,3 +1453,6 @@ module rfnoc_image_core #(
assign radio1_radio_time = radio_time; assign radio1_radio_time = radio_time;
endmodule endmodule
`default_nettype wire
top/x300/x300_rfnoc_image_core.vh
+21
View File
@@ -0,0 +1,21 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x300)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:07.013471
// Source: x300_rfnoc_image_core.yml
// Source SHA256: 32a28be8a0bcbe6bb9a5df0058b3c813741fa80c1faafd11270d8b500d7d9b85
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }
top/x300/x310_rfnoc_image_core.v
+300 -241
View File
@@ -1,18 +1,31 @@
// //
// Copyright 2020 Ettus Research, A National Instruments Brand // Copyright 2021 Ettus Research, A National Instruments Brand
// //
// SPDX-License-Identifier: LGPL-3.0-or-later // SPDX-License-Identifier: LGPL-3.0-or-later
// //
// Module: rfnoc_image_core (for x300) // Module: rfnoc_image_core (for x300)
// This file was autogenerated by UHD's image builder tool (rfnoc_image_builder) //
// Description:
//
// The RFNoC Image Core contains the Verilog description of the RFNoC design
// to be loaded onto the FPGA.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file! // Re-running that tool will overwrite this file!
// File generated on: 2020-09-02T12:02:33.545638 //
// Source: ./x310_rfnoc_image_core.yml // File generated on: 2021-05-03T08:51:07.732667
// Source SHA256: acc39ec2e56ad0a5dd482a8db6b4dbb7e9790c03074d7461a38e0b5356456a83 // Source: x310_rfnoc_image_core.yml
// Source SHA256: 7a01e3b4aa95b9e5b59f627d5a7d3f27c16afb4bb6bdad1f7fb9a624fb4b9647
//
`default_nettype none
module rfnoc_image_core #( module rfnoc_image_core #(
parameter [15:0] PROTOVER = {8'd1, 8'd0} parameter CHDR_W = 64,
parameter MTU = 10,
parameter [15:0] PROTOVER = {8'd1, 8'd0},
parameter RADIO_NIPC = 1
) ( ) (
// Clocks // Clocks
input wire chdr_aclk, input wire chdr_aclk,
@@ -23,130 +36,135 @@ module rfnoc_image_core #(
input wire dram_clk, input wire dram_clk,
// Basic // Basic
input wire [ 15:0] device_id, input wire [ 15:0] device_id,
//// IO ports //////////////////////////////////
// IO ports /////////////////////////
// ctrlport_radio0 // ctrlport_radio0
output wire [ 1-1:0] m_ctrlport_radio0_req_wr, output wire [ 0:0] m_ctrlport_radio0_req_wr,
output wire [ 1-1:0] m_ctrlport_radio0_req_rd, output wire [ 0:0] m_ctrlport_radio0_req_rd,
output wire [ 20-1:0] m_ctrlport_radio0_req_addr, output wire [ 19:0] m_ctrlport_radio0_req_addr,
output wire [ 32-1:0] m_ctrlport_radio0_req_data, output wire [ 31:0] m_ctrlport_radio0_req_data,
output wire [ 4-1:0] m_ctrlport_radio0_req_byte_en, output wire [ 3:0] m_ctrlport_radio0_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio0_req_has_time, output wire [ 0:0] m_ctrlport_radio0_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio0_req_time, output wire [ 63:0] m_ctrlport_radio0_req_time,
input wire [ 1-1:0] m_ctrlport_radio0_resp_ack, input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio0_resp_status, input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 32-1:0] m_ctrlport_radio0_resp_data, input wire [ 31:0] m_ctrlport_radio0_resp_data,
// ctrlport_radio1 // ctrlport_radio1
output wire [ 1-1:0] m_ctrlport_radio1_req_wr, output wire [ 0:0] m_ctrlport_radio1_req_wr,
output wire [ 1-1:0] m_ctrlport_radio1_req_rd, output wire [ 0:0] m_ctrlport_radio1_req_rd,
output wire [ 20-1:0] m_ctrlport_radio1_req_addr, output wire [ 19:0] m_ctrlport_radio1_req_addr,
output wire [ 32-1:0] m_ctrlport_radio1_req_data, output wire [ 31:0] m_ctrlport_radio1_req_data,
output wire [ 4-1:0] m_ctrlport_radio1_req_byte_en, output wire [ 3:0] m_ctrlport_radio1_req_byte_en,
output wire [ 1-1:0] m_ctrlport_radio1_req_has_time, output wire [ 0:0] m_ctrlport_radio1_req_has_time,
output wire [ 64-1:0] m_ctrlport_radio1_req_time, output wire [ 63:0] m_ctrlport_radio1_req_time,
input wire [ 1-1:0] m_ctrlport_radio1_resp_ack, input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 2-1:0] m_ctrlport_radio1_resp_status, input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 32-1:0] m_ctrlport_radio1_resp_data, input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time_keeper // time_keeper
input wire [ 64-1:0] radio_time, input wire [ 63:0] radio_time,
// x300_radio0 // x300_radio0
input wire [ 64-1:0] radio_rx_data_radio0, input wire [ 63:0] radio_rx_data_radio0,
input wire [ 2-1:0] radio_rx_stb_radio0, input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 2-1:0] radio_rx_running_radio0, output wire [ 1:0] radio_rx_running_radio0,
output wire [ 64-1:0] radio_tx_data_radio0, output wire [ 63:0] radio_tx_data_radio0,
input wire [ 2-1:0] radio_tx_stb_radio0, input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 2-1:0] radio_tx_running_radio0, output wire [ 1:0] radio_tx_running_radio0,
// x300_radio1 // x300_radio1
input wire [ 64-1:0] radio_rx_data_radio1, input wire [ 63:0] radio_rx_data_radio1,
input wire [ 2-1:0] radio_rx_stb_radio1, input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 2-1:0] radio_rx_running_radio1, output wire [ 1:0] radio_rx_running_radio1,
output wire [ 64-1:0] radio_tx_data_radio1, output wire [ 63:0] radio_tx_data_radio1,
input wire [ 2-1:0] radio_tx_stb_radio1, input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 2-1:0] radio_tx_running_radio1, output wire [ 1:0] radio_tx_running_radio1,
// dram // dram
input wire [ 1-1:0] axi_rst, input wire [ 0:0] axi_rst,
output wire [ 4-1:0] m_axi_awid, output wire [ 3:0] m_axi_awid,
output wire [128-1:0] m_axi_awaddr, output wire [ 127:0] m_axi_awaddr,
output wire [ 32-1:0] m_axi_awlen, output wire [ 31:0] m_axi_awlen,
output wire [ 12-1:0] m_axi_awsize, output wire [ 11:0] m_axi_awsize,
output wire [ 8-1:0] m_axi_awburst, output wire [ 7:0] m_axi_awburst,
output wire [ 4-1:0] m_axi_awlock, output wire [ 3:0] m_axi_awlock,
output wire [ 16-1:0] m_axi_awcache, output wire [ 15:0] m_axi_awcache,
output wire [ 12-1:0] m_axi_awprot, output wire [ 11:0] m_axi_awprot,
output wire [ 16-1:0] m_axi_awqos, output wire [ 15:0] m_axi_awqos,
output wire [ 16-1:0] m_axi_awregion, output wire [ 15:0] m_axi_awregion,
output wire [ 4-1:0] m_axi_awuser, output wire [ 3:0] m_axi_awuser,
output wire [ 4-1:0] m_axi_awvalid, output wire [ 3:0] m_axi_awvalid,
input wire [ 4-1:0] m_axi_awready, input wire [ 3:0] m_axi_awready,
output wire [256-1:0] m_axi_wdata, output wire [ 255:0] m_axi_wdata,
output wire [ 32-1:0] m_axi_wstrb, output wire [ 31:0] m_axi_wstrb,
output wire [ 4-1:0] m_axi_wlast, output wire [ 3:0] m_axi_wlast,
output wire [ 4-1:0] m_axi_wuser, output wire [ 3:0] m_axi_wuser,
output wire [ 4-1:0] m_axi_wvalid, output wire [ 3:0] m_axi_wvalid,
input wire [ 4-1:0] m_axi_wready, input wire [ 3:0] m_axi_wready,
input wire [ 4-1:0] m_axi_bid, input wire [ 3:0] m_axi_bid,
input wire [ 8-1:0] m_axi_bresp, input wire [ 7:0] m_axi_bresp,
input wire [ 4-1:0] m_axi_buser, input wire [ 3:0] m_axi_buser,
input wire [ 4-1:0] m_axi_bvalid, input wire [ 3:0] m_axi_bvalid,
output wire [ 4-1:0] m_axi_bready, output wire [ 3:0] m_axi_bready,
output wire [ 4-1:0] m_axi_arid, output wire [ 3:0] m_axi_arid,
output wire [128-1:0] m_axi_araddr, output wire [ 127:0] m_axi_araddr,
output wire [ 32-1:0] m_axi_arlen, output wire [ 31:0] m_axi_arlen,
output wire [ 12-1:0] m_axi_arsize, output wire [ 11:0] m_axi_arsize,
output wire [ 8-1:0] m_axi_arburst, output wire [ 7:0] m_axi_arburst,
output wire [ 4-1:0] m_axi_arlock, output wire [ 3:0] m_axi_arlock,
output wire [ 16-1:0] m_axi_arcache, output wire [ 15:0] m_axi_arcache,
output wire [ 12-1:0] m_axi_arprot, output wire [ 11:0] m_axi_arprot,
output wire [ 16-1:0] m_axi_arqos, output wire [ 15:0] m_axi_arqos,
output wire [ 16-1:0] m_axi_arregion, output wire [ 15:0] m_axi_arregion,
output wire [ 4-1:0] m_axi_aruser, output wire [ 3:0] m_axi_aruser,
output wire [ 4-1:0] m_axi_arvalid, output wire [ 3:0] m_axi_arvalid,
input wire [ 4-1:0] m_axi_arready, input wire [ 3:0] m_axi_arready,
input wire [ 4-1:0] m_axi_rid, input wire [ 3:0] m_axi_rid,
input wire [256-1:0] m_axi_rdata, input wire [ 255:0] m_axi_rdata,
input wire [ 8-1:0] m_axi_rresp, input wire [ 7:0] m_axi_rresp,
input wire [ 4-1:0] m_axi_rlast, input wire [ 3:0] m_axi_rlast,
input wire [ 4-1:0] m_axi_ruser, input wire [ 3:0] m_axi_ruser,
input wire [ 4-1:0] m_axi_rvalid, input wire [ 3:0] m_axi_rvalid,
output wire [ 4-1:0] m_axi_rready, output wire [ 3:0] m_axi_rready,
// Transport 0 (eth0 10G)
input wire [64-1:0] s_eth0_tdata, // Transport Adapters ///////////////
// Transport 0 (eth0)
input wire [CHDR_W-1:0] s_eth0_tdata,
input wire s_eth0_tlast, input wire s_eth0_tlast,
input wire s_eth0_tvalid, input wire s_eth0_tvalid,
output wire s_eth0_tready, output wire s_eth0_tready,
output wire [64-1:0] m_eth0_tdata, output wire [CHDR_W-1:0] m_eth0_tdata,
output wire m_eth0_tlast, output wire m_eth0_tlast,
output wire m_eth0_tvalid, output wire m_eth0_tvalid,
input wire m_eth0_tready, input wire m_eth0_tready,
// Transport 1 (eth1 1G) // Transport 1 (eth1)
input wire [64-1:0] s_eth1_tdata, input wire [CHDR_W-1:0] s_eth1_tdata,
input wire s_eth1_tlast, input wire s_eth1_tlast,
input wire s_eth1_tvalid, input wire s_eth1_tvalid,
output wire s_eth1_tready, output wire s_eth1_tready,
output wire [64-1:0] m_eth1_tdata, output wire [CHDR_W-1:0] m_eth1_tdata,
output wire m_eth1_tlast, output wire m_eth1_tlast,
output wire m_eth1_tvalid, output wire m_eth1_tvalid,
input wire m_eth1_tready, input wire m_eth1_tready,
// Transport 2 (pcie PCIe) // Transport 2 (pcie)
input wire [64-1:0] s_pcie_tdata, input wire [CHDR_W-1:0] s_pcie_tdata,
input wire s_pcie_tlast, input wire s_pcie_tlast,
input wire s_pcie_tvalid, input wire s_pcie_tvalid,
output wire s_pcie_tready, output wire s_pcie_tready,
output wire [64-1:0] m_pcie_tdata, output wire [CHDR_W-1:0] m_pcie_tdata,
output wire m_pcie_tlast, output wire m_pcie_tlast,
output wire m_pcie_tvalid, output wire m_pcie_tvalid,
input wire m_pcie_tready input wire m_pcie_tready
); );
localparam CHDR_W = 64;
localparam MTU = 10;
localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`"; localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";
wire rfnoc_chdr_clk, rfnoc_chdr_rst; wire rfnoc_chdr_clk, rfnoc_chdr_rst;
wire rfnoc_ctrl_clk, rfnoc_ctrl_rst; wire rfnoc_ctrl_clk, rfnoc_ctrl_rst;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// CHDR Crossbar // CHDR Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [CHDR_W-1:0] xb_to_ep0_tdata ; wire [CHDR_W-1:0] xb_to_ep0_tdata ;
wire xb_to_ep0_tlast ; wire xb_to_ep0_tlast ;
wire xb_to_ep0_tvalid; wire xb_to_ep0_tvalid;
@@ -225,9 +243,18 @@ module rfnoc_image_core #(
.ext_rtcfg_ack () .ext_rtcfg_ack ()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Stream Endpoints // Stream Endpoints
// ---------------------------------------------------- //---------------------------------------------------------------------------
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP0 = 65536;
localparam INGRESS_BUFF_SIZE_EP0 =
REQ_BUFF_SIZE_EP0 == 0 ? 5 :
REQ_BUFF_SIZE_EP0 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP0);
wire [CHDR_W-1:0] m_ep0_out0_tdata; wire [CHDR_W-1:0] m_ep0_out0_tdata;
wire m_ep0_out0_tlast; wire m_ep0_out0_tlast;
@@ -251,7 +278,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (0), .INST_NUM (0),
.CTRL_XBAR_PORT (1), .CTRL_XBAR_PORT (1),
.INGRESS_BUFF_SIZE (16), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP0),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep0_i ( ) ep0_i (
@@ -290,6 +317,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP1 = 0;
localparam INGRESS_BUFF_SIZE_EP1 =
REQ_BUFF_SIZE_EP1 == 0 ? 5 :
REQ_BUFF_SIZE_EP1 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP1);
wire [CHDR_W-1:0] m_ep1_out0_tdata; wire [CHDR_W-1:0] m_ep1_out0_tdata;
wire m_ep1_out0_tlast; wire m_ep1_out0_tlast;
wire m_ep1_out0_tvalid; wire m_ep1_out0_tvalid;
@@ -312,7 +347,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (1), .INST_NUM (1),
.CTRL_XBAR_PORT (2), .CTRL_XBAR_PORT (2),
.INGRESS_BUFF_SIZE (5), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP1),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep1_i ( ) ep1_i (
@@ -351,6 +386,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP2 = 65536;
localparam INGRESS_BUFF_SIZE_EP2 =
REQ_BUFF_SIZE_EP2 == 0 ? 5 :
REQ_BUFF_SIZE_EP2 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP2);
wire [CHDR_W-1:0] m_ep2_out0_tdata; wire [CHDR_W-1:0] m_ep2_out0_tdata;
wire m_ep2_out0_tlast; wire m_ep2_out0_tlast;
wire m_ep2_out0_tvalid; wire m_ep2_out0_tvalid;
@@ -373,7 +416,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (2), .INST_NUM (2),
.CTRL_XBAR_PORT (3), .CTRL_XBAR_PORT (3),
.INGRESS_BUFF_SIZE (16), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP2),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep2_i ( ) ep2_i (
@@ -412,6 +455,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP3 = 0;
localparam INGRESS_BUFF_SIZE_EP3 =
REQ_BUFF_SIZE_EP3 == 0 ? 5 :
REQ_BUFF_SIZE_EP3 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP3);
wire [CHDR_W-1:0] m_ep3_out0_tdata; wire [CHDR_W-1:0] m_ep3_out0_tdata;
wire m_ep3_out0_tlast; wire m_ep3_out0_tlast;
wire m_ep3_out0_tvalid; wire m_ep3_out0_tvalid;
@@ -434,7 +485,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (3), .INST_NUM (3),
.CTRL_XBAR_PORT (4), .CTRL_XBAR_PORT (4),
.INGRESS_BUFF_SIZE (5), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP3),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep3_i ( ) ep3_i (
@@ -473,6 +524,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP4 = 4096;
localparam INGRESS_BUFF_SIZE_EP4 =
REQ_BUFF_SIZE_EP4 == 0 ? 5 :
REQ_BUFF_SIZE_EP4 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP4);
wire [CHDR_W-1:0] m_ep4_out0_tdata; wire [CHDR_W-1:0] m_ep4_out0_tdata;
wire m_ep4_out0_tlast; wire m_ep4_out0_tlast;
wire m_ep4_out0_tvalid; wire m_ep4_out0_tvalid;
@@ -495,7 +554,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (4), .INST_NUM (4),
.CTRL_XBAR_PORT (5), .CTRL_XBAR_PORT (5),
.INGRESS_BUFF_SIZE (12), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP4),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep4_i ( ) ep4_i (
@@ -534,6 +593,14 @@ module rfnoc_image_core #(
.signal_data_err (1'b0) .signal_data_err (1'b0)
); );
// If requested buffer size is 0, use the minimum SRL-based FIFO size.
// Otherwise, make sure it's at least two MTU-sized packets.
localparam REQ_BUFF_SIZE_EP5 = 4096;
localparam INGRESS_BUFF_SIZE_EP5 =
REQ_BUFF_SIZE_EP5 == 0 ? 5 :
REQ_BUFF_SIZE_EP5 < 2*(2**MTU) ? MTU+1 :
$clog2(REQ_BUFF_SIZE_EP5);
wire [CHDR_W-1:0] m_ep5_out0_tdata; wire [CHDR_W-1:0] m_ep5_out0_tdata;
wire m_ep5_out0_tlast; wire m_ep5_out0_tlast;
wire m_ep5_out0_tvalid; wire m_ep5_out0_tvalid;
@@ -556,7 +623,7 @@ module rfnoc_image_core #(
.NUM_DATA_O (1), .NUM_DATA_O (1),
.INST_NUM (5), .INST_NUM (5),
.CTRL_XBAR_PORT (6), .CTRL_XBAR_PORT (6),
.INGRESS_BUFF_SIZE (12), .INGRESS_BUFF_SIZE (INGRESS_BUFF_SIZE_EP5),
.MTU (MTU), .MTU (MTU),
.REPORT_STRM_ERRS (1) .REPORT_STRM_ERRS (1)
) ep5_i ( ) ep5_i (
@@ -596,10 +663,9 @@ module rfnoc_image_core #(
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Control Crossbar // Control Crossbar
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata; wire [31:0] m_core_ctrl_tdata, s_core_ctrl_tdata;
wire m_core_ctrl_tlast, s_core_ctrl_tlast; wire m_core_ctrl_tlast, s_core_ctrl_tlast;
@@ -656,9 +722,11 @@ module rfnoc_image_core #(
.deadlock_detected() .deadlock_detected()
); );
// ----------------------------------------------------
//---------------------------------------------------------------------------
// RFNoC Core Kernel // RFNoC Core Kernel
// ---------------------------------------------------- //---------------------------------------------------------------------------
wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status; wire [(512*7)-1:0] rfnoc_core_config, rfnoc_core_status;
rfnoc_core_kernel #( rfnoc_core_kernel #(
@@ -696,13 +764,15 @@ module rfnoc_image_core #(
.rfnoc_core_status (rfnoc_core_status) .rfnoc_core_status (rfnoc_core_status)
); );
// ----------------------------------------------------
// Blocks
// ----------------------------------------------------
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Blocks
//---------------------------------------------------------------------------
//-----------------------------------
// duc0 // duc0
// ---------------------------------------------------- //-----------------------------------
wire duc0_ce_clk; wire duc0_ce_clk;
wire [CHDR_W-1:0] s_duc0_in_0_tdata ; wire [CHDR_W-1:0] s_duc0_in_0_tdata ;
wire s_duc0_in_0_tlast ; wire s_duc0_in_0_tlast ;
@@ -713,7 +783,6 @@ module rfnoc_image_core #(
wire m_duc0_out_0_tvalid; wire m_duc0_out_0_tvalid;
wire m_duc0_out_0_tready; wire m_duc0_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (2), .THIS_PORTID (2),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -727,8 +796,6 @@ module rfnoc_image_core #(
.ce_clk (duc0_ce_clk), .ce_clk (duc0_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]), .rfnoc_core_config (rfnoc_core_config[512*1-1:512*0]),
.rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]), .rfnoc_core_status (rfnoc_core_status[512*1-1:512*0]),
.s_rfnoc_chdr_tdata ({s_duc0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_duc0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_duc0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_duc0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_duc0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_duc0_in_0_tvalid}),
@@ -747,10 +814,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_duc0_ctrl_tready) .m_rfnoc_ctrl_tready (m_duc0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// ddc0 // ddc0
// ---------------------------------------------------- //-----------------------------------
wire ddc0_ce_clk; wire ddc0_ce_clk;
wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ; wire [CHDR_W-1:0] s_ddc0_in_1_tdata , s_ddc0_in_0_tdata ;
wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ; wire s_ddc0_in_1_tlast , s_ddc0_in_0_tlast ;
@@ -761,7 +828,6 @@ module rfnoc_image_core #(
wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid; wire m_ddc0_out_1_tvalid, m_ddc0_out_0_tvalid;
wire m_ddc0_out_1_tready, m_ddc0_out_0_tready; wire m_ddc0_out_1_tready, m_ddc0_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (3), .THIS_PORTID (3),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -775,8 +841,6 @@ module rfnoc_image_core #(
.ce_clk (ddc0_ce_clk), .ce_clk (ddc0_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]), .rfnoc_core_config (rfnoc_core_config[512*2-1:512*1]),
.rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]), .rfnoc_core_status (rfnoc_core_status[512*2-1:512*1]),
.s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_ddc0_in_1_tdata , s_ddc0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_ddc0_in_1_tlast , s_ddc0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_ddc0_in_1_tvalid, s_ddc0_in_0_tvalid}),
@@ -795,10 +859,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready) .m_rfnoc_ctrl_tready (m_ddc0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// radio0 // radio0
// ---------------------------------------------------- //-----------------------------------
wire radio0_radio_clk; wire radio0_radio_clk;
wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ; wire [CHDR_W-1:0] s_radio0_in_1_tdata , s_radio0_in_0_tdata ;
wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ; wire s_radio0_in_1_tlast , s_radio0_in_0_tlast ;
@@ -810,25 +874,25 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tready, m_radio0_out_0_tready; wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio0_m_ctrlport_req_wr; wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 1-1:0] radio0_m_ctrlport_req_rd; wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 20-1:0] radio0_m_ctrlport_req_addr; wire [ 19:0] radio0_m_ctrlport_req_addr;
wire [ 32-1:0] radio0_m_ctrlport_req_data; wire [ 31:0] radio0_m_ctrlport_req_data;
wire [ 4-1:0] radio0_m_ctrlport_req_byte_en; wire [ 3:0] radio0_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio0_m_ctrlport_req_has_time; wire [ 0:0] radio0_m_ctrlport_req_has_time;
wire [ 64-1:0] radio0_m_ctrlport_req_time; wire [ 63:0] radio0_m_ctrlport_req_time;
wire [ 1-1:0] radio0_m_ctrlport_resp_ack; wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 2-1:0] radio0_m_ctrlport_resp_status; wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 32-1:0] radio0_m_ctrlport_resp_data; wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio0_radio_time; wire [ 63:0] radio0_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio0_radio_rx_data; wire [ 63:0] radio0_radio_rx_data;
wire [ 2-1:0] radio0_radio_rx_stb; wire [ 1:0] radio0_radio_rx_stb;
wire [ 2-1:0] radio0_radio_rx_running; wire [ 1:0] radio0_radio_rx_running;
wire [ 64-1:0] radio0_radio_tx_data; wire [ 63:0] radio0_radio_tx_data;
wire [ 2-1:0] radio0_radio_tx_stb; wire [ 1:0] radio0_radio_tx_stb;
wire [ 2-1:0] radio0_radio_tx_running; wire [ 1:0] radio0_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (4), .THIS_PORTID (4),
@@ -841,7 +905,6 @@ module rfnoc_image_core #(
.radio_clk (radio0_radio_clk), .radio_clk (radio0_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]), .rfnoc_core_config (rfnoc_core_config[512*3-1:512*2]),
.rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]), .rfnoc_core_status (rfnoc_core_status[512*3-1:512*2]),
.m_ctrlport_req_wr (radio0_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio0_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio0_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio0_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio0_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio0_m_ctrlport_req_addr),
@@ -859,7 +922,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio0_radio_tx_data), .radio_tx_data (radio0_radio_tx_data),
.radio_tx_stb (radio0_radio_tx_stb), .radio_tx_stb (radio0_radio_tx_stb),
.radio_tx_running (radio0_radio_tx_running), .radio_tx_running (radio0_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio0_in_1_tdata , s_radio0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio0_in_1_tlast , s_radio0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio0_in_1_tvalid, s_radio0_in_0_tvalid}),
@@ -878,10 +940,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio0_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio0_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// duc1 // duc1
// ---------------------------------------------------- //-----------------------------------
wire duc1_ce_clk; wire duc1_ce_clk;
wire [CHDR_W-1:0] s_duc1_in_0_tdata ; wire [CHDR_W-1:0] s_duc1_in_0_tdata ;
wire s_duc1_in_0_tlast ; wire s_duc1_in_0_tlast ;
@@ -892,7 +954,6 @@ module rfnoc_image_core #(
wire m_duc1_out_0_tvalid; wire m_duc1_out_0_tvalid;
wire m_duc1_out_0_tready; wire m_duc1_out_0_tready;
rfnoc_block_duc #( rfnoc_block_duc #(
.THIS_PORTID (5), .THIS_PORTID (5),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -906,8 +967,6 @@ module rfnoc_image_core #(
.ce_clk (duc1_ce_clk), .ce_clk (duc1_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]), .rfnoc_core_config (rfnoc_core_config[512*4-1:512*3]),
.rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]), .rfnoc_core_status (rfnoc_core_status[512*4-1:512*3]),
.s_rfnoc_chdr_tdata ({s_duc1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_duc1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_duc1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_duc1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_duc1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_duc1_in_0_tvalid}),
@@ -926,10 +985,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_duc1_ctrl_tready) .m_rfnoc_ctrl_tready (m_duc1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// ddc1 // ddc1
// ---------------------------------------------------- //-----------------------------------
wire ddc1_ce_clk; wire ddc1_ce_clk;
wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ; wire [CHDR_W-1:0] s_ddc1_in_1_tdata , s_ddc1_in_0_tdata ;
wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ; wire s_ddc1_in_1_tlast , s_ddc1_in_0_tlast ;
@@ -940,7 +999,6 @@ module rfnoc_image_core #(
wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid; wire m_ddc1_out_1_tvalid, m_ddc1_out_0_tvalid;
wire m_ddc1_out_1_tready, m_ddc1_out_0_tready; wire m_ddc1_out_1_tready, m_ddc1_out_0_tready;
rfnoc_block_ddc #( rfnoc_block_ddc #(
.THIS_PORTID (6), .THIS_PORTID (6),
.CHDR_W (CHDR_W), .CHDR_W (CHDR_W),
@@ -954,8 +1012,6 @@ module rfnoc_image_core #(
.ce_clk (ddc1_ce_clk), .ce_clk (ddc1_ce_clk),
.rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]), .rfnoc_core_config (rfnoc_core_config[512*5-1:512*4]),
.rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]), .rfnoc_core_status (rfnoc_core_status[512*5-1:512*4]),
.s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_ddc1_in_1_tdata , s_ddc1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_ddc1_in_1_tlast , s_ddc1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_ddc1_in_1_tvalid, s_ddc1_in_0_tvalid}),
@@ -974,10 +1030,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready) .m_rfnoc_ctrl_tready (m_ddc1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// radio1 // radio1
// ---------------------------------------------------- //-----------------------------------
wire radio1_radio_clk; wire radio1_radio_clk;
wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ; wire [CHDR_W-1:0] s_radio1_in_1_tdata , s_radio1_in_0_tdata ;
wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ; wire s_radio1_in_1_tlast , s_radio1_in_0_tlast ;
@@ -989,25 +1045,25 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tready, m_radio1_out_0_tready; wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrl_port // ctrl_port
wire [ 1-1:0] radio1_m_ctrlport_req_wr; wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 1-1:0] radio1_m_ctrlport_req_rd; wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 20-1:0] radio1_m_ctrlport_req_addr; wire [ 19:0] radio1_m_ctrlport_req_addr;
wire [ 32-1:0] radio1_m_ctrlport_req_data; wire [ 31:0] radio1_m_ctrlport_req_data;
wire [ 4-1:0] radio1_m_ctrlport_req_byte_en; wire [ 3:0] radio1_m_ctrlport_req_byte_en;
wire [ 1-1:0] radio1_m_ctrlport_req_has_time; wire [ 0:0] radio1_m_ctrlport_req_has_time;
wire [ 64-1:0] radio1_m_ctrlport_req_time; wire [ 63:0] radio1_m_ctrlport_req_time;
wire [ 1-1:0] radio1_m_ctrlport_resp_ack; wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 2-1:0] radio1_m_ctrlport_resp_status; wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 32-1:0] radio1_m_ctrlport_resp_data; wire [ 31:0] radio1_m_ctrlport_resp_data;
// time_keeper // time_keeper
wire [ 64-1:0] radio1_radio_time; wire [ 63:0] radio1_radio_time;
// x300_radio // x300_radio
wire [ 64-1:0] radio1_radio_rx_data; wire [ 63:0] radio1_radio_rx_data;
wire [ 2-1:0] radio1_radio_rx_stb; wire [ 1:0] radio1_radio_rx_stb;
wire [ 2-1:0] radio1_radio_rx_running; wire [ 1:0] radio1_radio_rx_running;
wire [ 64-1:0] radio1_radio_tx_data; wire [ 63:0] radio1_radio_tx_data;
wire [ 2-1:0] radio1_radio_tx_stb; wire [ 1:0] radio1_radio_tx_stb;
wire [ 2-1:0] radio1_radio_tx_running; wire [ 1:0] radio1_radio_tx_running;
rfnoc_block_radio #( rfnoc_block_radio #(
.THIS_PORTID (7), .THIS_PORTID (7),
@@ -1020,7 +1076,6 @@ module rfnoc_image_core #(
.radio_clk (radio1_radio_clk), .radio_clk (radio1_radio_clk),
.rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]), .rfnoc_core_config (rfnoc_core_config[512*6-1:512*5]),
.rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]), .rfnoc_core_status (rfnoc_core_status[512*6-1:512*5]),
.m_ctrlport_req_wr (radio1_m_ctrlport_req_wr), .m_ctrlport_req_wr (radio1_m_ctrlport_req_wr),
.m_ctrlport_req_rd (radio1_m_ctrlport_req_rd), .m_ctrlport_req_rd (radio1_m_ctrlport_req_rd),
.m_ctrlport_req_addr (radio1_m_ctrlport_req_addr), .m_ctrlport_req_addr (radio1_m_ctrlport_req_addr),
@@ -1038,7 +1093,6 @@ module rfnoc_image_core #(
.radio_tx_data (radio1_radio_tx_data), .radio_tx_data (radio1_radio_tx_data),
.radio_tx_stb (radio1_radio_tx_stb), .radio_tx_stb (radio1_radio_tx_stb),
.radio_tx_running (radio1_radio_tx_running), .radio_tx_running (radio1_radio_tx_running),
.s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_radio1_in_1_tdata , s_radio1_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_radio1_in_1_tlast , s_radio1_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_radio1_in_1_tvalid, s_radio1_in_0_tvalid}),
@@ -1057,10 +1111,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_radio1_ctrl_tready) .m_rfnoc_ctrl_tready (m_radio1_ctrl_tready)
); );
//-----------------------------------
// ----------------------------------------------------
// replay0 // replay0
// ---------------------------------------------------- //-----------------------------------
wire replay0_mem_clk; wire replay0_mem_clk;
wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ; wire [CHDR_W-1:0] s_replay0_in_1_tdata , s_replay0_in_0_tdata ;
wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ; wire s_replay0_in_1_tlast , s_replay0_in_0_tlast ;
@@ -1072,51 +1126,51 @@ module rfnoc_image_core #(
wire m_replay0_out_1_tready, m_replay0_out_0_tready; wire m_replay0_out_1_tready, m_replay0_out_0_tready;
// axi_ram // axi_ram
wire [ 1-1:0] replay0_axi_rst; wire [ 0:0] replay0_axi_rst;
wire [ 4-1:0] replay0_m_axi_awid; wire [ 3:0] replay0_m_axi_awid;
wire [128-1:0] replay0_m_axi_awaddr; wire [ 127:0] replay0_m_axi_awaddr;
wire [ 32-1:0] replay0_m_axi_awlen; wire [ 31:0] replay0_m_axi_awlen;
wire [ 12-1:0] replay0_m_axi_awsize; wire [ 11:0] replay0_m_axi_awsize;
wire [ 8-1:0] replay0_m_axi_awburst; wire [ 7:0] replay0_m_axi_awburst;
wire [ 4-1:0] replay0_m_axi_awlock; wire [ 3:0] replay0_m_axi_awlock;
wire [ 16-1:0] replay0_m_axi_awcache; wire [ 15:0] replay0_m_axi_awcache;
wire [ 12-1:0] replay0_m_axi_awprot; wire [ 11:0] replay0_m_axi_awprot;
wire [ 16-1:0] replay0_m_axi_awqos; wire [ 15:0] replay0_m_axi_awqos;
wire [ 16-1:0] replay0_m_axi_awregion; wire [ 15:0] replay0_m_axi_awregion;
wire [ 4-1:0] replay0_m_axi_awuser; wire [ 3:0] replay0_m_axi_awuser;
wire [ 4-1:0] replay0_m_axi_awvalid; wire [ 3:0] replay0_m_axi_awvalid;
wire [ 4-1:0] replay0_m_axi_awready; wire [ 3:0] replay0_m_axi_awready;
wire [256-1:0] replay0_m_axi_wdata; wire [ 255:0] replay0_m_axi_wdata;
wire [ 32-1:0] replay0_m_axi_wstrb; wire [ 31:0] replay0_m_axi_wstrb;
wire [ 4-1:0] replay0_m_axi_wlast; wire [ 3:0] replay0_m_axi_wlast;
wire [ 4-1:0] replay0_m_axi_wuser; wire [ 3:0] replay0_m_axi_wuser;
wire [ 4-1:0] replay0_m_axi_wvalid; wire [ 3:0] replay0_m_axi_wvalid;
wire [ 4-1:0] replay0_m_axi_wready; wire [ 3:0] replay0_m_axi_wready;
wire [ 4-1:0] replay0_m_axi_bid; wire [ 3:0] replay0_m_axi_bid;
wire [ 8-1:0] replay0_m_axi_bresp; wire [ 7:0] replay0_m_axi_bresp;
wire [ 4-1:0] replay0_m_axi_buser; wire [ 3:0] replay0_m_axi_buser;
wire [ 4-1:0] replay0_m_axi_bvalid; wire [ 3:0] replay0_m_axi_bvalid;
wire [ 4-1:0] replay0_m_axi_bready; wire [ 3:0] replay0_m_axi_bready;
wire [ 4-1:0] replay0_m_axi_arid; wire [ 3:0] replay0_m_axi_arid;
wire [128-1:0] replay0_m_axi_araddr; wire [ 127:0] replay0_m_axi_araddr;
wire [ 32-1:0] replay0_m_axi_arlen; wire [ 31:0] replay0_m_axi_arlen;
wire [ 12-1:0] replay0_m_axi_arsize; wire [ 11:0] replay0_m_axi_arsize;
wire [ 8-1:0] replay0_m_axi_arburst; wire [ 7:0] replay0_m_axi_arburst;
wire [ 4-1:0] replay0_m_axi_arlock; wire [ 3:0] replay0_m_axi_arlock;
wire [ 16-1:0] replay0_m_axi_arcache; wire [ 15:0] replay0_m_axi_arcache;
wire [ 12-1:0] replay0_m_axi_arprot; wire [ 11:0] replay0_m_axi_arprot;
wire [ 16-1:0] replay0_m_axi_arqos; wire [ 15:0] replay0_m_axi_arqos;
wire [ 16-1:0] replay0_m_axi_arregion; wire [ 15:0] replay0_m_axi_arregion;
wire [ 4-1:0] replay0_m_axi_aruser; wire [ 3:0] replay0_m_axi_aruser;
wire [ 4-1:0] replay0_m_axi_arvalid; wire [ 3:0] replay0_m_axi_arvalid;
wire [ 4-1:0] replay0_m_axi_arready; wire [ 3:0] replay0_m_axi_arready;
wire [ 4-1:0] replay0_m_axi_rid; wire [ 3:0] replay0_m_axi_rid;
wire [256-1:0] replay0_m_axi_rdata; wire [ 255:0] replay0_m_axi_rdata;
wire [ 8-1:0] replay0_m_axi_rresp; wire [ 7:0] replay0_m_axi_rresp;
wire [ 4-1:0] replay0_m_axi_rlast; wire [ 3:0] replay0_m_axi_rlast;
wire [ 4-1:0] replay0_m_axi_ruser; wire [ 3:0] replay0_m_axi_ruser;
wire [ 4-1:0] replay0_m_axi_rvalid; wire [ 3:0] replay0_m_axi_rvalid;
wire [ 4-1:0] replay0_m_axi_rready; wire [ 3:0] replay0_m_axi_rready;
rfnoc_block_replay #( rfnoc_block_replay #(
.THIS_PORTID (8), .THIS_PORTID (8),
@@ -1131,7 +1185,6 @@ module rfnoc_image_core #(
.mem_clk (replay0_mem_clk), .mem_clk (replay0_mem_clk),
.rfnoc_core_config (rfnoc_core_config[512*7-1:512*6]), .rfnoc_core_config (rfnoc_core_config[512*7-1:512*6]),
.rfnoc_core_status (rfnoc_core_status[512*7-1:512*6]), .rfnoc_core_status (rfnoc_core_status[512*7-1:512*6]),
.axi_rst (replay0_axi_rst), .axi_rst (replay0_axi_rst),
.m_axi_awid (replay0_m_axi_awid), .m_axi_awid (replay0_m_axi_awid),
.m_axi_awaddr (replay0_m_axi_awaddr), .m_axi_awaddr (replay0_m_axi_awaddr),
@@ -1177,7 +1230,6 @@ module rfnoc_image_core #(
.m_axi_ruser (replay0_m_axi_ruser), .m_axi_ruser (replay0_m_axi_ruser),
.m_axi_rvalid (replay0_m_axi_rvalid), .m_axi_rvalid (replay0_m_axi_rvalid),
.m_axi_rready (replay0_m_axi_rready), .m_axi_rready (replay0_m_axi_rready),
.s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }), .s_rfnoc_chdr_tdata ({s_replay0_in_1_tdata , s_replay0_in_0_tdata }),
.s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }), .s_rfnoc_chdr_tlast ({s_replay0_in_1_tlast , s_replay0_in_0_tlast }),
.s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}), .s_rfnoc_chdr_tvalid ({s_replay0_in_1_tvalid, s_replay0_in_0_tvalid}),
@@ -1196,10 +1248,10 @@ module rfnoc_image_core #(
.m_rfnoc_ctrl_tready (m_replay0_ctrl_tready) .m_rfnoc_ctrl_tready (m_replay0_ctrl_tready)
); );
//---------------------------------------------------------------------------
// ----------------------------------------------------
// Static Router // Static Router
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_duc0_in_0_tdata = m_ep0_out0_tdata; assign s_duc0_in_0_tdata = m_ep0_out0_tdata;
assign s_duc0_in_0_tlast = m_ep0_out0_tlast; assign s_duc0_in_0_tlast = m_ep0_out0_tlast;
assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid; assign s_duc0_in_0_tvalid = m_ep0_out0_tvalid;
@@ -1281,9 +1333,10 @@ module rfnoc_image_core #(
assign m_replay0_out_1_tready = s_ep5_in0_tready; assign m_replay0_out_1_tready = s_ep5_in0_tready;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Unused Ports // Unused Ports
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign s_radio0_in_1_tdata = {CHDR_W{1'b0}}; assign s_radio0_in_1_tdata = {CHDR_W{1'b0}};
assign s_radio0_in_1_tlast = 1'b0; assign s_radio0_in_1_tlast = 1'b0;
assign s_radio0_in_1_tvalid = 1'b0; assign s_radio0_in_1_tvalid = 1'b0;
@@ -1293,9 +1346,11 @@ module rfnoc_image_core #(
assign m_ep1_out0_tready = 1'b1; assign m_ep1_out0_tready = 1'b1;
assign m_ep3_out0_tready = 1'b1; assign m_ep3_out0_tready = 1'b1;
// ----------------------------------------------------
//---------------------------------------------------------------------------
// Clock Domains // Clock Domains
// ---------------------------------------------------- //---------------------------------------------------------------------------
assign radio0_radio_clk = radio_clk; assign radio0_radio_clk = radio_clk;
assign ddc0_ce_clk = ce_clk; assign ddc0_ce_clk = ce_clk;
assign duc0_ce_clk = ce_clk; assign duc0_ce_clk = ce_clk;
@@ -1305,9 +1360,10 @@ module rfnoc_image_core #(
assign replay0_mem_clk = dram_clk; assign replay0_mem_clk = dram_clk;
// ---------------------------------------------------- //---------------------------------------------------------------------------
// IO Port Connection // IO Port Connection
// ---------------------------------------------------- //---------------------------------------------------------------------------
// Master/Slave Connections: // Master/Slave Connections:
assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr; assign m_ctrlport_radio0_req_wr = radio0_m_ctrlport_req_wr;
assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd; assign m_ctrlport_radio0_req_rd = radio0_m_ctrlport_req_rd;
@@ -1397,3 +1453,6 @@ module rfnoc_image_core #(
assign radio1_radio_time = radio_time; assign radio1_radio_time = radio_time;
endmodule endmodule
`default_nettype wire
top/x300/x310_rfnoc_image_core.vh
+21
View File
@@ -0,0 +1,21 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Header: rfnoc_image_core.vh (for x300)
//
// Description:
//
// This is the header file for the RFNoC Image Core.
//
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:07.779170
// Source: x310_rfnoc_image_core.yml
// Source SHA256: 7a01e3b4aa95b9e5b59f627d5a7d3f27c16afb4bb6bdad1f7fb9a624fb4b9647
//
`define CHDR_WIDTH 64
`define RFNOC_PROTOVER { 8'd1, 8'd0 }