fpga: lib: Add modports to SV AXI-Stream blocks

Original-commit: da46dddbebab2ddb1f25f2f200431c2299b395f4

lib/axi4s_sv/axi4s_fifo.sv

@@ -16,8 +16,8 @@ module axi4s_fifo #(
  ) (
   // Clock domain: i.clk (o.clk is unused)
   input logic clear=1'b0,
-  interface   i,  // AxiStreamIf or AxiStreamPacketIf
-  interface   o,  // AxiStreamIf or AxiStreamPacketIf
+  interface.slave  i,  // AxiStreamIf or AxiStreamPacketIf
+  interface.master o,  // AxiStreamIf or AxiStreamPacketIf
   output logic [15:0] space,
   output logic [15:0] occupied
 );