From 4188b6ccbcd0bcdcb0e9936f02c1d453f4edd3d9 Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Fri, 16 Apr 2021 15:02:24 -0500 Subject: [PATCH] fpga: lib: Add modports to SV AXI-Stream blocks Original-commit: da46dddbebab2ddb1f25f2f200431c2299b395f4 --- lib/axi4s_sv/axi4s_add_bytes.sv | 4 ++-- lib/axi4s_sv/axi4s_fifo.sv | 4 ++-- lib/axi4s_sv/axi4s_remove_bytes.sv | 4 ++-- lib/axi4s_sv/axi4s_width_conv.sv | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/lib/axi4s_sv/axi4s_add_bytes.sv b/lib/axi4s_sv/axi4s_add_bytes.sv index 3989422..57124a0 100644 --- a/lib/axi4s_sv/axi4s_add_bytes.sv +++ b/lib/axi4s_sv/axi4s_add_bytes.sv @@ -29,8 +29,8 @@ module axi4s_add_bytes #( int ADD_BYTES = 6, bit SYNC = 1 ) ( - interface i, // AxiStreamIf or AxiStreamPacketIf - interface o // AxiStreamIf or AxiStreamPacketIf + interface.slave i, // AxiStreamIf or AxiStreamPacketIf + interface.master o // AxiStreamIf or AxiStreamPacketIf ); localparam BYTES_PER_WORD = i.DATA_WIDTH/8; diff --git a/lib/axi4s_sv/axi4s_fifo.sv b/lib/axi4s_sv/axi4s_fifo.sv index 647e1dc..c3c7199 100644 --- a/lib/axi4s_sv/axi4s_fifo.sv +++ b/lib/axi4s_sv/axi4s_fifo.sv @@ -16,8 +16,8 @@ module axi4s_fifo #( ) ( // Clock domain: i.clk (o.clk is unused) input logic clear=1'b0, - interface i, // AxiStreamIf or AxiStreamPacketIf - interface o, // AxiStreamIf or AxiStreamPacketIf + interface.slave i, // AxiStreamIf or AxiStreamPacketIf + interface.master o, // AxiStreamIf or AxiStreamPacketIf output logic [15:0] space, output logic [15:0] occupied ); diff --git a/lib/axi4s_sv/axi4s_remove_bytes.sv b/lib/axi4s_sv/axi4s_remove_bytes.sv index 4321d87..382cdb1 100644 --- a/lib/axi4s_sv/axi4s_remove_bytes.sv +++ b/lib/axi4s_sv/axi4s_remove_bytes.sv @@ -35,8 +35,8 @@ module axi4s_remove_bytes #( REM_START=0, REM_END=8 )( - interface i, // AxiStreamIf or AxiStreamPacketIf - interface o // AxiStreamIf or AxiStreamPacketIf + interface.slave i, // AxiStreamIf or AxiStreamPacketIf + interface.master o // AxiStreamIf or AxiStreamPacketIf ); localparam BYTES_PER_WORD = i.DATA_WIDTH/8; diff --git a/lib/axi4s_sv/axi4s_width_conv.sv b/lib/axi4s_sv/axi4s_width_conv.sv index f05f704..0660ee9 100644 --- a/lib/axi4s_sv/axi4s_width_conv.sv +++ b/lib/axi4s_sv/axi4s_width_conv.sv @@ -25,8 +25,8 @@ module axi4s_width_conv #( bit O_USER_TRAILING_BYTES = 0, bit SYNC_CLKS = 1 ) ( - interface i, // AxiStreamIf or AxiStreamPacketIf - interface o // AxiStreamIf or AxiStreamPacketIf + interface.slave i, // AxiStreamIf or AxiStreamPacketIf + interface.master o // AxiStreamIf or AxiStreamPacketIf ); localparam IWIDTH =i.DATA_WIDTH;