fpga: lib: Add modports to SV AXI-Stream blocks

Original-commit: da46dddbebab2ddb1f25f2f200431c2299b395f4
2021-06-03 11:26:54 -05:00
parent d6ca4f01fc
commit 4188b6ccbc
4 changed files with 8 additions and 8 deletions
@@ -29,8 +29,8 @@ module axi4s_add_bytes #(
  int ADD_BYTES = 6,
  bit SYNC      = 1
 ) (
-   interface   i,  // AxiStreamIf or AxiStreamPacketIf
-   interface   o   // AxiStreamIf or AxiStreamPacketIf
+   interface.slave  i,  // AxiStreamIf or AxiStreamPacketIf
+   interface.master o   // AxiStreamIf or AxiStreamPacketIf
 );

  localparam BYTES_PER_WORD = i.DATA_WIDTH/8;