fpga: lib: Add modports to SV AXI-Stream blocks

Original-commit: da46dddbebab2ddb1f25f2f200431c2299b395f4

lib/axi4s_sv/axi4s_add_bytes.sv

@@ -29,8 +29,8 @@ module axi4s_add_bytes #(
   int ADD_BYTES = 6,
   bit SYNC      = 1
 ) (
-   interface   i,  // AxiStreamIf or AxiStreamPacketIf
-   interface   o   // AxiStreamIf or AxiStreamPacketIf
+   interface.slave  i,  // AxiStreamIf or AxiStreamPacketIf
+   interface.master o   // AxiStreamIf or AxiStreamPacketIf
 );
 
   localparam BYTES_PER_WORD = i.DATA_WIDTH/8;

lib/axi4s_sv/axi4s_fifo.sv

@@ -16,8 +16,8 @@ module axi4s_fifo #(
  ) (
   // Clock domain: i.clk (o.clk is unused)
   input logic clear=1'b0,
-  interface   i,  // AxiStreamIf or AxiStreamPacketIf
-  interface   o,  // AxiStreamIf or AxiStreamPacketIf
+  interface.slave  i,  // AxiStreamIf or AxiStreamPacketIf
+  interface.master o,  // AxiStreamIf or AxiStreamPacketIf
   output logic [15:0] space,
   output logic [15:0] occupied
 );

lib/axi4s_sv/axi4s_remove_bytes.sv

@@ -35,8 +35,8 @@ module axi4s_remove_bytes #(
   REM_START=0,
   REM_END=8
 )(
-   interface   i,  // AxiStreamIf or AxiStreamPacketIf
-   interface   o   // AxiStreamIf or AxiStreamPacketIf
+   interface.slave  i,  // AxiStreamIf or AxiStreamPacketIf
+   interface.master o   // AxiStreamIf or AxiStreamPacketIf
 );
 
   localparam BYTES_PER_WORD = i.DATA_WIDTH/8;

lib/axi4s_sv/axi4s_width_conv.sv

@@ -25,8 +25,8 @@ module axi4s_width_conv #(
   bit    O_USER_TRAILING_BYTES = 0,
   bit    SYNC_CLKS = 1
 ) (
-   interface   i,  // AxiStreamIf or AxiStreamPacketIf
-   interface   o   // AxiStreamIf or AxiStreamPacketIf
+   interface.slave   i,  // AxiStreamIf or AxiStreamPacketIf
+   interface.master  o   // AxiStreamIf or AxiStreamPacketIf
 );
 
   localparam IWIDTH =i.DATA_WIDTH;