miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: lib: add register stage in ipv4 chdr adapter

Browse Source 
Original-commit: 2b9504d84d8f8e5dd7156498b4c8b5db5a2c84da
This commit is contained in:
Max Köhler
2025-02-05 09:14:26 -06:00
committed by Wade Fife
parent 8aefaa7582
commit 40ce83817a
2 changed files with 52 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/rfnoc/xport_sv/eth_ipv4_chdr_adapter.sv
+1 -1
View File
@@ -500,7 +500,7 @@ module eth_ipv4_chdr_adapter #(
c2e3.tready = c2e3_tready;
end
axi_mux #(
.SIZE(2), .PRIO(0), .WIDTH(ENET_W+ENET_USER_W), .PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
.SIZE(2), .PRIO(0), .WIDTH(ENET_W+ENET_USER_W), .PRE_FIFO_SIZE(1), .POST_FIFO_SIZE(1)
) eth_mux_i (
.clk(eth_rx.clk), .reset(eth_rx.rst), .clear(1'b0),
.i_tdata({c2e3.tuser, c2e3.tdata, v2e3.tuser, v2e3.tdata}), .i_tlast({c2e3.tlast, v2e3.tlast}),