fpga: x400: Refactor CPLDs build process
This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes. Original-commit: e1ce4565dbc7336ee806adce7c087bda4fcc77ae
This commit is contained in:
Humberto Jimenez
committed by
Wade Fife
Wade Fife
parent
119abe6800
commit
4082066a6f
@@ -4,87 +4,98 @@
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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GIT_HASH = $(shell ../../../../../tools/scripts/git-hash.sh)
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP ZBX CPLD Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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##
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##Output:
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## build/<device-id>/usrp_zbx_cpld.pof: Bitstream to use with JTAG programmer
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## build/<device-id>/usrp_zbx_cpld.svf: Bitstream to use with PS JTAG engine (background programming)
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## build/<device-id>/usrp_zbx_cpld.rpd: Bitstream to use via reconfig engine
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## build/<device-id>/usrp_zbx_cpld_isp_off.svf: Bitstream to use with JTAG test points (initial programming)
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build: cpld_defaults ip
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@echo -ne "\n---- Make: Synthesis ...\n\n";
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@quartus_map zbx_top_cpld --verilog_macro="GIT_HASH=32'h$(GIT_HASH)";
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@echo -ne "\n\n---- Make: Implementation ...\n\n";
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@quartus_fit zbx_top_cpld;
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@echo -ne "\n\n---- Make: Analyzing timing ...\n\n";
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@quartus_sta zbx_top_cpld;
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@# grep for unconstrained path warning
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@grep "332102" output_files/zbx_top_cpld.sta.rpt; \
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if [ $$? -eq 0 ]; then false; else true; fi
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@# grep for timing closure critical warning
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@grep "332148" output_files/zbx_top_cpld.sta.rpt; \
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if [ $$? -eq 0 ]; then false; else true; fi
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@# expect no warnings
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@grep -iw "warning" output_files/zbx_top_cpld.sta.rpt; \
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if [ $$? -eq 0 ]; then false; else true; fi
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@# expect no critical warning except "review power analyzer report file"
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@grep -i "critical warning" output_files/* | grep -v 16562; \
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if [ $$? -eq 0 ]; then false; else true; fi
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@echo -ne "\n\n---- Make: Generating bitfile...\n\n";
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@quartus_asm zbx_top_cpld;
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@echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP enabled)...\n\n";
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@quartus_cpf --convert \
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--frequency 12.5MHz \
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--voltage 2.5 \
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--operation p \
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./output_files/zbx_top_cpld.pof ./output_files/zbx_top_cpld_isp_on.svf -o background_programming=on;
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@echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP disabled)...\n\n";
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@quartus_cpf --convert \
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--frequency 12.5MHz \
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--voltage 2.5 \
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--operation p \
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./output_files/zbx_top_cpld.pof ./output_files/zbx_top_cpld_isp_off.svf;
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@echo -ne "\n\n---- Make: Converting bitfile to rdp format...\n\n";
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@quartus_cpf -c raw_conversion.cof
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@echo -ne "\n\n---- Make: Copy final files...\n\n";
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@mkdir -p build
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@cp output_files/zbx_top_cpld.pof build/usrp_zbx_cpld.pof
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@cp output_files/zbx_top_cpld_isp_off.svf build/usrp_zbx_cpld.svf
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@cp output_files/zbx_top_cpld_isp_on.svf build/usrp_zbx_cpld_isp_on.svf
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@cp output_files/zbx_top_cpld_converted_cfm0_auto.rpd build/usrp_zbx_cpld.rpd
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@echo -ne "\n\n---- Make: ZBX CPLD ready!\n";
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@echo -ne " Use build/usrp_zbx_cpld.pof via JTAG programmer or\n"
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@echo -ne " build/usrp_zbx_cpld.svf (ISP off) via MB CPLD JTAG engine or\n"
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@echo -ne " build/usrp_zbx_cpld.rpd via reconfig engine or\n"
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@echo -ne " build/usrp_zbx_cpld_isp_on.rpd via MB CPLD JTAG engine.\n"
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# Definitions
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10M04_ID = "10M04SAU324I7G"
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clean:
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@echo -ne "\nCleaning ZBX CPLD...\n";
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@git clean -Xdf
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QSYS_PATH=$(subst \,/,$(QUARTUS_ROOTDIR))/sopc_builder/bin
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ROOT_DIR:=$(shell dirname $(realpath $(firstword $(MAKEFILE_LIST))))
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REGS_PY_FILE=$(ROOT_DIR)/../../../../../../../host/lib/ic_reg_maps/gen_zbx_cpld_regs.py
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REGS_PY_MODULE=register_endpoints/memory_init_files/zbx_cpld_regs_t.py
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$(REGS_PY_MODULE): $(REGS_PY_FILE)
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@python3 $(REGS_PY_FILE) $(REGS_PY_MODULE)
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# Target specific variables
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ZBX_CPLD_10M04: DEFS = VARIANT_`echo $(10M04_ID) | cut -c1-5`=1
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# Using one of the files as a dependency (all files are generated at the same time)
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INIT_FILES := $(ROOT_DIR)/register_endpoints/memory_init_files/rx0_path_defaults.hex
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INIT_FILES := register_endpoints/memory_init_files/rx0_path_defaults.hex
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$(INIT_FILES): register_endpoints/memory_init_files/gen_defaults.py $(REGS_PY_MODULE)
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@python3 $(ROOT_DIR)/register_endpoints/memory_init_files/gen_defaults.py
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TARGET = bin
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TOP ?= zbx_top_cpld
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cpld_defaults: $(INIT_FILES)
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# pre_build()
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pre_build = @\
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mkdir -p build-$@/register_endpoints/memory_init_files/; \
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cp -rf register_endpoints/memory_init_files/*.hex build-$@/register_endpoints/memory_init_files/
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ip: ip/flash/on_chip_flash/simulation/on_chip_flash.v \
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ip/osc/osc/simulation/osc.v
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@make -C ../../../cpld ip
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# quartus_build($1=Device, $2=Definitions)
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quartus_build = make -f Makefile.zbx_cpld.inc $(TARGET) NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" POST_STA_TCL="ps_cs_analysis.tcl"
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ip/flash/on_chip_flash/simulation/on_chip_flash.v:
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$(QSYS_PATH)/qsys-generate ip/flash/on_chip_flash.qsys --simulation=VERILOG
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# quartus_ip($1=Device, $2=Definitions)
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quartus_ip = make -f Makefile.zbx_cpld.inc quar_ip NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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ip/osc/osc/simulation/osc.v:
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$(QSYS_PATH)/qsys-generate ip/osc/osc.qsys --simulation=VERILOG
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# post_build($1=Artifact Name)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p build/; \
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echo "Exporting bitstream files..."; \
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cp build-$@/output_files/$(TOP).pof build/$(1).pof; \
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cp build-$@/output_files/$(TOP)_isp_off.svf build/$(1)_isp_off.svf; \
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cp build-$@/output_files/$(TOP)_isp_on.svf build/$(1).svf; \
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cp build-$@/output_files/$(TOP)_converted_cfm0_auto.rpd build/$(1).rpd; \
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echo -ne "\n\n---- Make: MB CPLD ready!\n"; \
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echo -ne " Use build/$(1).pof via JTAG programmer or\n"; \
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echo -ne " build/$(1).svf (ISP on) via PS JTAG-engine (background programming) or\n"; \
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echo -ne " build/$(1).rpd via reconfig engine or\n"; \
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echo -ne " build/$(1)_isp_off.svf via JTAG test points (initial programming)\n";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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all: build
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##
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##Supported Targets
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##-----------------
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all: ZBX_CPLD_10M04 ##(Default target)
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##ZBX_CPLD_10M04: ZBX CPLD targeted to 10M04SAU169I7G.
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ZBX_CPLD_10M04: $(INIT_FILES)
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$(call pre_build)
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$(call quartus_build,$(10M04_ID),$(DEFS))
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$(call post_build,"usrp_zbx_cpld")
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ZBX_CPLD_IP: ##Build IPs only, needed for simulation.
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@# Building only ZBX_CPLD_10M04 IP
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$(call quartus_ip,$(10M04_ID),$(DEFS))
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$(INIT_FILES):
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make -f Makefile.zbx_cpld.inc cpld_defaults
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clean: ##Clean up all target build outputs.
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@echo -ne "\nCleaning targets and git repo...\n";
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@rm -rf build-ZBX_CPLD*
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@rm -rf build
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@git clean -Xdf
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cleanall: ##Clean up all target and ip build outputs.
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@echo -ne "\nCleaning targets, IP, and git repo...\n";
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@rm -rf build-ZBX_CPLD*
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@rm -rf build
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@rm -rf build-ip
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@git clean -Xdf
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help: ##Show this help message.
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@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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##
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##Supported Options
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##-----------------
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##
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.PHONY: all build clean ip
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@@ -0,0 +1,68 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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##################################################
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# Project Setup
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##################################################
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# TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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##################################################
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# Include other makefiles
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##################################################
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PROJECT_DIR = $(abspath .)
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BASE_DIR = $(abspath ../../../../)
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IP_DIR = $(abspath ./ip)
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include $(BASE_DIR)/../tools/make/quartus_design_builder.mak
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# Include IP directory
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include $(IP_DIR)/Makefile.inc
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# Define VERILOG_DEFS for macros definition
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VERILOG_DEFS=$(EXTRA_DEFS) $(GIT_HASH_VERILOG_DEF)
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# Memory initialization files (CPLD default values)
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REGS_PY_FILE=$(PROJECT_DIR)/../../../../../../../host/lib/ic_reg_maps/gen_zbx_cpld_regs.py
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INIT_FILES_DIR=$(PROJECT_DIR)/register_endpoints/memory_init_files/
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REGS_PY_MODULE=$(INIT_FILES_DIR)/zbx_cpld_regs_t.py
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$(REGS_PY_MODULE): $(REGS_PY_FILE)
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@python3 $(REGS_PY_FILE) $(REGS_PY_MODULE)
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# Using one of the files as a dependency (all files are generated at the same time)
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INIT_FILES := $(INIT_FILES_DIR)/rx0_path_defaults.hex
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$(INIT_FILES): $(REGS_PY_MODULE) $(INIT_FILES_DIR)/gen_defaults.py
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@python3 $(INIT_FILES_DIR)/gen_defaults.py
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cpld_defaults: .prereqs $(INIT_FILES)
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@echo "Initialization files DONE ..."
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bin: .prereqs
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$(call BUILD_QUARTUS_DESIGN,$(TOP_MODULE),$(ARCH),$(PART_ID),$(PROJECT_DIR),$(BUILD_DIR),$(POST_TCL_SCRIPT),0)
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@\
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pushd $(BUILD_DIR); \
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echo "Converting bitfile to svf format (ISP enabled)..."; \
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quartus_cpf --convert \
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--frequency 12.5MHz \
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--voltage 2.5 \
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--operation p \
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output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE)_isp_on.svf -o background_programming=on; \
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echo "Converting bitfile to svf format (ISP disabled)..."; \
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quartus_cpf --convert \
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--frequency 12.5MHz \
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--voltage 2.5 \
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--operation p \
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output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE)_isp_off.svf; \
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echo "Converting bitfile to rpd format..."; \
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quartus_cpf -c raw_conversion.cof; \
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popd;
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quar_ip: .prereqs ip
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@echo "IP Build DONE ..."
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@@ -1486,9 +1486,9 @@ This enum is used to create the constants held in the basic registers in both ve
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<tr valign="top">
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<td class='value'>553848841</td>
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<td class='value'>554767892</td>
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<td class='l'>0x21031009</td>
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<td class='l'>0x21111614</td>
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<td class="l" style="text-align: left;">
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<p class="name"><a name='BASIC_REGS_REGMAP|BASIC_REGISTERS_VALUES|CPLD_REVISION'></a>CPLD_REVISION</p>
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@@ -6914,10 +6914,12 @@ Offers ability to enable or disable the PLL reference clock.
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<a name="RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM"></a>
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<h3 class="enum">FLASH_PRIMARY_IMAGE_ADDR_ENUM Enumeration</h3>
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Those values are the start and end address of the CFM image flash
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sector from Intel's On-Chip Flash IP Generator. Note that the values
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given in the IP generator are byte based where the values of this enum
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are U32 based (divided by 4).
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These values are the start and end address of the CFM image flash
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sector from Intel's On-Chip Flash IP Generator.
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Be aware that three different values exist per each of the two
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supported MAX10 variants: 10M04 and 10M08
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Note that the values given in the IP generator are byte based where
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the values of this enum are U32 based (divided by 4).
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<table class="enum" border="0" cellspacing="0" cellpadding="0">
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<tr class="header" valign="center">
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@@ -6941,7 +6943,20 @@ Those values are the start and end address of the CFM image flash
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<td class='l'>0x01000</td>
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<td class="l" style="text-align: left;">
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<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT</p>
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<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04</p>
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</td>
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</tr>
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<tr valign="top">
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<td class='value'>8192</td>
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<td class='l'>0x02000</td>
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<td class="l" style="text-align: left;">
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<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08'></a>FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08</p>
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</td>
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@@ -6954,7 +6969,20 @@ Those values are the start and end address of the CFM image flash
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<td class='l'>0x09C00</td>
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<td class="l" style="text-align: left;">
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<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR'></a>FLASH_PRIMARY_IMAGE_START_ADDR</p>
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<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_10M04'></a>FLASH_PRIMARY_IMAGE_START_ADDR_10M04</p>
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</td>
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</tr>
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<tr valign="top">
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<td class='value'>44032</td>
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<td class='l'>0x0AC00</td>
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<td class="l" style="text-align: left;">
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<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_START_ADDR_10M08'></a>FLASH_PRIMARY_IMAGE_START_ADDR_10M08</p>
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</td>
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@@ -6967,7 +6995,20 @@ Those values are the start and end address of the CFM image flash
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<td class='l'>0x127FF</td>
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<td class="l" style="text-align: left;">
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<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR'></a>FLASH_PRIMARY_IMAGE_END_ADDR</p>
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<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR_10M04'></a>FLASH_PRIMARY_IMAGE_END_ADDR_10M04</p>
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</td>
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</tr>
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<tr valign="top">
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<td class='value'>79871</td>
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<td class='l'>0x137FF</td>
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<td class="l" style="text-align: left;">
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<p class="name"><a name='RECONFIG_REGMAP|FLASH_PRIMARY_IMAGE_ADDR_ENUM|FLASH_PRIMARY_IMAGE_END_ADDR_10M08'></a>FLASH_PRIMARY_IMAGE_END_ADDR_10M08</p>
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</td>
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@@ -7357,9 +7398,12 @@ Total Offset =</td></tr>
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<p>Defines the sector to be erased. Has to be set latest with the
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write access which starts the erase operation by strobing
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<a href="#RECONFIG_REGMAP|FLASH_CONTROL_REG|FLASH_ERASE_STB">FLASH_ERASE_STB</a>.<br>
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If the flash is configured to support memory initialization (see
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<a href="#RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_MEM_INIT_ENABLED">FLASH_MEM_INIT_ENABLED</a> flag) the sectors 2 to 4 have to be erased.
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If the flag is not asserted only sector 4 has to be erased.</p>
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With 10M04 variants, if the flash is configured to support memory
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initialization (see <a href="#RECONFIG_REGMAP|FLASH_STATUS_REG|FLASH_MEM_INIT_ENABLED">FLASH_MEM_INIT_ENABLED</a> flag) the sectors 2
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to 4 have to be erased. If the flag is not asserted only sector 4
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has to be erased.
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With 10M08 variants, the sectors to be erased are 3 to 5 when
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using memory initialization or only sector 5 otherwise.</p>
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</td>
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</tr>
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@@ -0,0 +1,25 @@
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#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
|
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#
|
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include $(IP_DIR)/on_chip_flash/Makefile.inc
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include $(IP_DIR)/osc/Makefile.inc
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include $(IP_DIR)/clkctrl/Makefile.inc
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IP_SRCS = \
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$(IP_ON_CHIP_FLASH_SRCS) \
|
||||
$(IP_OSC_SRCS) \
|
||||
$(IP_CLKCTRL_SRCS)
|
||||
|
||||
|
||||
IP_OUTPUTS = \
|
||||
$(IP_ON_CHIP_FLASH_OUTS) \
|
||||
$(IP_OSC_OUTS) \
|
||||
$(IP_CLKCTRL_OUTS)
|
||||
|
||||
|
||||
ip: $(IP_OUTPUTS)
|
||||
|
||||
.PHONY: ip
|
||||
@@ -0,0 +1,3 @@
|
||||
# generate files
|
||||
clkctrl/
|
||||
clkctrl.sopcinfo
|
||||
@@ -0,0 +1,16 @@
|
||||
#
|
||||
# Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/quartus_ip_builder.mak
|
||||
|
||||
IP_CLKCTRL_SRCS = \
|
||||
$(IP_BUILD_DIR)/clkctrl/clkctrl.qsys
|
||||
|
||||
IP_CLKCTRL_OUTS = \
|
||||
$(IP_BUILD_DIR)/clkctrl/clkctrl.sopcinfo
|
||||
|
||||
$(IP_CLKCTRL_SRCS) $(IP_CLKCTRL_OUTS) : $(IP_DIR)/clkctrl/clkctrl.qsys
|
||||
$(call BUILD_QUARTUS_IP,clkctrl,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR))
|
||||
@@ -0,0 +1,73 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<system name="$${FILENAME}">
|
||||
<component
|
||||
name="$${FILENAME}"
|
||||
displayName="$${FILENAME}"
|
||||
version="1.0"
|
||||
description=""
|
||||
tags="INTERNAL_COMPONENT=true"
|
||||
categories="" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element altclkctrl_0
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<parameter name="device" value="10M04SAU324I7G" />
|
||||
<parameter name="deviceFamily" value="MAX 10" />
|
||||
<parameter name="deviceSpeedGrade" value="7" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
<parameter name="generateLegacySim" value="false" />
|
||||
<parameter name="generationId" value="0" />
|
||||
<parameter name="globalResetBus" value="false" />
|
||||
<parameter name="hdlLanguage" value="VERILOG" />
|
||||
<parameter name="hideFromIPCatalog" value="true" />
|
||||
<parameter name="lockedInterfaceDefinition" value="" />
|
||||
<parameter name="maxAdditionalLatency" value="1" />
|
||||
<parameter name="projectName" value="" />
|
||||
<parameter name="sopcBorderPoints" value="false" />
|
||||
<parameter name="systemHash" value="0" />
|
||||
<parameter name="testBenchDutName" value="" />
|
||||
<parameter name="timeStamp" value="0" />
|
||||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface
|
||||
name="altclkctrl_input"
|
||||
internal="altclkctrl_0.altclkctrl_input"
|
||||
type="conduit"
|
||||
dir="end">
|
||||
<port name="inclk" internal="inclk" />
|
||||
<port name="ena" internal="ena" />
|
||||
</interface>
|
||||
<interface
|
||||
name="altclkctrl_output"
|
||||
internal="altclkctrl_0.altclkctrl_output"
|
||||
type="conduit"
|
||||
dir="end">
|
||||
<port name="outclk" internal="outclk" />
|
||||
</interface>
|
||||
<module
|
||||
name="altclkctrl_0"
|
||||
kind="altclkctrl"
|
||||
version="18.1"
|
||||
enabled="1"
|
||||
autoexport="1">
|
||||
<parameter name="CLOCK_TYPE" value="1" />
|
||||
<parameter name="DEVICE_FAMILY" value="MAX 10" />
|
||||
<parameter name="ENA_REGISTER_MODE" value="1" />
|
||||
<parameter name="GUI_USE_ENA" value="true" />
|
||||
<parameter name="NUMBER_OF_CLOCKS" value="1" />
|
||||
<parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
|
||||
</module>
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
|
||||
</system>
|
||||
@@ -0,0 +1,16 @@
|
||||
#
|
||||
# Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/quartus_ip_builder.mak
|
||||
|
||||
IP_ON_CHIP_FLASH_SRCS = \
|
||||
$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.qsys
|
||||
|
||||
IP_ON_CHIP_FLASH_OUTS = \
|
||||
$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.sopcinfo
|
||||
|
||||
$(IP_ON_CHIP_FLASH_SRCS) $(IP_ON_CHIP_FLASH_OUTS) : $(IP_DIR)/on_chip_flash/on_chip_flash.qsys
|
||||
$(call BUILD_QUARTUS_IP,on_chip_flash,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR))
|
||||
@@ -0,0 +1,16 @@
|
||||
#
|
||||
# Copyright 2021 Ettus Research, a National Instruments Brand
|
||||
#
|
||||
# SPDX-License-Identifier: LGPL-3.0-or-later
|
||||
#
|
||||
|
||||
include $(TOOLS_DIR)/make/quartus_ip_builder.mak
|
||||
|
||||
IP_OSC_SRCS = \
|
||||
$(IP_BUILD_DIR)/osc/osc.qsys
|
||||
|
||||
IP_OSC_OUTS = \
|
||||
$(IP_BUILD_DIR)/osc/osc.sopcinfo
|
||||
|
||||
$(IP_OSC_SRCS) $(IP_OSC_OUTS) : $(IP_DIR)/osc/osc.qsys
|
||||
$(call BUILD_QUARTUS_IP,osc,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR))
|
||||
+41
-41
@@ -824,49 +824,49 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CH1_TX_LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 2MA -to CH1_TX_LED
|
||||
|
||||
# The zbx_top_cpld.v has to stand first as it contains a define statement.
|
||||
set_global_assignment -name VERILOG_FILE ./zbx_top_cpld.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_decoder.v
|
||||
set_global_assignment -name SDC_FILE ../../../constraints/timing/shared_constants.sdc
|
||||
set_global_assignment -name SDC_FILE ../../../cpld/db_spi_shared_constants.sdc
|
||||
set_global_assignment -name SDC_FILE zbx_top_cpld.sdc
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/synchronizer_impl.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/synchronizer.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/control/reset_sync.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/rfnoc/utils/ctrlport_splitter.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../cpld/spi_slave.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../cpld/spi_slave_to_ctrlport_master.v
|
||||
set_global_assignment -name VERILOG_FILE ./register_endpoints/basic_regs.v
|
||||
set_global_assignment -name VERILOG_FILE ./register_endpoints/power_regs.v
|
||||
set_global_assignment -name VERILOG_FILE ./register_endpoints/switch_control.v
|
||||
set_global_assignment -name VERILOG_FILE ./register_endpoints/dsa_control.v
|
||||
set_global_assignment -name VERILOG_FILE ./register_endpoints/led_control.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_top.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v
|
||||
set_global_assignment -name VERILOG_FILE ./../../../../../lib/wb_spi/rtl/verilog/spi_shift.v
|
||||
set_global_assignment -name VERILOG_FILE ./register_endpoints/lo_control.v
|
||||
set_global_assignment -name VERILOG_FILE ./zbx_cpld_core.v
|
||||
set_global_assignment -name VERILOG_FILE ../../ctrlport_byte_deserializer.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../cpld/reconfig_engine.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../lib/rfnoc/utils/ctrlport_combiner.v
|
||||
set_global_assignment -name VERILOG_FILE register_endpoints/atr_controller.v
|
||||
set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../lib/control/ram_2port_impl.vh
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../lib/control/ram_2port.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../lib/control/handshake.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../lib/control/pulse_synchronizer.v
|
||||
set_global_assignment -name VERILOG_FILE ./ctrlport_window.v
|
||||
set_global_assignment -name VERILOG_FILE ../zbx_top_cpld.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_decoder.v
|
||||
set_global_assignment -name SDC_FILE ../../../../constraints/timing/shared_constants.sdc
|
||||
set_global_assignment -name SDC_FILE ../../../../cpld/db_spi_shared_constants.sdc
|
||||
set_global_assignment -name SDC_FILE ../zbx_top_cpld.sdc
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer_impl.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/synchronizer.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/reset_sync.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_splitter.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../cpld/spi_slave.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../cpld/spi_slave_to_ctrlport_master.v
|
||||
set_global_assignment -name VERILOG_FILE ../register_endpoints/basic_regs.v
|
||||
set_global_assignment -name VERILOG_FILE ../register_endpoints/power_regs.v
|
||||
set_global_assignment -name VERILOG_FILE ../register_endpoints/switch_control.v
|
||||
set_global_assignment -name VERILOG_FILE ../register_endpoints/dsa_control.v
|
||||
set_global_assignment -name VERILOG_FILE ../register_endpoints/led_control.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/wb_spi/rtl/verilog/spi_top.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/wb_spi/rtl/verilog/spi_shift.v
|
||||
set_global_assignment -name VERILOG_FILE ../register_endpoints/lo_control.v
|
||||
set_global_assignment -name VERILOG_FILE ../zbx_cpld_core.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../ctrlport_byte_deserializer.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../cpld/reconfig_engine.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_combiner.v
|
||||
set_global_assignment -name VERILOG_FILE ../register_endpoints/atr_controller.v
|
||||
set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../../lib/control/ram_2port_impl.vh
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/ram_2port.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/handshake.v
|
||||
set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/pulse_synchronizer.v
|
||||
set_global_assignment -name VERILOG_FILE ../ctrlport_window.v
|
||||
|
||||
set_global_assignment -name QSYS_FILE ip/flash/on_chip_flash.qsys
|
||||
set_global_assignment -name QSYS_FILE ip/osc/osc.qsys
|
||||
set_global_assignment -name QSYS_FILE ../../../cpld/ip/clkctrl/clkctrl.qsys
|
||||
set_global_assignment -name SOURCE_FILE db/zbx_top_cpld.cmp.rdb
|
||||
set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys
|
||||
set_global_assignment -name QSYS_FILE ../ip/osc/osc.qsys
|
||||
set_global_assignment -name QSYS_FILE ../../../../cpld/ip/clkctrl/clkctrl.qsys
|
||||
set_global_assignment -name SOURCE_FILE ../db/zbx_top_cpld.cmp.rdb
|
||||
|
||||
set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx1_path_defaults.hex
|
||||
set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx0_path_defaults.hex
|
||||
set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/tx_dsa_defaults.hex
|
||||
set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx1_path_defaults.hex
|
||||
set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx0_path_defaults.hex
|
||||
set_global_assignment -name HEX_FILE register_endpoints/memory_init_files/rx_dsa_defaults.hex
|
||||
set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/tx1_path_defaults.hex
|
||||
set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/tx0_path_defaults.hex
|
||||
set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/tx_dsa_defaults.hex
|
||||
set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/rx1_path_defaults.hex
|
||||
set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/rx0_path_defaults.hex
|
||||
set_global_assignment -name HEX_FILE ./register_endpoints/memory_init_files/rx_dsa_defaults.hex
|
||||
|
||||
set_global_assignment -name ENABLE_OCT_DONE OFF
|
||||
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
|
||||
@@ -150,7 +150,7 @@ endmodule
|
||||
// This enum is used to create the constants held in the basic registers in both verilog and vhdl.
|
||||
// </info>
|
||||
// <value name="BOARD_ID_VALUE" integer="0x4002"/>
|
||||
// <value name="CPLD_REVISION" integer="0x21031009"/>
|
||||
// <value name="CPLD_REVISION" integer="0x21111614"/>
|
||||
// <value name="OLDEST_CPLD_REVISION" integer="0x20110611"/>
|
||||
// </enumeratedtype>
|
||||
//
|
||||
|
||||
@@ -29,7 +29,7 @@
|
||||
localparam BASIC_REGISTERS_VALUES_SIZE = 3;
|
||||
localparam BOARD_ID_VALUE = 'h4002; // BASIC_REGISTERS_VALUES:BOARD_ID_VALUE
|
||||
localparam OLDEST_CPLD_REVISION = 'h20110611; // BASIC_REGISTERS_VALUES:OLDEST_CPLD_REVISION
|
||||
localparam CPLD_REVISION = 'h21031009; // BASIC_REGISTERS_VALUES:CPLD_REVISION
|
||||
localparam CPLD_REVISION = 'h21111614; // BASIC_REGISTERS_VALUES:CPLD_REVISION
|
||||
|
||||
// SLAVE_SIGNATURE Register (from basic_regs.v)
|
||||
localparam SLAVE_SIGNATURE = 'h0; // Register Offset
|
||||
|
||||
Reference in New Issue
Block a user