Humberto Jimenez
4082066a6f
This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes. Original-commit: e1ce4565dbc7336ee806adce7c087bda4fcc77ae
31 lines
1.3 KiB
Plaintext
31 lines
1.3 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition
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# Date created = 17:19:38 August 16, 2019
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "17.1"
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DATE = "17:19:38 August 16, 2019"
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# Revisions
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PROJECT_REVISION = "zbx_top_cpld"
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