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fpga: x400: refactor RFDC block diagrams and timing constraints

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Original-commit: a7bce74be154de9a68d6bdf2f9a6651b480b6dfa
This commit is contained in:
Friedrich Wenisch
2025-02-13 07:51:05 -06:00
committed by Wade Fife
parent f480008cf9
commit 3ed06cc861
12 changed files with 215 additions and 393 deletions
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top/x400/Makefile.x4xx.inc
+2 -2
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@@ -110,9 +110,9 @@ ifneq (,$(findstring RF_BW=400,$(RFNOC_IMAGE_CORE_DEFS)))
MB_XDC += \ MB_XDC += \
constraints/timing/x440_clocks_400.xdc constraints/timing/x440_clocks_400.xdc
endif endif
ifneq (,$(findstring RF_BW=1600,$(RFNOC_IMAGE_CORE_DEFS))) ifneq (,$(findstring RF_BW=200,$(RFNOC_IMAGE_CORE_DEFS)))
MB_XDC += \ MB_XDC += \
constraints/timing/x440_clocks_1600.xdc constraints/timing/x440_clocks_200.xdc
endif endif
MB_XDC += \ MB_XDC += \
constraints/timing/x440_clocks.xdc constraints/timing/x440_clocks.xdc
top/x400/constraints/timing/x410.xdc
+21 -21
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@@ -56,31 +56,28 @@ set_input_delay -clock pll_ref_clk \
# x410_ps_rfdc_bd # x410_ps_rfdc_bd
############################################################################### ###############################################################################
# This property tells Vivado that we require these clocks to be well aligned. # This property tells Vivado that we require the clocks generated by the RFDC MMCM to be well
# We have synchronous clock domain crossings between these clocks that can have # aligned. We have synchronous clock domain crossings between these clocks that can have
# large hold violations after placement due to uneven clock loading. # large hold violations after placement due to uneven clock loading.
set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\ # The constraint CLOCK_DELAY_GROUP has to be applied on the clock nets.
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\ # These nets are connected to the outputs of the clock buffers, which are driven by the MMCM.
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\ # Search the nets begining from the MMCM outputs to find the clock buffers outputs.
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\ set rfdc_mmcm [get_cells -hierarchical -filter { PRIMITIVE_TYPE == CLOCK.PLL.MMCME4_ADV && NAME =~ *rfdc/data_clock_mmcm* } ]
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk_2x ||\ set mmcm_clkout_pins [get_pins -of_objects $rfdc_mmcm -regexp -filter {NAME =~ ".*CLKOUT[0-4]"}]
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/rfdc_clk \ set mmcm_clkout_nets [get_nets -of_objects $mmcm_clkout_pins]
}] set clkbuf_in_pins [get_pins -leaf -of_objects $mmcm_clkout_nets -filter {DIRECTION == IN}]
set clkbuf_cells [get_cells -of_objects $clkbuf_in_pins]
set clkbuf_out_pins [get_pins -of_objects $clkbuf_cells -filter {DIRECTION == OUT}]
set clkbuf_out_nets [get_nets -of_objects $clkbuf_out_pins]
set_property CLOCK_DELAY_GROUP DataClkGroup $clkbuf_out_nets
# We treat rfdc_clk and data_clk buffers as asynchronous, with knowledge that
# We treat rfdc_clk buffers as asynchronous, with knowledge that
# code clocked in this domain will be reset after this clocked is enabled. This # code clocked in this domain will be reset after this clocked is enabled. This
# will make timing easier to meet on these clock domains. # will make timing easier to meet on these clock domains.
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg1x*/C}] \ # set_false_path -from [get_cells -hierarchical -regexp -filter {NAME =~ .*/rfdc/clock_gates_0/.*rEnableRfdc\dBufg.*_reg}]
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_1x_buf/*BUFGCE*/CE}] set_false_path -from [get_cells -hierarchical -regexp -filter {NAME =~ .*/rfdc/clock_gates_0/.*rEnableDataBufg\dx.*_reg}]
set_false_path -from [get_cells -hierarchical -regexp -filter {NAME =~ .*/rfdc/clock_gates_0/.*rEnableRfdcBufg\dx.*_reg}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdcBufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rfdc_clk_2x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg1x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk1xSafeBufg/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableDataBufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*DataClk2xSafeBufg/CE}]
############################################################################### ###############################################################################
@@ -138,3 +135,6 @@ set spi_max_out_delay 11.000
set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}] set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports set_output_delay -clock [get_clocks pll_ref_clk] -min $spi_min_out_delay $spi_out_ports
set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports set_output_delay -clock [get_clocks pll_ref_clk] -max $spi_max_out_delay $spi_out_ports
# Force SPI registers into IOB.
set_property IOB TRUE [get_cells "cpld_interface_i/ctrlport_spi_master_i/simple_spi_core_64bit_i/sclk_reg"]
set_property IOB TRUE [get_cells "cpld_interface_i/ctrlport_spi_master_i/simple_spi_core_64bit_i/mosi_reg"]
top/x400/constraints/timing/x440.xdc
+17 -24
View File
@@ -40,33 +40,26 @@ set_multicycle_path -end -hold 7 -from [get_pins db_gpio_gen[*].db_gpio_interfac
# x440_ps_rfdc_bd # x440_ps_rfdc_bd
############################################################################### ###############################################################################
# This property tells Vivado that we require these clocks to be well aligned. # This property tells Vivado that we require the clocks generated by the RFDC MMCM to be well
# We have synchronous clock domain crossings between these clocks that can have # aligned. We have synchronous clock domain crossings between these clocks that can have
# large hold violations after placement due to uneven clock loading. # large hold violations after placement due to uneven clock loading.
set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\ # The constraint CLOCK_DELAY_GROUP has to be applied on the clock nets.
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\ # These nets are connected to the outputs of the clock buffers, which are driven by the MMCM.
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\ # Search the nets begining from the MMCM outputs to find the clock buffers outputs.
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\ set rfdc_mmcm [get_cells -hierarchical -filter { PRIMITIVE_TYPE == CLOCK.PLL.MMCME4_ADV && NAME =~ *rfdc/data_clock_mmcm* } ]
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio0_rfdc_clk ||\ set mmcm_clkout_pins [get_pins -of_objects $rfdc_mmcm -regexp -filter {NAME =~ ".*CLKOUT[0-6]"}]
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio0_rfdc_clk_2x ||\ set mmcm_clkout_nets [get_nets -of_objects $mmcm_clkout_pins]
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio1_rfdc_clk ||\ set clkbuf_in_pins [get_pins -leaf -of_objects $mmcm_clkout_nets -filter {DIRECTION == IN}]
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio1_rfdc_clk_2x \ set clkbuf_cells [get_cells -of_objects $clkbuf_in_pins]
}] set clkbuf_out_pins [get_pins -of_objects $clkbuf_cells -filter {DIRECTION == OUT}]
set clkbuf_out_nets [get_nets -of_objects $clkbuf_out_pins]
set_property CLOCK_DELAY_GROUP DataClkGroup $clkbuf_out_nets
# We treat rfdc_clk buffers as asynchronous, with knowledge that # We treat rfdc_clk buffers as asynchronous, with knowledge that
# code clocked in this domain will be reset after this clocked is enabled. This # code clocked in this domain will be reset after this clocked is enabled. This
# will make timing easier to meet on these clock domains. # will make timing easier to meet on these clock domains.
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc0Bufg1x*/C}] \ set_false_path -from [get_cells -hierarchical -regexp -filter {NAME =~ .*/rfdc/clock_gates_0/.*rEnableRfdc\dBufg.*_reg}]
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf0_clk_1x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc0Bufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf0_clk_2x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc1Bufg1x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf1_clk_1x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc1Bufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf1_clk_2x_buf/*BUFGCE*/CE}]
############################################################################### ###############################################################################
@@ -117,8 +110,8 @@ set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSR
# The output delays are chosen to allow a large time window of valid data for # The output delays are chosen to allow a large time window of valid data for
# the MB CPLD logic. # the MB CPLD logic.
set spi_min_out_delay -1.500 set spi_min_out_delay 0.000
set spi_max_out_delay 9.500 set spi_max_out_delay 11.000
# Set output constraints for all ports. # Set output constraints for all ports.
set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}] set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]
top/x400/constraints/timing/x440_clocks.xdc
+4 -18
View File
@@ -12,26 +12,12 @@
# #
# Note: Vivado will create generated clocks based on the default MMCM settings # Note: Vivado will create generated clocks based on the default MMCM settings
# configured in the clocking wizard, but we are going to dynamically change # configured in the clocking wizard, but we are going to dynamically change
# those clocks, and so we need to provide worst-case values in here. # those clocks, and so the MMCM has to be configured for the highest frequency.
############################################################################### ###############################################################################
# PLL Reference Clock (PRC) input. This goes from the LMK straight to the MMCM # PLL Reference Clock (PRC) input. This goes from the LMK straight to the MMCM
# input, and is used to generate the internal PRC as well as RFDC/data clocks. # input, and is used to generate the internal PRC as well as RFDC/data clocks.
set pll_ref_clk_in_period 15.625 # Set to maximum frequency of 64 MHz. Actual frequency depends on the LMK
create_clock -name pll_ref_in_clk -period $pll_ref_clk_in_period [get_ports PLL_REFCLK_FPGA_P] # configuration.
# Internal PLL Reference Clock (PRC). Used to derive data clocks. Constrain to
# the fastest possible clock rate supported in the driver.
set pll_ref_clk_period 15.625 set pll_ref_clk_period 15.625
create_clock -name pll_ref_clk \ create_clock -name pll_ref_clk -period $pll_ref_clk_period [get_ports PLL_REFCLK_FPGA_P]
-period $pll_ref_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT0]
###############################################################################
# Generated Clocks
###############################################################################
create_generated_clock -name sync_ref_clk \
-source [get_ports BASE_REFCLK_FPGA_P] \
-divide_by 2 [get_pins clock_div_5mhz/clk_out_reg/Q]
top/x400/constraints/timing/x440_clocks_1600.xdc
-20
View File
@@ -1,20 +0,0 @@
#
# Copyright 2023 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Clock definition constraints for X440 1600 type images
#
# Data clocks: Generated by the MMCM, used for data paths between the RFDC output
# and RFNoC. Maximum supported master clock rate is 2.048 Gsps @8SPC => 256 MHz.
set rfdc_data_clk_period 3.906
create_clock -name rfdc_r0_clk -add \
-period $rfdc_data_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2]
create_clock -name rfdc_r1_clk -add \
-period $rfdc_data_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5]
top/x400/constraints/timing/x440_clocks_200.xdc
+25
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@@ -0,0 +1,25 @@
#
# Copyright 2024 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
# Clock definition constraints for X440 200 MHz BW type images
#
# Data clocks: Generated by the MMCM, used for data paths between the RFDC output and RFNoC.
# The RFDC block diagram is set up for the maximum required clock frequencies (rfdc_clk_1x @ 256 MHz),
# which are used in the 1600 MHz bitfile.
# This is not required for the 200 MHz bitfile, hence we multiply the output clock divider values by 8
# to allow Vivado to auto-derive the correct clock periods.
set data_clock_mmcm [get_cells -hierarchical -filter { PRIMITIVE_TYPE == CLOCK.PLL.MMCME4_ADV && NAME =~ "*data_clock_mmcm*" }]
set_property -dict [ list \
CLKOUT1_DIVIDE {32} \
CLKOUT2_DIVIDE {32} \
CLKOUT3_DIVIDE {16} \
CLKOUT4_DIVIDE {16} \
CLKOUT5_DIVIDE {32} \
CLKOUT6_DIVIDE {16} \
] $data_clock_mmcm
top/x400/constraints/timing/x440_clocks_400.xdc
+16 -12
View File
@@ -1,21 +1,25 @@
# #
# Copyright 2023 Ettus Research, a National Instruments Brand # Copyright 2024 Ettus Research, a National Instruments Brand
# #
# SPDX-License-Identifier: LGPL-3.0-or-later # SPDX-License-Identifier: LGPL-3.0-or-later
# #
# Description: # Description:
# Clock definition constraints for X440 400 type images # Clock definition constraints for X440 400 MHz BW type images
# #
# Data clocks: Generated by the MMCM, used for data paths between the RFDC output # Data clocks: Generated by the MMCM, used for data paths between the RFDC output and RFNoC.
# and RFNoC. Maximum supported master clock rate is 500 Msps @8SPC => 62.5 MHz. # The RFDC block diagram is set up for the maximum required clock frequencies (rfdc_clk_1x @ 256 MHz),
# Theoretical maximum converter rate is 4.096 GSps, so really, 512 Msps @ 8SPC => 64 MHz. # which are used in the 1600 MHz bitfile.
set rfdc_data_clk_period 15.625 # This is not required for the 400 MHz bitfile, hence we multiply the output clock divider values by 4
# to allow Vivado to auto-derive the correct clock periods.
create_clock -name rfdc_r0_clk -add \ set data_clock_mmcm [get_cells -hierarchical -filter { PRIMITIVE_TYPE == CLOCK.PLL.MMCME4_ADV && NAME =~ "*data_clock_mmcm*" }]
-period $rfdc_data_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2]
create_clock -name rfdc_r1_clk -add \
-period $rfdc_data_clk_period \
[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5]
set_property -dict [ list \
CLKOUT1_DIVIDE {16} \
CLKOUT2_DIVIDE {16} \
CLKOUT3_DIVIDE {8} \
CLKOUT4_DIVIDE {8} \
CLKOUT5_DIVIDE {16} \
CLKOUT6_DIVIDE {8} \
] $data_clock_mmcm
top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/hdl_sources.tcl
+11 -11
View File
@@ -1,14 +1,14 @@
set script_loc [file normalize [info script]] set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc] set script_dir [file dirname $script_loc]
read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v read_vhdl -library work $script_dir/../../../regmap/x410/PkgRFDC_REGS_REGMAP.vhd
read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
read_vhdl -library work $script_dir/../../../regmap/x410/PkgRFDC_REGS_REGMAP.vhd read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
read_vhdl -library work $script_dir/../../../rf/x410/x410_rf_reset_controller.vhd read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
read_vhdl -library work $script_dir/../../../rf/x410/x410_clock_gates.vhd read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd read_vhdl -library work $script_dir/../../../rf/x410/x410_clock_gates.vhd
read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd read_vhdl -library work $script_dir/../../../rf/x410/x410_rf_reset_controller.vhd
top/x400/ip/x4xx_ps_rfdc_bd/x410_ps_rfdc_bd/x410_ps_rfdc_bd.tcl
+16 -87
View File
@@ -154,7 +154,6 @@ xilinx.com:ip:xlslice:1.0\
xilinx.com:ip:axi_protocol_converter:2.1\ xilinx.com:ip:axi_protocol_converter:2.1\
xilinx.com:ip:axi_dma:7.1\ xilinx.com:ip:axi_dma:7.1\
xilinx.com:ip:smartconnect:1.0\ xilinx.com:ip:smartconnect:1.0\
xilinx.com:ip:util_ds_buf:2.2\
" "
set list_ips_missing "" set list_ips_missing ""
@@ -214,74 +213,6 @@ if { $bCheckIPsPassed != 1 } {
################################################################## ##################################################################
# Hierarchical cell: rf_clock_buffers
proc create_hier_cell_rf_clock_buffers { parentCell nameHier } {
variable script_folder
if { $parentCell eq "" || $nameHier eq "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rf_clock_buffers() - Empty argument(s)!"}
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create interface pins
# Create pins
create_bd_pin -dir O -from 0 -to 0 rfdc_clk
create_bd_pin -dir O -from 0 -to 0 rfdc_clk_2x
create_bd_pin -dir I -from 0 -to 0 rfdc_clk_2x_ce
create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_2x_pll
create_bd_pin -dir I -from 0 -to 0 rfdc_clk_ce
create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_pll
# Create instance: rfdc_clk_1x_buf, and set properties
set rfdc_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_1x_buf ]
set_property -dict [ list \
CONFIG.C_BUF_TYPE {BUFGCE} \
] $rfdc_clk_1x_buf
# Create instance: rfdc_clk_2x_buf, and set properties
set rfdc_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_2x_buf ]
set_property -dict [ list \
CONFIG.C_BUF_TYPE {BUFGCE} \
] $rfdc_clk_2x_buf
# Create port connections
connect_bd_net -net BUFGCE_I2_1 [get_bd_pins rfdc_clk_2x_pll] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_I]
connect_bd_net -net rfdc_clk_1 [get_bd_pins rfdc_clk_pll] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_I]
connect_bd_net -net rfdc_clk_1x_buf_BUFGCE_O [get_bd_pins rfdc_clk] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_O]
connect_bd_net -net rfdc_clk_2x_buf_BUFGCE_O [get_bd_pins rfdc_clk_2x] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_O]
connect_bd_net -net rfdc_clk_2x_ce_1 [get_bd_pins rfdc_clk_2x_ce] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_CE]
connect_bd_net -net rfdc_clk_ce_1 [get_bd_pins rfdc_clk_ce] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_CE]
# Restore current instance
current_bd_instance $oldCurInst
}
# Hierarchical cell: calibration_muxes # Hierarchical cell: calibration_muxes
proc create_hier_cell_calibration_muxes { parentCell nameHier } { proc create_hier_cell_calibration_muxes { parentCell nameHier } {
@@ -797,8 +728,8 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
create_bd_pin -dir I -from 31 -to 0 rf_axi_status_sclk create_bd_pin -dir I -from 31 -to 0 rf_axi_status_sclk
create_bd_pin -dir I -from 31 -to 0 rf_dsp_info_sclk create_bd_pin -dir I -from 31 -to 0 rf_dsp_info_sclk
create_bd_pin -dir I -from 31 -to 0 rf_rfdc_info_sclk create_bd_pin -dir I -from 31 -to 0 rf_rfdc_info_sclk
create_bd_pin -dir O -from 0 -to 0 rfdc_clk create_bd_pin -dir O rfdc_clk
create_bd_pin -dir O -from 0 -to 0 rfdc_clk_2x create_bd_pin -dir O rfdc_clk_2x
create_bd_pin -dir O -type intr rfdc_irq create_bd_pin -dir O -type intr rfdc_irq
create_bd_pin -dir I -type rst s_axi_config_aresetn create_bd_pin -dir I -type rst s_axi_config_aresetn
create_bd_pin -dir I -type clk s_axi_config_clk create_bd_pin -dir I -type clk s_axi_config_clk
@@ -858,31 +789,34 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
# Create instance: const_1, and set properties # Create instance: const_1, and set properties
set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ] set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ]
# Create instance: constant_1, and set properties
set constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_1 ]
# Create instance: data_clock_mmcm, and set properties # Create instance: data_clock_mmcm, and set properties
set data_clock_mmcm [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 data_clock_mmcm ] set data_clock_mmcm [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 data_clock_mmcm ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.AXI_DRP {true} \ CONFIG.AXI_DRP {true} \
CONFIG.CLKIN1_JITTER_PS {162.76} \ CONFIG.CLKIN1_JITTER_PS {162.76} \
CONFIG.CLKOUT1_DRIVES {Buffer} \ CONFIG.CLKOUT1_DRIVES {BUFG} \
CONFIG.CLKOUT1_JITTER {116.960} \ CONFIG.CLKOUT1_JITTER {116.960} \
CONFIG.CLKOUT1_PHASE_ERROR {124.626} \ CONFIG.CLKOUT1_PHASE_ERROR {124.626} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {61.44} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {61.44} \
CONFIG.CLKOUT2_DRIVES {Buffer} \ CONFIG.CLKOUT2_DRIVES {No_buffer} \
CONFIG.CLKOUT2_JITTER {104.559} \ CONFIG.CLKOUT2_JITTER {104.559} \
CONFIG.CLKOUT2_PHASE_ERROR {124.626} \ CONFIG.CLKOUT2_PHASE_ERROR {124.626} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {122.88} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {122.88} \
CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_DRIVES {Buffer} \ CONFIG.CLKOUT3_DRIVES {BUFGCE} \
CONFIG.CLKOUT3_JITTER {98.017} \ CONFIG.CLKOUT3_JITTER {98.017} \
CONFIG.CLKOUT3_PHASE_ERROR {124.626} \ CONFIG.CLKOUT3_PHASE_ERROR {124.626} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {184.32} \ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {184.32} \
CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_DRIVES {Buffer} \ CONFIG.CLKOUT4_DRIVES {No_buffer} \
CONFIG.CLKOUT4_JITTER {93.671} \ CONFIG.CLKOUT4_JITTER {93.671} \
CONFIG.CLKOUT4_PHASE_ERROR {124.626} \ CONFIG.CLKOUT4_PHASE_ERROR {124.626} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {245.76} \ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {245.76} \
CONFIG.CLKOUT4_USED {true} \ CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT5_DRIVES {Buffer} \ CONFIG.CLKOUT5_DRIVES {BUFGCE} \
CONFIG.CLKOUT5_JITTER {87.938} \ CONFIG.CLKOUT5_JITTER {87.938} \
CONFIG.CLKOUT5_PHASE_ERROR {124.626} \ CONFIG.CLKOUT5_PHASE_ERROR {124.626} \
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {368.64} \ CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {368.64} \
@@ -991,9 +925,6 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
CONFIG.C_IS_DUAL {1} \ CONFIG.C_IS_DUAL {1} \
] $reg_rfdc_tile_mapping ] $reg_rfdc_tile_mapping
# Create instance: rf_clock_buffers
create_hier_cell_rf_clock_buffers $hier_obj rf_clock_buffers
# Create instance: rf_data_converter, and set properties # Create instance: rf_data_converter, and set properties
set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ] set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ]
set_property -dict [ list \ set_property -dict [ list \
@@ -1384,18 +1315,16 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
connect_bd_net -net clock_gates_0_cSoftwareStatus [get_bd_pins clock_gates_0/rSoftwareStatus] [get_bd_pins reg_clock_gate_control/gpio2_io_i] connect_bd_net -net clock_gates_0_cSoftwareStatus [get_bd_pins clock_gates_0/rSoftwareStatus] [get_bd_pins reg_clock_gate_control/gpio2_io_i]
connect_bd_net -net clock_gates_0_rGatedBaseClksValid [get_bd_pins gated_base_clks_valid_clk40] [get_bd_pins clock_gates_0/rGatedBaseClksValid] connect_bd_net -net clock_gates_0_rGatedBaseClksValid [get_bd_pins gated_base_clks_valid_clk40] [get_bd_pins clock_gates_0/rGatedBaseClksValid]
connect_bd_net -net clock_gates_0_rPllLocked [get_bd_pins data_clock_locked] [get_bd_pins clock_gates_0/rPllLocked] connect_bd_net -net clock_gates_0_rPllLocked [get_bd_pins data_clock_locked] [get_bd_pins clock_gates_0/rPllLocked]
connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg2x] [get_bd_pins rf_clock_buffers/rfdc_clk_2x_ce] connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg2x] [get_bd_pins data_clock_mmcm/rfdc_clk_2x_ce]
connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg1x] [get_bd_pins rf_clock_buffers/rfdc_clk_ce] connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg1x] [get_bd_pins data_clock_mmcm/rfdc_clk_ce]
connect_bd_net -net dac_reset_pulse_dclk_1 [get_bd_pins dac_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/dDacResetPulse] [get_bd_pins rf_reset_controller_1/dDacResetPulse] connect_bd_net -net dac_reset_pulse_dclk_1 [get_bd_pins dac_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/dDacResetPulse] [get_bd_pins rf_reset_controller_1/dDacResetPulse]
connect_bd_net -net data_clk_2x_pll [get_bd_pins clock_gates_0/DataClk2xPll] [get_bd_pins data_clock_mmcm/data_clk_2x] connect_bd_net -net data_clk_2x_pll [get_bd_pins clock_gates_0/DataClk2xPll] [get_bd_pins data_clock_mmcm/data_clk_2x]
connect_bd_net -net data_clock_mmcm_data_clk [get_bd_pins data_clk] [get_bd_pins clock_gates_0/DataClk1x] [get_bd_pins rf_nco_reset_0/DataClk] [get_bd_pins rf_reset_controller_0/DataClk] [get_bd_pins rf_reset_controller_1/DataClk] connect_bd_net -net data_clock_mmcm_data_clk [get_bd_pins data_clk] [get_bd_pins clock_gates_0/DataClk1x] [get_bd_pins rf_nco_reset_0/DataClk] [get_bd_pins rf_reset_controller_0/DataClk] [get_bd_pins rf_reset_controller_1/DataClk]
connect_bd_net -net data_clock_mmcm_data_clk1 [get_bd_pins clock_gates_0/DataClk1xPll] [get_bd_pins data_clock_mmcm/data_clk] connect_bd_net -net data_clock_mmcm_data_clk1 [get_bd_pins clock_gates_0/DataClk1xPll] [get_bd_pins data_clock_mmcm/data_clk]
connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_pins data_clk_2x] [get_bd_pins clock_gates_0/DataClk2x] [get_bd_pins rf_reset_controller_0/DataClk2x] [get_bd_pins rf_reset_controller_1/DataClk2x] connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_pins data_clk_2x] [get_bd_pins clock_gates_0/DataClk2x] [get_bd_pins rf_reset_controller_0/DataClk2x] [get_bd_pins rf_reset_controller_1/DataClk2x]
connect_bd_net -net data_clock_mmcm_locked [get_bd_pins clock_gates_0/aPllLocked] [get_bd_pins data_clock_mmcm/locked] connect_bd_net -net data_clock_mmcm_locked [get_bd_pins clock_gates_0/aPllLocked] [get_bd_pins data_clock_mmcm/locked]
connect_bd_net -net data_clock_mmcm_rfdc_clk [get_bd_pins rfdc_clk] [get_bd_pins calibration_muxes/s_axi_aclk_0] [get_bd_pins capture_sysref/rfdc_clk] [get_bd_pins rf_clock_buffers/rfdc_clk] [get_bd_pins rf_data_converter/m0_axis_aclk] [get_bd_pins rf_data_converter/m2_axis_aclk] [get_bd_pins rf_data_converter/s0_axis_aclk] [get_bd_pins rf_data_converter/s1_axis_aclk] [get_bd_pins rf_reset_controller_0/RfClk] [get_bd_pins rf_reset_controller_1/RfClk] connect_bd_net -net data_clock_mmcm_rfdc_clk [get_bd_pins rfdc_clk] [get_bd_pins calibration_muxes/s_axi_aclk_0] [get_bd_pins capture_sysref/rfdc_clk] [get_bd_pins data_clock_mmcm/rfdc_clk] [get_bd_pins rf_data_converter/m0_axis_aclk] [get_bd_pins rf_data_converter/m2_axis_aclk] [get_bd_pins rf_data_converter/s0_axis_aclk] [get_bd_pins rf_data_converter/s1_axis_aclk] [get_bd_pins rf_reset_controller_0/RfClk] [get_bd_pins rf_reset_controller_1/RfClk]
connect_bd_net -net data_clock_mmcm_rfdc_clk1 [get_bd_pins data_clock_mmcm/rfdc_clk] [get_bd_pins rf_clock_buffers/rfdc_clk_pll] connect_bd_net -net data_clock_mmcm_rfdc_clk_2x1 [get_bd_pins rfdc_clk_2x] [get_bd_pins axi_interconnect_rf/M02_ACLK] [get_bd_pins axi_interconnect_rf/M11_ACLK] [get_bd_pins data_clock_mmcm/rfdc_clk_2x] [get_bd_pins reg_invert_iq_radio0/s_axi_aclk] [get_bd_pins reg_invert_iq_radio1/s_axi_aclk] [get_bd_pins rf_reset_controller_0/RfClk2x] [get_bd_pins rf_reset_controller_1/RfClk2x]
connect_bd_net -net data_clock_mmcm_rfdc_clk_2x [get_bd_pins rfdc_clk_2x] [get_bd_pins axi_interconnect_rf/M02_ACLK] [get_bd_pins axi_interconnect_rf/M11_ACLK] [get_bd_pins reg_invert_iq_radio0/s_axi_aclk] [get_bd_pins reg_invert_iq_radio1/s_axi_aclk] [get_bd_pins rf_clock_buffers/rfdc_clk_2x] [get_bd_pins rf_reset_controller_0/RfClk2x] [get_bd_pins rf_reset_controller_1/RfClk2x]
connect_bd_net -net data_clock_mmcm_rfdc_clk_2x1 [get_bd_pins data_clock_mmcm/rfdc_clk_2x] [get_bd_pins rf_clock_buffers/rfdc_clk_2x_pll]
connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_pins pll_ref_clk_out] [get_bd_pins capture_sysref/pll_ref_clk] [get_bd_pins data_clock_mmcm/pll_ref_clk_out] [get_bd_pins rf_reset_controller_0/PllRefClk] [get_bd_pins rf_reset_controller_1/PllRefClk] connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_pins pll_ref_clk_out] [get_bd_pins capture_sysref/pll_ref_clk] [get_bd_pins data_clock_mmcm/pll_ref_clk_out] [get_bd_pins rf_reset_controller_0/PllRefClk] [get_bd_pins rf_reset_controller_1/PllRefClk]
connect_bd_net -net enable_gated_clocks_clk40_1 [get_bd_pins enable_gated_clocks_clk40] [get_bd_pins clock_gates_0/rSafeToEnableGatedClks] connect_bd_net -net enable_gated_clocks_clk40_1 [get_bd_pins enable_gated_clocks_clk40] [get_bd_pins clock_gates_0/rSafeToEnableGatedClks]
connect_bd_net -net enable_rclk_0_1 [get_bd_pins enable_sysref_rclk] [get_bd_pins capture_sysref/enable_rclk] connect_bd_net -net enable_rclk_0_1 [get_bd_pins enable_sysref_rclk] [get_bd_pins capture_sysref/enable_rclk]
@@ -3628,13 +3557,13 @@ proc create_root_design { parentCell } {
set rf_axi_status_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_axi_status_clk40 ] set rf_axi_status_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_axi_status_clk40 ]
set rf_dsp_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_dsp_info_clk40 ] set rf_dsp_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_dsp_info_clk40 ]
set rf_rfdc_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_rfdc_info_clk40 ] set rf_rfdc_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_rfdc_info_clk40 ]
set rfdc_clk [ create_bd_port -dir O -from 0 -to 0 -type clk rfdc_clk ] set rfdc_clk [ create_bd_port -dir O -type clk rfdc_clk ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {adc_tile224_ch0_dout_i:adc_tile224_ch1_dout_i:adc_tile224_ch1_dout_q:adc_tile224_ch0_dout_q:dac_tile228_ch0_din:dac_tile228_ch1_din:dac_tile229_ch0_din:dac_tile229_ch1_din:adc_tile226_ch0_dout_i:adc_tile226_ch0_dout_q:adc_tile226_ch1_dout_i:adc_tile226_ch1_dout_q} \ CONFIG.ASSOCIATED_BUSIF {adc_tile224_ch0_dout_i:adc_tile224_ch1_dout_i:adc_tile224_ch1_dout_q:adc_tile224_ch0_dout_q:dac_tile228_ch0_din:dac_tile228_ch1_din:dac_tile229_ch0_din:dac_tile229_ch1_din:adc_tile226_ch0_dout_i:adc_tile226_ch0_dout_q:adc_tile226_ch1_dout_i:adc_tile226_ch1_dout_q} \
CONFIG.ASSOCIATED_RESET {adc_tile224_axis_resetn_rclk:adc_tile226_axis_resetn_rclk:dac_tile228_axis_resetn_rclk:dac_tile229_axis_resetn_rclk} \ CONFIG.ASSOCIATED_RESET {adc_tile224_axis_resetn_rclk:adc_tile226_axis_resetn_rclk:dac_tile228_axis_resetn_rclk:dac_tile229_axis_resetn_rclk} \
CONFIG.FREQ_HZ {184320000} \ CONFIG.FREQ_HZ {184320000} \
] $rfdc_clk ] $rfdc_clk
set rfdc_clk_2x [ create_bd_port -dir O -from 0 -to 0 -type clk rfdc_clk_2x ] set rfdc_clk_2x [ create_bd_port -dir O -type clk rfdc_clk_2x ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {368640000} \ CONFIG.FREQ_HZ {368640000} \
] $rfdc_clk_2x ] $rfdc_clk_2x
top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/hdl_sources.tcl
+13 -13
View File
@@ -1,16 +1,16 @@
set script_loc [file normalize [info script]] set script_loc [file normalize [info script]]
set script_dir [file dirname $script_loc] set script_dir [file dirname $script_loc]
read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v read_vhdl -library work $script_dir/../../../regmap/x440/PkgRFDC_REGS_REGMAP.vhd
read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v read_verilog -library work $script_dir/../../../regmap/x440/rfdc_mapping_regmap_utils.vh
read_verilog -library work $script_dir/../../../regmap/x440/rfdc_mapping_regmap_utils.vh read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
read_verilog -library work $script_dir/../../../rf/x440/x440_rfdc_tx_control_remap.v read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
read_vhdl -library work $script_dir/../../../regmap/x440/PkgRFDC_REGS_REGMAP.vhd read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
read_vhdl -library work $script_dir/../../../rf/x440/x440_rf_reset_controller.vhd read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
read_vhdl -library work $script_dir/../../../rf/x440/x440_clock_gates.vhd read_vhdl -library work $script_dir/../../../rf/x440/x440_clock_gates.vhd
read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd read_vhdl -library work $script_dir/../../../rf/x440/x440_rf_reset_controller.vhd
read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd read_verilog -library work $script_dir/../../../rf/x440/x440_rfdc_tx_control_remap.v
top/x400/ip/x4xx_ps_rfdc_bd/x440_ps_rfdc_bd/x440_ps_rfdc_bd.tcl
+80 -180
View File
@@ -154,7 +154,6 @@ xilinx.com:ip:xlslice:1.0\
xilinx.com:ip:axi_protocol_converter:2.1\ xilinx.com:ip:axi_protocol_converter:2.1\
xilinx.com:ip:axi_dma:7.1\ xilinx.com:ip:axi_dma:7.1\
xilinx.com:ip:smartconnect:1.0\ xilinx.com:ip:smartconnect:1.0\
xilinx.com:ip:util_ds_buf:2.2\
" "
set list_ips_missing "" set list_ips_missing ""
@@ -215,98 +214,6 @@ if { $bCheckIPsPassed != 1 } {
################################################################## ##################################################################
# Hierarchical cell: rf_clock_buffers
proc create_hier_cell_rf_clock_buffers { parentCell nameHier } {
variable script_folder
if { $parentCell eq "" || $nameHier eq "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rf_clock_buffers() - Empty argument(s)!"}
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create interface pins
# Create pins
create_bd_pin -dir I -from 0 -to 0 radio0_rfdc_clk_2x_ce
create_bd_pin -dir I -from 0 -to 0 -type clk radio0_rfdc_clk_2x_pll
create_bd_pin -dir I -from 0 -to 0 radio0_rfdc_clk_ce
create_bd_pin -dir I -from 0 -to 0 -type clk radio0_rfdc_clk_pll
create_bd_pin -dir I -from 0 -to 0 radio1_rfdc_clk_2x_ce
create_bd_pin -dir I -from 0 -to 0 -type clk radio1_rfdc_clk_2x_pll
create_bd_pin -dir I -from 0 -to 0 radio1_rfdc_clk_ce
create_bd_pin -dir I -from 0 -to 0 -type clk radio1_rfdc_clk_pll
create_bd_pin -dir O -from 0 -to 0 rf0_clk_1x
create_bd_pin -dir O -from 0 -to 0 rf0_clk_2x
create_bd_pin -dir O -from 0 -to 0 rf1_clk_1x
create_bd_pin -dir O -from 0 -to 0 rf1_clk_2x
# Create instance: rf0_clk_1x_buf, and set properties
set rf0_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rf0_clk_1x_buf ]
set_property -dict [ list \
CONFIG.C_BUF_TYPE {BUFGCE} \
] $rf0_clk_1x_buf
# Create instance: rf0_clk_2x_buf, and set properties
set rf0_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rf0_clk_2x_buf ]
set_property -dict [ list \
CONFIG.C_BUF_TYPE {BUFGCE} \
] $rf0_clk_2x_buf
# Create instance: rf1_clk_1x_buf, and set properties
set rf1_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rf1_clk_1x_buf ]
set_property -dict [ list \
CONFIG.C_BUF_TYPE {BUFGCE} \
] $rf1_clk_1x_buf
# Create instance: rf1_clk_2x_buf, and set properties
set rf1_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rf1_clk_2x_buf ]
set_property -dict [ list \
CONFIG.C_BUF_TYPE {BUFGCE} \
] $rf1_clk_2x_buf
# Create port connections
connect_bd_net -net BUFGCE_I2_1 [get_bd_pins radio0_rfdc_clk_2x_pll] [get_bd_pins rf0_clk_2x_buf/BUFGCE_I]
connect_bd_net -net radio0_rfdc_clk_2x_ce1_1 [get_bd_pins radio1_rfdc_clk_2x_ce] [get_bd_pins rf1_clk_2x_buf/BUFGCE_CE]
connect_bd_net -net radio0_rfdc_clk_pll1_1 [get_bd_pins radio1_rfdc_clk_pll] [get_bd_pins rf1_clk_1x_buf/BUFGCE_I]
connect_bd_net -net radio0_rfdc_clk_pll2_1 [get_bd_pins radio1_rfdc_clk_2x_pll] [get_bd_pins rf1_clk_2x_buf/BUFGCE_I]
connect_bd_net -net radio1_rfdc_clk_ce [get_bd_pins radio1_rfdc_clk_ce] [get_bd_pins rf1_clk_1x_buf/BUFGCE_CE]
connect_bd_net -net rf1_clk_1x_buf_BUFGCE_O [get_bd_pins rf1_clk_1x] [get_bd_pins rf1_clk_1x_buf/BUFGCE_O]
connect_bd_net -net rf1_clk_2x_buf_BUFGCE_O [get_bd_pins rf1_clk_2x] [get_bd_pins rf1_clk_2x_buf/BUFGCE_O]
connect_bd_net -net rfdc_clk_1 [get_bd_pins radio0_rfdc_clk_pll] [get_bd_pins rf0_clk_1x_buf/BUFGCE_I]
connect_bd_net -net rfdc_clk_1x_buf_BUFGCE_O [get_bd_pins rf0_clk_1x] [get_bd_pins rf0_clk_1x_buf/BUFGCE_O]
connect_bd_net -net rfdc_clk_2x_buf_BUFGCE_O [get_bd_pins rf0_clk_2x] [get_bd_pins rf0_clk_2x_buf/BUFGCE_O]
connect_bd_net -net rfdc_clk_2x_ce_1 [get_bd_pins radio0_rfdc_clk_2x_ce] [get_bd_pins rf0_clk_2x_buf/BUFGCE_CE]
connect_bd_net -net rfdc_clk_ce_1 [get_bd_pins radio0_rfdc_clk_ce] [get_bd_pins rf0_clk_1x_buf/BUFGCE_CE]
# Restore current instance
current_bd_instance $oldCurInst
}
# Hierarchical cell: calibration_muxes # Hierarchical cell: calibration_muxes
proc create_hier_cell_calibration_muxes { parentCell nameHier } { proc create_hier_cell_calibration_muxes { parentCell nameHier } {
@@ -896,12 +803,12 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
create_bd_pin -dir O -type clk pll_ref_clk_out create_bd_pin -dir O -type clk pll_ref_clk_out
create_bd_pin -dir O -from 3 -to 0 radio0_invert_adc_iq_r0clk create_bd_pin -dir O -from 3 -to 0 radio0_invert_adc_iq_r0clk
create_bd_pin -dir O -from 3 -to 0 radio0_invert_dac_iq_r0clk create_bd_pin -dir O -from 3 -to 0 radio0_invert_dac_iq_r0clk
create_bd_pin -dir O -from 0 -to 0 radio0_rfdc_clk create_bd_pin -dir O radio0_rfdc_clk
create_bd_pin -dir O -from 0 -to 0 radio0_rfdc_clk_2x create_bd_pin -dir O radio0_rfdc_clk_2x
create_bd_pin -dir O -from 3 -to 0 radio1_invert_adc_iq_r1clk create_bd_pin -dir O -from 3 -to 0 radio1_invert_adc_iq_r1clk
create_bd_pin -dir O -from 3 -to 0 radio1_invert_dac_iq_r1clk create_bd_pin -dir O -from 3 -to 0 radio1_invert_dac_iq_r1clk
create_bd_pin -dir O -from 0 -to 0 radio1_rfdc_clk_1x create_bd_pin -dir O radio1_rfdc_clk_1x
create_bd_pin -dir O -from 0 -to 0 radio1_rfdc_clk_2x create_bd_pin -dir O radio1_rfdc_clk_2x
create_bd_pin -dir I -from 31 -to 0 rf_axi_status_sclk create_bd_pin -dir I -from 31 -to 0 rf_axi_status_sclk
create_bd_pin -dir I -from 31 -to 0 rf_dsp_info_sclk create_bd_pin -dir I -from 31 -to 0 rf_dsp_info_sclk
create_bd_pin -dir I -from 31 -to 0 rf_rfdc_info_sclk create_bd_pin -dir I -from 31 -to 0 rf_rfdc_info_sclk
@@ -945,7 +852,7 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
] [get_bd_pins /rfdc/capture_sysref/pll_ref_clk] ] [get_bd_pins /rfdc/capture_sysref/pll_ref_clk]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
CONFIG.PHASE {0} \ CONFIG.PHASE {0} \
CONFIG.CLK_DOMAIN {x440_ps_rfdc_bd_pll_ref_clk_in} \ CONFIG.CLK_DOMAIN {x440_ps_rfdc_bd_pll_ref_clk_in} \
] [get_bd_pins /rfdc/capture_sysref/rfdc_clk] ] [get_bd_pins /rfdc/capture_sysref/rfdc_clk]
@@ -969,39 +876,39 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
set_property -dict [ list \ set_property -dict [ list \
CONFIG.AXI_DRP {true} \ CONFIG.AXI_DRP {true} \
CONFIG.CLKIN1_JITTER_PS {156.25} \ CONFIG.CLKIN1_JITTER_PS {156.25} \
CONFIG.CLKOUT1_DRIVES {Buffer} \ CONFIG.CLKOUT1_DRIVES {BUFG} \
CONFIG.CLKOUT1_JITTER {130.541} \ CONFIG.CLKOUT1_JITTER {157.622} \
CONFIG.CLKOUT1_PHASE_ERROR {128.385} \ CONFIG.CLKOUT1_PHASE_ERROR {114.796} \
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {64.00} \ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {64.00} \
CONFIG.CLKOUT2_DRIVES {Buffer} \ CONFIG.CLKOUT2_DRIVES {BUFG} \
CONFIG.CLKOUT2_JITTER {116.118} \ CONFIG.CLKOUT2_JITTER {120.323} \
CONFIG.CLKOUT2_PHASE_ERROR {128.385} \ CONFIG.CLKOUT2_PHASE_ERROR {114.796} \
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {128.00} \ CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {256.00} \
CONFIG.CLKOUT2_USED {true} \ CONFIG.CLKOUT2_USED {true} \
CONFIG.CLKOUT3_DRIVES {Buffer} \ CONFIG.CLKOUT3_DRIVES {BUFGCE} \
CONFIG.CLKOUT3_JITTER {130.541} \ CONFIG.CLKOUT3_JITTER {120.323} \
CONFIG.CLKOUT3_PHASE_ERROR {128.385} \ CONFIG.CLKOUT3_PHASE_ERROR {114.796} \
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {64.00} \ CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {256.00} \
CONFIG.CLKOUT3_USED {true} \ CONFIG.CLKOUT3_USED {true} \
CONFIG.CLKOUT4_DRIVES {Buffer} \ CONFIG.CLKOUT4_DRIVES {BUFG} \
CONFIG.CLKOUT4_JITTER {103.479} \ CONFIG.CLKOUT4_JITTER {106.992} \
CONFIG.CLKOUT4_PHASE_ERROR {128.385} \ CONFIG.CLKOUT4_PHASE_ERROR {114.796} \
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {256.00} \ CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {512.00} \
CONFIG.CLKOUT4_USED {true} \ CONFIG.CLKOUT4_USED {true} \
CONFIG.CLKOUT5_DRIVES {Buffer} \ CONFIG.CLKOUT5_DRIVES {BUFGCE} \
CONFIG.CLKOUT5_JITTER {116.118} \ CONFIG.CLKOUT5_JITTER {106.992} \
CONFIG.CLKOUT5_PHASE_ERROR {128.385} \ CONFIG.CLKOUT5_PHASE_ERROR {114.796} \
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {128.00} \ CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {512.00} \
CONFIG.CLKOUT5_USED {true} \ CONFIG.CLKOUT5_USED {true} \
CONFIG.CLKOUT6_DRIVES {Buffer} \ CONFIG.CLKOUT6_DRIVES {BUFGCE} \
CONFIG.CLKOUT6_JITTER {130.541} \ CONFIG.CLKOUT6_JITTER {120.323} \
CONFIG.CLKOUT6_PHASE_ERROR {128.385} \ CONFIG.CLKOUT6_PHASE_ERROR {114.796} \
CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {64.00} \ CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {256.00} \
CONFIG.CLKOUT6_USED {true} \ CONFIG.CLKOUT6_USED {true} \
CONFIG.CLKOUT7_DRIVES {Buffer} \ CONFIG.CLKOUT7_DRIVES {BUFGCE} \
CONFIG.CLKOUT7_JITTER {116.118} \ CONFIG.CLKOUT7_JITTER {106.992} \
CONFIG.CLKOUT7_PHASE_ERROR {128.385} \ CONFIG.CLKOUT7_PHASE_ERROR {114.796} \
CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {128.00} \ CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {512.00} \
CONFIG.CLKOUT7_USED {true} \ CONFIG.CLKOUT7_USED {true} \
CONFIG.CLK_OUT1_PORT {pll_ref_clk_out} \ CONFIG.CLK_OUT1_PORT {pll_ref_clk_out} \
CONFIG.CLK_OUT2_PORT {data_clk} \ CONFIG.CLK_OUT2_PORT {data_clk} \
@@ -1012,16 +919,16 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
CONFIG.CLK_OUT7_PORT {r1_rfdc_clk_2x} \ CONFIG.CLK_OUT7_PORT {r1_rfdc_clk_2x} \
CONFIG.ENABLE_CLOCK_MONITOR {false} \ CONFIG.ENABLE_CLOCK_MONITOR {false} \
CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \ CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \
CONFIG.MMCM_CLKFBOUT_MULT_F {20.000} \ CONFIG.MMCM_CLKFBOUT_MULT_F {16.000} \
CONFIG.MMCM_CLKIN1_PERIOD {15.625} \ CONFIG.MMCM_CLKIN1_PERIOD {15.625} \
CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
CONFIG.MMCM_CLKOUT0_DIVIDE_F {20.000} \ CONFIG.MMCM_CLKOUT0_DIVIDE_F {16.000} \
CONFIG.MMCM_CLKOUT1_DIVIDE {10} \ CONFIG.MMCM_CLKOUT1_DIVIDE {4} \
CONFIG.MMCM_CLKOUT2_DIVIDE {20} \ CONFIG.MMCM_CLKOUT2_DIVIDE {4} \
CONFIG.MMCM_CLKOUT3_DIVIDE {5} \ CONFIG.MMCM_CLKOUT3_DIVIDE {2} \
CONFIG.MMCM_CLKOUT4_DIVIDE {10} \ CONFIG.MMCM_CLKOUT4_DIVIDE {2} \
CONFIG.MMCM_CLKOUT5_DIVIDE {20} \ CONFIG.MMCM_CLKOUT5_DIVIDE {4} \
CONFIG.MMCM_CLKOUT6_DIVIDE {10} \ CONFIG.MMCM_CLKOUT6_DIVIDE {2} \
CONFIG.MMCM_DIVCLK_DIVIDE {1} \ CONFIG.MMCM_DIVCLK_DIVIDE {1} \
CONFIG.NUM_OUT_CLKS {7} \ CONFIG.NUM_OUT_CLKS {7} \
CONFIG.PHASE_DUTY_CONFIG {false} \ CONFIG.PHASE_DUTY_CONFIG {false} \
@@ -1109,9 +1016,6 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
CONFIG.C_IS_DUAL {1} \ CONFIG.C_IS_DUAL {1} \
] $reg_rfdc_tile_mapping ] $reg_rfdc_tile_mapping
# Create instance: rf_clock_buffers
create_hier_cell_rf_clock_buffers $hier_obj rf_clock_buffers
# Create instance: rf_data_converter, and set properties # Create instance: rf_data_converter, and set properties
set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ] set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ]
set_property -dict [ list \ set_property -dict [ list \
@@ -1588,36 +1492,32 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
connect_bd_net -net capture_sysref_0_sysref_out_rclk [get_bd_pins sysref_out_r0clk] [get_bd_pins capture_sysref/sysref_out_rclk] [get_bd_pins rf_data_converter/user_sysref_adc] [get_bd_pins rf_data_converter/user_sysref_dac] [get_bd_pins rf_nco_reset_0/dSysref] connect_bd_net -net capture_sysref_0_sysref_out_rclk [get_bd_pins sysref_out_r0clk] [get_bd_pins capture_sysref/sysref_out_rclk] [get_bd_pins rf_data_converter/user_sysref_adc] [get_bd_pins rf_data_converter/user_sysref_dac] [get_bd_pins rf_nco_reset_0/dSysref]
connect_bd_net -net capture_sysref_sysref_out_pclk [get_bd_pins sysref_out_pclk] [get_bd_pins capture_sysref/sysref_out_pclk] connect_bd_net -net capture_sysref_sysref_out_pclk [get_bd_pins sysref_out_pclk] [get_bd_pins capture_sysref/sysref_out_pclk]
connect_bd_net -net clk_in1_0_1 [get_bd_pins pll_ref_clk_in] [get_bd_pins data_clock_mmcm/clk_in1] connect_bd_net -net clk_in1_0_1 [get_bd_pins pll_ref_clk_in] [get_bd_pins data_clock_mmcm/clk_in1]
connect_bd_net -net clock_gates_0_aEnableRf1Bufg2x [get_bd_pins clock_gates_0/aEnableRf1Bufg2x] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_2x_ce] connect_bd_net -net clock_gates_0_aEnableRf1Bufg2x [get_bd_pins clock_gates_0/aEnableRf1Bufg2x] [get_bd_pins data_clock_mmcm/r1_rfdc_clk_2x_ce]
connect_bd_net -net clock_gates_0_cSoftwareStatus [get_bd_pins clock_gates_0/rSoftwareStatus] [get_bd_pins reg_clock_gate_control/gpio2_io_i] connect_bd_net -net clock_gates_0_cSoftwareStatus [get_bd_pins clock_gates_0/rSoftwareStatus] [get_bd_pins reg_clock_gate_control/gpio2_io_i]
connect_bd_net -net clock_gates_0_rGatedBaseClksValid [get_bd_pins gated_base_clks_valid_clk40] [get_bd_pins clock_gates_0/rGatedBaseClksValid] connect_bd_net -net clock_gates_0_rGatedBaseClksValid [get_bd_pins gated_base_clks_valid_clk40] [get_bd_pins clock_gates_0/rGatedBaseClksValid]
connect_bd_net -net clock_gates_0_rPllLocked [get_bd_pins data_clock_locked] [get_bd_pins clock_gates_0/rPllLocked] connect_bd_net -net clock_gates_0_rPllLocked [get_bd_pins data_clock_locked] [get_bd_pins clock_gates_0/rPllLocked]
connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRf0Bufg2x] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_2x_ce] connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRf0Bufg2x] [get_bd_pins data_clock_mmcm/r0_rfdc_clk_2x_ce]
connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRf0Bufg1x] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_ce] connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRf0Bufg1x] [get_bd_pins data_clock_mmcm/r0_rfdc_clk_ce]
connect_bd_net -net dac_reset_pulse_r0clk_1 [get_bd_pins dac_reset_pulse_r0clk] [get_bd_pins rf_reset_controller_0/rDacResetPulse] connect_bd_net -net dac_reset_pulse_r0clk_1 [get_bd_pins dac_reset_pulse_r0clk] [get_bd_pins rf_reset_controller_0/rDacResetPulse]
connect_bd_net -net dac_reset_pulse_r1clk_1 [get_bd_pins dac_reset_pulse_r1clk] [get_bd_pins rf_reset_controller_1/rDacResetPulse] connect_bd_net -net dac_reset_pulse_r1clk_1 [get_bd_pins dac_reset_pulse_r1clk] [get_bd_pins rf_reset_controller_1/rDacResetPulse]
connect_bd_net -net data_clock_mmcm_data_clk [get_bd_pins data_clk] [get_bd_pins data_clock_mmcm/data_clk] connect_bd_net -net data_clock_mmcm_data_clk [get_bd_pins data_clk] [get_bd_pins data_clock_mmcm/data_clk]
connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_pins data_clk_2x] [get_bd_pins data_clock_mmcm/data_clk_2x] connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_pins data_clk_2x] [get_bd_pins data_clock_mmcm/data_clk_2x]
connect_bd_net -net data_clock_mmcm_locked [get_bd_pins clock_gates_0/aPllLocked] [get_bd_pins data_clock_mmcm/locked] connect_bd_net -net data_clock_mmcm_locked [get_bd_pins clock_gates_0/aPllLocked] [get_bd_pins data_clock_mmcm/locked]
connect_bd_net -net data_clock_mmcm_r0_rfdc_clk [get_bd_pins data_clock_mmcm/r0_rfdc_clk] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_pll] connect_bd_net -net data_clock_mmcm_r0_rfdc_clk [get_bd_pins radio0_rfdc_clk] [get_bd_pins axi_interconnect_rf/M02_ACLK] [get_bd_pins calibration_muxes/s_axi_aclk_0] [get_bd_pins calibration_muxes/s_axi_aclk_1] [get_bd_pins capture_sysref/rfdc_clk] [get_bd_pins data_clock_mmcm/r0_rfdc_clk] [get_bd_pins reg_invert_iq_radio0/s_axi_aclk] [get_bd_pins rf_data_converter/m0_axis_aclk] [get_bd_pins rf_data_converter/m1_axis_aclk] [get_bd_pins rf_data_converter/s0_axis_aclk] [get_bd_pins rf_nco_reset_0/DataClk] [get_bd_pins rf_reset_controller_0/RfClk]
connect_bd_net -net data_clock_mmcm_r0_rfdc_clk_2x [get_bd_pins data_clock_mmcm/r0_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_2x_pll] connect_bd_net -net data_clock_mmcm_r0_rfdc_clk_2x [get_bd_pins radio0_rfdc_clk_2x] [get_bd_pins data_clock_mmcm/r0_rfdc_clk_2x] [get_bd_pins rf_reset_controller_0/RfClk2x]
connect_bd_net -net data_clock_mmcm_r1_rfdc_clk [get_bd_pins data_clock_mmcm/r1_rfdc_clk] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_pll] connect_bd_net -net data_clock_mmcm_r1_rfdc_clk [get_bd_pins radio1_rfdc_clk_1x] [get_bd_pins axi_interconnect_rf/M11_ACLK] [get_bd_pins data_clock_mmcm/r1_rfdc_clk] [get_bd_pins reg_invert_iq_radio1/s_axi_aclk] [get_bd_pins rf_data_converter/m2_axis_aclk] [get_bd_pins rf_data_converter/m3_axis_aclk] [get_bd_pins rf_data_converter/s1_axis_aclk] [get_bd_pins rf_reset_controller_1/RfClk]
connect_bd_net -net data_clock_mmcm_r1_rfdc_clk_2x [get_bd_pins data_clock_mmcm/r1_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_2x_pll] connect_bd_net -net data_clock_mmcm_r1_rfdc_clk_2x [get_bd_pins radio1_rfdc_clk_2x] [get_bd_pins data_clock_mmcm/r1_rfdc_clk_2x] [get_bd_pins rf_reset_controller_1/RfClk2x]
connect_bd_net -net data_clock_mmcm_rfdc_clk [get_bd_pins radio0_rfdc_clk] [get_bd_pins axi_interconnect_rf/M02_ACLK] [get_bd_pins calibration_muxes/s_axi_aclk_0] [get_bd_pins calibration_muxes/s_axi_aclk_1] [get_bd_pins capture_sysref/rfdc_clk] [get_bd_pins reg_invert_iq_radio0/s_axi_aclk] [get_bd_pins rf_clock_buffers/rf0_clk_1x] [get_bd_pins rf_data_converter/m0_axis_aclk] [get_bd_pins rf_data_converter/m1_axis_aclk] [get_bd_pins rf_data_converter/s0_axis_aclk] [get_bd_pins rf_nco_reset_0/DataClk] [get_bd_pins rf_reset_controller_0/RfClk]
connect_bd_net -net data_clock_mmcm_rfdc_clk_2x [get_bd_pins radio0_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/rf0_clk_2x] [get_bd_pins rf_reset_controller_0/RfClk2x]
connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_pins pll_ref_clk_out] [get_bd_pins capture_sysref/pll_ref_clk] [get_bd_pins data_clock_mmcm/pll_ref_clk_out] [get_bd_pins rf_reset_controller_0/PllRefClk] [get_bd_pins rf_reset_controller_1/PllRefClk] connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_pins pll_ref_clk_out] [get_bd_pins capture_sysref/pll_ref_clk] [get_bd_pins data_clock_mmcm/pll_ref_clk_out] [get_bd_pins rf_reset_controller_0/PllRefClk] [get_bd_pins rf_reset_controller_1/PllRefClk]
connect_bd_net -net enable_gated_clocks_clk40_1 [get_bd_pins enable_gated_clocks_clk40] [get_bd_pins clock_gates_0/rSafeToEnableGatedClks] connect_bd_net -net enable_gated_clocks_clk40_1 [get_bd_pins enable_gated_clocks_clk40] [get_bd_pins clock_gates_0/rSafeToEnableGatedClks]
connect_bd_net -net enable_rclk_0_1 [get_bd_pins enable_sysref_r0clk] [get_bd_pins capture_sysref/enable_rclk] connect_bd_net -net enable_rclk_0_1 [get_bd_pins enable_sysref_r0clk] [get_bd_pins capture_sysref/enable_rclk]
connect_bd_net -net gpio2_io_i_0_2 [get_bd_pins rf_dsp_info_sclk] [get_bd_pins reg_rf_axi_status/gpio2_io_i] connect_bd_net -net gpio2_io_i_0_2 [get_bd_pins rf_dsp_info_sclk] [get_bd_pins reg_rf_axi_status/gpio2_io_i]
connect_bd_net -net gpio_io_i_0_1 [get_bd_pins rf_axi_status_sclk] [get_bd_pins reg_rf_axi_status/gpio_io_i] connect_bd_net -net gpio_io_i_0_1 [get_bd_pins rf_axi_status_sclk] [get_bd_pins reg_rf_axi_status/gpio_io_i]
connect_bd_net -net radio1_rfdc_clk_ce_1 [get_bd_pins clock_gates_0/aEnableRf1Bufg1x] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_ce] connect_bd_net -net radio1_rfdc_clk_ce_1 [get_bd_pins clock_gates_0/aEnableRf1Bufg1x] [get_bd_pins data_clock_mmcm/r1_rfdc_clk_ce]
connect_bd_net -net reg_invert_iq_radio1_gpio_io_o [get_bd_pins reg_invert_iq_radio1/gpio_io_o] [get_bd_pins slice_iqswap_11_8_radio1/Din] [get_bd_pins slice_iqswap_3_0_radio1/Din] connect_bd_net -net reg_invert_iq_radio1_gpio_io_o [get_bd_pins reg_invert_iq_radio1/gpio_io_o] [get_bd_pins slice_iqswap_11_8_radio1/Din] [get_bd_pins slice_iqswap_3_0_radio1/Din]
connect_bd_net -net reg_reset_mmcm_gpio_io_o [get_bd_pins axi_interconnect_rf/M01_ARESETN] [get_bd_pins clock_gates_0/rPllReset_n] [get_bd_pins data_clock_mmcm/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/gpio_io_o] connect_bd_net -net reg_reset_mmcm_gpio_io_o [get_bd_pins axi_interconnect_rf/M01_ARESETN] [get_bd_pins clock_gates_0/rPllReset_n] [get_bd_pins data_clock_mmcm/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/gpio_io_o]
connect_bd_net -net reg_rf_reset_control1_gpio_io_o [get_bd_pins clock_gates_0/rSoftwareControl] [get_bd_pins reg_clock_gate_control/gpio_io_o] connect_bd_net -net reg_rf_reset_control1_gpio_io_o [get_bd_pins clock_gates_0/rSoftwareControl] [get_bd_pins reg_clock_gate_control/gpio_io_o]
connect_bd_net -net reg_rf_reset_control_radio1_gpio_io_o [get_bd_pins reg_rf_reset_control_radio1/gpio_io_o] [get_bd_pins rf_reset_controller_1/cSoftwareControl] connect_bd_net -net reg_rf_reset_control_radio1_gpio_io_o [get_bd_pins reg_rf_reset_control_radio1/gpio_io_o] [get_bd_pins rf_reset_controller_1/cSoftwareControl]
connect_bd_net -net reg_rf_resets_gpio_io_o [get_bd_pins reg_rf_reset_control_radio0/gpio_io_o] [get_bd_pins rf_reset_controller_0/cSoftwareControl] connect_bd_net -net reg_rf_resets_gpio_io_o [get_bd_pins reg_rf_reset_control_radio0/gpio_io_o] [get_bd_pins rf_reset_controller_0/cSoftwareControl]
connect_bd_net -net rf_clock_buffers_rf1_clk_1x [get_bd_pins radio1_rfdc_clk_1x] [get_bd_pins axi_interconnect_rf/M11_ACLK] [get_bd_pins reg_invert_iq_radio1/s_axi_aclk] [get_bd_pins rf_clock_buffers/rf1_clk_1x] [get_bd_pins rf_data_converter/m2_axis_aclk] [get_bd_pins rf_data_converter/m3_axis_aclk] [get_bd_pins rf_data_converter/s1_axis_aclk] [get_bd_pins rf_reset_controller_1/RfClk]
connect_bd_net -net rf_clock_buffers_rf1_clk_2x [get_bd_pins radio1_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/rf1_clk_2x] [get_bd_pins rf_reset_controller_1/RfClk2x]
connect_bd_net -net rf_data_converter_adc0_01_over_threshold1 [get_bd_pins ThresholdRegister/In0] [get_bd_pins rf_data_converter/adc0_01_over_threshold1] connect_bd_net -net rf_data_converter_adc0_01_over_threshold1 [get_bd_pins ThresholdRegister/In0] [get_bd_pins rf_data_converter/adc0_01_over_threshold1]
connect_bd_net -net rf_data_converter_adc0_01_over_threshold2 [get_bd_pins ThresholdRegister/In1] [get_bd_pins rf_data_converter/adc0_01_over_threshold2] connect_bd_net -net rf_data_converter_adc0_01_over_threshold2 [get_bd_pins ThresholdRegister/In1] [get_bd_pins rf_data_converter/adc0_01_over_threshold2]
connect_bd_net -net rf_data_converter_adc0_23_over_threshold1 [get_bd_pins ThresholdRegister/In2] [get_bd_pins rf_data_converter/adc0_23_over_threshold1] connect_bd_net -net rf_data_converter_adc0_23_over_threshold1 [get_bd_pins ThresholdRegister/In2] [get_bd_pins rf_data_converter/adc0_23_over_threshold1]
@@ -3441,96 +3341,96 @@ proc create_root_design { parentCell } {
set adc_tile224_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_i ] set adc_tile224_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_i ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile224_ch0_dout_i ] $adc_tile224_ch0_dout_i
set adc_tile224_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_q ] set adc_tile224_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_q ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile224_ch0_dout_q ] $adc_tile224_ch0_dout_q
set adc_tile224_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch0_vin ] set adc_tile224_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch0_vin ]
set adc_tile224_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_i ] set adc_tile224_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_i ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile224_ch1_dout_i ] $adc_tile224_ch1_dout_i
set adc_tile224_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_q ] set adc_tile224_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_q ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile224_ch1_dout_q ] $adc_tile224_ch1_dout_q
set adc_tile224_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch1_vin ] set adc_tile224_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch1_vin ]
set adc_tile225_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch0_dout_i ] set adc_tile225_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch0_dout_i ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile225_ch0_dout_i ] $adc_tile225_ch0_dout_i
set adc_tile225_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch0_dout_q ] set adc_tile225_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch0_dout_q ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile225_ch0_dout_q ] $adc_tile225_ch0_dout_q
set adc_tile225_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile225_ch0_vin ] set adc_tile225_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile225_ch0_vin ]
set adc_tile225_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch1_dout_i ] set adc_tile225_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch1_dout_i ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile225_ch1_dout_i ] $adc_tile225_ch1_dout_i
set adc_tile225_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch1_dout_q ] set adc_tile225_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch1_dout_q ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile225_ch1_dout_q ] $adc_tile225_ch1_dout_q
set adc_tile225_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile225_ch1_vin ] set adc_tile225_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile225_ch1_vin ]
set adc_tile226_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_i ] set adc_tile226_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_i ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile226_ch0_dout_i ] $adc_tile226_ch0_dout_i
set adc_tile226_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_q ] set adc_tile226_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_q ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile226_ch0_dout_q ] $adc_tile226_ch0_dout_q
set adc_tile226_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch0_vin ] set adc_tile226_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch0_vin ]
set adc_tile226_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_i ] set adc_tile226_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_i ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile226_ch1_dout_i ] $adc_tile226_ch1_dout_i
set adc_tile226_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_q ] set adc_tile226_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_q ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile226_ch1_dout_q ] $adc_tile226_ch1_dout_q
set adc_tile226_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch1_vin ] set adc_tile226_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch1_vin ]
set adc_tile227_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch0_dout_i ] set adc_tile227_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch0_dout_i ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile227_ch0_dout_i ] $adc_tile227_ch0_dout_i
set adc_tile227_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch0_dout_q ] set adc_tile227_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch0_dout_q ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile227_ch0_dout_q ] $adc_tile227_ch0_dout_q
set adc_tile227_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile227_ch0_vin ] set adc_tile227_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile227_ch0_vin ]
set adc_tile227_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch1_dout_i ] set adc_tile227_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch1_dout_i ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $adc_tile227_ch1_dout_i ] $adc_tile227_ch1_dout_i
set adc_tile227_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch1_dout_q ] set adc_tile227_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch1_dout_q ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
CONFIG.PHASE {0.0} \ CONFIG.PHASE {0.0} \
] $adc_tile227_ch1_dout_q ] $adc_tile227_ch1_dout_q
@@ -3542,7 +3442,7 @@ proc create_root_design { parentCell } {
set dac_tile228_ch0_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch0_din ] set dac_tile228_ch0_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch0_din ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
CONFIG.HAS_TKEEP {0} \ CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \ CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \ CONFIG.HAS_TREADY {1} \
@@ -3558,7 +3458,7 @@ proc create_root_design { parentCell } {
set dac_tile228_ch1_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch1_din ] set dac_tile228_ch1_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch1_din ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
CONFIG.HAS_TKEEP {0} \ CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \ CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \ CONFIG.HAS_TREADY {1} \
@@ -3574,7 +3474,7 @@ proc create_root_design { parentCell } {
set dac_tile228_ch2_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch2_din ] set dac_tile228_ch2_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch2_din ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
CONFIG.HAS_TKEEP {0} \ CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \ CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \ CONFIG.HAS_TREADY {1} \
@@ -3591,7 +3491,7 @@ proc create_root_design { parentCell } {
set dac_tile228_ch3_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch3_din ] set dac_tile228_ch3_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch3_din ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
CONFIG.HAS_TKEEP {0} \ CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \ CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \ CONFIG.HAS_TREADY {1} \
@@ -3608,7 +3508,7 @@ proc create_root_design { parentCell } {
set dac_tile229_ch0_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch0_din ] set dac_tile229_ch0_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch0_din ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
CONFIG.HAS_TKEEP {0} \ CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \ CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \ CONFIG.HAS_TREADY {1} \
@@ -3624,7 +3524,7 @@ proc create_root_design { parentCell } {
set dac_tile229_ch1_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch1_din ] set dac_tile229_ch1_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch1_din ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
CONFIG.HAS_TKEEP {0} \ CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \ CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \ CONFIG.HAS_TREADY {1} \
@@ -3640,7 +3540,7 @@ proc create_root_design { parentCell } {
set dac_tile229_ch2_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch2_din ] set dac_tile229_ch2_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch2_din ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
CONFIG.HAS_TKEEP {0} \ CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \ CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \ CONFIG.HAS_TREADY {1} \
@@ -3657,7 +3557,7 @@ proc create_root_design { parentCell } {
set dac_tile229_ch3_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch3_din ] set dac_tile229_ch3_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch3_din ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
CONFIG.HAS_TKEEP {0} \ CONFIG.HAS_TKEEP {0} \
CONFIG.HAS_TLAST {0} \ CONFIG.HAS_TLAST {0} \
CONFIG.HAS_TREADY {1} \ CONFIG.HAS_TREADY {1} \
@@ -3918,11 +3818,11 @@ proc create_root_design { parentCell } {
set dac_reset_pulse_r1clk [ create_bd_port -dir I dac_reset_pulse_r1clk ] set dac_reset_pulse_r1clk [ create_bd_port -dir I dac_reset_pulse_r1clk ]
set data_clk [ create_bd_port -dir O -type clk data_clk ] set data_clk [ create_bd_port -dir O -type clk data_clk ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {128000000} \ CONFIG.FREQ_HZ {256000000} \
] $data_clk ] $data_clk
set data_clk_2x [ create_bd_port -dir O -type clk data_clk_2x ] set data_clk_2x [ create_bd_port -dir O -type clk data_clk_2x ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {256000000} \ CONFIG.FREQ_HZ {512000000} \
] $data_clk_2x ] $data_clk_2x
set data_clock_locked [ create_bd_port -dir O data_clock_locked ] set data_clock_locked [ create_bd_port -dir O data_clock_locked ]
set enable_gated_clocks_clk40 [ create_bd_port -dir I enable_gated_clocks_clk40 ] set enable_gated_clocks_clk40 [ create_bd_port -dir I enable_gated_clocks_clk40 ]
@@ -3960,20 +3860,20 @@ proc create_root_design { parentCell } {
] $pll_ref_clk_out ] $pll_ref_clk_out
set radio0_invert_adc_iq_r0clk [ create_bd_port -dir O -from 3 -to 0 radio0_invert_adc_iq_r0clk ] set radio0_invert_adc_iq_r0clk [ create_bd_port -dir O -from 3 -to 0 radio0_invert_adc_iq_r0clk ]
set radio0_invert_dac_iq_r0clk [ create_bd_port -dir O -from 3 -to 0 radio0_invert_dac_iq_r0clk ] set radio0_invert_dac_iq_r0clk [ create_bd_port -dir O -from 3 -to 0 radio0_invert_dac_iq_r0clk ]
set radio0_rfdc_clk_1x [ create_bd_port -dir O -from 0 -to 0 -type clk radio0_rfdc_clk_1x ] set radio0_rfdc_clk_1x [ create_bd_port -dir O -type clk radio0_rfdc_clk_1x ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.ASSOCIATED_BUSIF {adc_tile224_ch0_dout_i:adc_tile224_ch1_dout_i:adc_tile224_ch1_dout_q:adc_tile224_ch0_dout_q:dac_tile228_ch0_din:dac_tile228_ch1_din:dac_tile229_ch0_din:dac_tile229_ch1_din:adc_tile226_ch0_dout_i:adc_tile226_ch0_dout_q:adc_tile226_ch1_dout_i:adc_tile226_ch1_dout_q} \ CONFIG.ASSOCIATED_BUSIF {adc_tile224_ch0_dout_i:adc_tile224_ch1_dout_i:adc_tile224_ch1_dout_q:adc_tile224_ch0_dout_q:dac_tile228_ch0_din:dac_tile228_ch1_din:dac_tile229_ch0_din:dac_tile229_ch1_din:adc_tile226_ch0_dout_i:adc_tile226_ch0_dout_q:adc_tile226_ch1_dout_i:adc_tile226_ch1_dout_q} \
CONFIG.ASSOCIATED_RESET {adc_tile224_axis_resetn_rclk:adc_tile226_axis_resetn_rclk:dac_tile228_axis_resetn_rclk:dac_tile229_axis_resetn_rclk} \ CONFIG.ASSOCIATED_RESET {adc_tile224_axis_resetn_rclk:adc_tile226_axis_resetn_rclk:dac_tile228_axis_resetn_rclk:dac_tile229_axis_resetn_rclk} \
CONFIG.FREQ_HZ {64000000} \ CONFIG.FREQ_HZ {256000000} \
] $radio0_rfdc_clk_1x ] $radio0_rfdc_clk_1x
set radio0_rfdc_clk_2x [ create_bd_port -dir O -from 0 -to 0 -type clk radio0_rfdc_clk_2x ] set radio0_rfdc_clk_2x [ create_bd_port -dir O -type clk radio0_rfdc_clk_2x ]
set_property -dict [ list \ set_property -dict [ list \
CONFIG.FREQ_HZ {128000000} \ CONFIG.FREQ_HZ {512000000} \
] $radio0_rfdc_clk_2x ] $radio0_rfdc_clk_2x
set radio1_invert_adc_iq_r1clk [ create_bd_port -dir O -from 3 -to 0 radio1_invert_adc_iq_r1clk ] set radio1_invert_adc_iq_r1clk [ create_bd_port -dir O -from 3 -to 0 radio1_invert_adc_iq_r1clk ]
set radio1_invert_dac_iq_r1clk [ create_bd_port -dir O -from 3 -to 0 radio1_invert_dac_iq_r1clk ] set radio1_invert_dac_iq_r1clk [ create_bd_port -dir O -from 3 -to 0 radio1_invert_dac_iq_r1clk ]
set radio1_rfdc_clk_1x [ create_bd_port -dir O -from 0 -to 0 radio1_rfdc_clk_1x ] set radio1_rfdc_clk_1x [ create_bd_port -dir O radio1_rfdc_clk_1x ]
set radio1_rfdc_clk_2x [ create_bd_port -dir O -from 0 -to 0 radio1_rfdc_clk_2x ] set radio1_rfdc_clk_2x [ create_bd_port -dir O radio1_rfdc_clk_2x ]
set rf_axi_status_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_axi_status_clk40 ] set rf_axi_status_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_axi_status_clk40 ]
set rf_dsp_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_dsp_info_clk40 ] set rf_dsp_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_dsp_info_clk40 ]
set rf_rfdc_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_rfdc_info_clk40 ] set rf_rfdc_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_rfdc_info_clk40 ]
top/x400/x4xx.sv
+10 -5
View File
@@ -461,12 +461,17 @@ module x4xx (
`ifdef X440 `ifdef X440
wire clk5; wire clk5;
clock_div #( BUFGCE_DIV #(
.N(2) .BUFGCE_DIVIDE(2),
.SIM_DEVICE("ULTRASCALE_PLUS"),
.IS_CE_INVERTED(1'b0),
.IS_CLR_INVERTED(1'b0),
.IS_I_INVERTED(1'b0)
) clock_div_5mhz ( ) clock_div_5mhz (
.clk_in (base_ref_clk), .I (base_ref_clk),
.clk_in_rst (brc_rst), .CLR (brc_rst),
.clk_out (clk5) .CE (1'b1),
.O (clk5)
); );
`endif `endif