fpga: x400: refactor RFDC block diagrams and timing constraints
Original-commit: a7bce74be154de9a68d6bdf2f9a6651b480b6dfa
This commit is contained in:
Friedrich Wenisch
committed by
Wade Fife
Wade Fife
parent
f480008cf9
commit
3ed06cc861
@@ -1,14 +1,14 @@
|
||||
set script_loc [file normalize [info script]]
|
||||
set script_dir [file dirname $script_loc]
|
||||
|
||||
read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
|
||||
read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
|
||||
read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
|
||||
read_vhdl -library work $script_dir/../../../regmap/x410/PkgRFDC_REGS_REGMAP.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/x410/x410_rf_reset_controller.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/x410/x410_clock_gates.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
|
||||
read_vhdl -library work $script_dir/../../../regmap/x410/PkgRFDC_REGS_REGMAP.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
|
||||
read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
|
||||
read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
|
||||
read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
|
||||
read_vhdl -library work $script_dir/../../../rf/x410/x410_clock_gates.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/x410/x410_rf_reset_controller.vhd
|
||||
|
||||
@@ -154,7 +154,6 @@ xilinx.com:ip:xlslice:1.0\
|
||||
xilinx.com:ip:axi_protocol_converter:2.1\
|
||||
xilinx.com:ip:axi_dma:7.1\
|
||||
xilinx.com:ip:smartconnect:1.0\
|
||||
xilinx.com:ip:util_ds_buf:2.2\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
@@ -214,74 +213,6 @@ if { $bCheckIPsPassed != 1 } {
|
||||
##################################################################
|
||||
|
||||
|
||||
# Hierarchical cell: rf_clock_buffers
|
||||
proc create_hier_cell_rf_clock_buffers { parentCell nameHier } {
|
||||
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rf_clock_buffers() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
# Create cell and set as current instance
|
||||
set hier_obj [create_bd_cell -type hier $nameHier]
|
||||
current_bd_instance $hier_obj
|
||||
|
||||
# Create interface pins
|
||||
|
||||
# Create pins
|
||||
create_bd_pin -dir O -from 0 -to 0 rfdc_clk
|
||||
create_bd_pin -dir O -from 0 -to 0 rfdc_clk_2x
|
||||
create_bd_pin -dir I -from 0 -to 0 rfdc_clk_2x_ce
|
||||
create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_2x_pll
|
||||
create_bd_pin -dir I -from 0 -to 0 rfdc_clk_ce
|
||||
create_bd_pin -dir I -from 0 -to 0 -type clk rfdc_clk_pll
|
||||
|
||||
# Create instance: rfdc_clk_1x_buf, and set properties
|
||||
set rfdc_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_1x_buf ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_BUF_TYPE {BUFGCE} \
|
||||
] $rfdc_clk_1x_buf
|
||||
|
||||
# Create instance: rfdc_clk_2x_buf, and set properties
|
||||
set rfdc_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rfdc_clk_2x_buf ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_BUF_TYPE {BUFGCE} \
|
||||
] $rfdc_clk_2x_buf
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net BUFGCE_I2_1 [get_bd_pins rfdc_clk_2x_pll] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_I]
|
||||
connect_bd_net -net rfdc_clk_1 [get_bd_pins rfdc_clk_pll] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_I]
|
||||
connect_bd_net -net rfdc_clk_1x_buf_BUFGCE_O [get_bd_pins rfdc_clk] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_O]
|
||||
connect_bd_net -net rfdc_clk_2x_buf_BUFGCE_O [get_bd_pins rfdc_clk_2x] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_O]
|
||||
connect_bd_net -net rfdc_clk_2x_ce_1 [get_bd_pins rfdc_clk_2x_ce] [get_bd_pins rfdc_clk_2x_buf/BUFGCE_CE]
|
||||
connect_bd_net -net rfdc_clk_ce_1 [get_bd_pins rfdc_clk_ce] [get_bd_pins rfdc_clk_1x_buf/BUFGCE_CE]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
}
|
||||
|
||||
# Hierarchical cell: calibration_muxes
|
||||
proc create_hier_cell_calibration_muxes { parentCell nameHier } {
|
||||
|
||||
@@ -797,8 +728,8 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
create_bd_pin -dir I -from 31 -to 0 rf_axi_status_sclk
|
||||
create_bd_pin -dir I -from 31 -to 0 rf_dsp_info_sclk
|
||||
create_bd_pin -dir I -from 31 -to 0 rf_rfdc_info_sclk
|
||||
create_bd_pin -dir O -from 0 -to 0 rfdc_clk
|
||||
create_bd_pin -dir O -from 0 -to 0 rfdc_clk_2x
|
||||
create_bd_pin -dir O rfdc_clk
|
||||
create_bd_pin -dir O rfdc_clk_2x
|
||||
create_bd_pin -dir O -type intr rfdc_irq
|
||||
create_bd_pin -dir I -type rst s_axi_config_aresetn
|
||||
create_bd_pin -dir I -type clk s_axi_config_clk
|
||||
@@ -858,31 +789,34 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
# Create instance: const_1, and set properties
|
||||
set const_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 const_1 ]
|
||||
|
||||
# Create instance: constant_1, and set properties
|
||||
set constant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_1 ]
|
||||
|
||||
# Create instance: data_clock_mmcm, and set properties
|
||||
set data_clock_mmcm [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 data_clock_mmcm ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.AXI_DRP {true} \
|
||||
CONFIG.CLKIN1_JITTER_PS {162.76} \
|
||||
CONFIG.CLKOUT1_DRIVES {Buffer} \
|
||||
CONFIG.CLKOUT1_DRIVES {BUFG} \
|
||||
CONFIG.CLKOUT1_JITTER {116.960} \
|
||||
CONFIG.CLKOUT1_PHASE_ERROR {124.626} \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {61.44} \
|
||||
CONFIG.CLKOUT2_DRIVES {Buffer} \
|
||||
CONFIG.CLKOUT2_DRIVES {No_buffer} \
|
||||
CONFIG.CLKOUT2_JITTER {104.559} \
|
||||
CONFIG.CLKOUT2_PHASE_ERROR {124.626} \
|
||||
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {122.88} \
|
||||
CONFIG.CLKOUT2_USED {true} \
|
||||
CONFIG.CLKOUT3_DRIVES {Buffer} \
|
||||
CONFIG.CLKOUT3_DRIVES {BUFGCE} \
|
||||
CONFIG.CLKOUT3_JITTER {98.017} \
|
||||
CONFIG.CLKOUT3_PHASE_ERROR {124.626} \
|
||||
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {184.32} \
|
||||
CONFIG.CLKOUT3_USED {true} \
|
||||
CONFIG.CLKOUT4_DRIVES {Buffer} \
|
||||
CONFIG.CLKOUT4_DRIVES {No_buffer} \
|
||||
CONFIG.CLKOUT4_JITTER {93.671} \
|
||||
CONFIG.CLKOUT4_PHASE_ERROR {124.626} \
|
||||
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {245.76} \
|
||||
CONFIG.CLKOUT4_USED {true} \
|
||||
CONFIG.CLKOUT5_DRIVES {Buffer} \
|
||||
CONFIG.CLKOUT5_DRIVES {BUFGCE} \
|
||||
CONFIG.CLKOUT5_JITTER {87.938} \
|
||||
CONFIG.CLKOUT5_PHASE_ERROR {124.626} \
|
||||
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {368.64} \
|
||||
@@ -991,9 +925,6 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
CONFIG.C_IS_DUAL {1} \
|
||||
] $reg_rfdc_tile_mapping
|
||||
|
||||
# Create instance: rf_clock_buffers
|
||||
create_hier_cell_rf_clock_buffers $hier_obj rf_clock_buffers
|
||||
|
||||
# Create instance: rf_data_converter, and set properties
|
||||
set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ]
|
||||
set_property -dict [ list \
|
||||
@@ -1384,18 +1315,16 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
connect_bd_net -net clock_gates_0_cSoftwareStatus [get_bd_pins clock_gates_0/rSoftwareStatus] [get_bd_pins reg_clock_gate_control/gpio2_io_i]
|
||||
connect_bd_net -net clock_gates_0_rGatedBaseClksValid [get_bd_pins gated_base_clks_valid_clk40] [get_bd_pins clock_gates_0/rGatedBaseClksValid]
|
||||
connect_bd_net -net clock_gates_0_rPllLocked [get_bd_pins data_clock_locked] [get_bd_pins clock_gates_0/rPllLocked]
|
||||
connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg2x] [get_bd_pins rf_clock_buffers/rfdc_clk_2x_ce]
|
||||
connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg1x] [get_bd_pins rf_clock_buffers/rfdc_clk_ce]
|
||||
connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg2x] [get_bd_pins data_clock_mmcm/rfdc_clk_2x_ce]
|
||||
connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRfBufg1x] [get_bd_pins data_clock_mmcm/rfdc_clk_ce]
|
||||
connect_bd_net -net dac_reset_pulse_dclk_1 [get_bd_pins dac_reset_pulse_dclk] [get_bd_pins rf_reset_controller_0/dDacResetPulse] [get_bd_pins rf_reset_controller_1/dDacResetPulse]
|
||||
connect_bd_net -net data_clk_2x_pll [get_bd_pins clock_gates_0/DataClk2xPll] [get_bd_pins data_clock_mmcm/data_clk_2x]
|
||||
connect_bd_net -net data_clock_mmcm_data_clk [get_bd_pins data_clk] [get_bd_pins clock_gates_0/DataClk1x] [get_bd_pins rf_nco_reset_0/DataClk] [get_bd_pins rf_reset_controller_0/DataClk] [get_bd_pins rf_reset_controller_1/DataClk]
|
||||
connect_bd_net -net data_clock_mmcm_data_clk1 [get_bd_pins clock_gates_0/DataClk1xPll] [get_bd_pins data_clock_mmcm/data_clk]
|
||||
connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_pins data_clk_2x] [get_bd_pins clock_gates_0/DataClk2x] [get_bd_pins rf_reset_controller_0/DataClk2x] [get_bd_pins rf_reset_controller_1/DataClk2x]
|
||||
connect_bd_net -net data_clock_mmcm_locked [get_bd_pins clock_gates_0/aPllLocked] [get_bd_pins data_clock_mmcm/locked]
|
||||
connect_bd_net -net data_clock_mmcm_rfdc_clk [get_bd_pins rfdc_clk] [get_bd_pins calibration_muxes/s_axi_aclk_0] [get_bd_pins capture_sysref/rfdc_clk] [get_bd_pins rf_clock_buffers/rfdc_clk] [get_bd_pins rf_data_converter/m0_axis_aclk] [get_bd_pins rf_data_converter/m2_axis_aclk] [get_bd_pins rf_data_converter/s0_axis_aclk] [get_bd_pins rf_data_converter/s1_axis_aclk] [get_bd_pins rf_reset_controller_0/RfClk] [get_bd_pins rf_reset_controller_1/RfClk]
|
||||
connect_bd_net -net data_clock_mmcm_rfdc_clk1 [get_bd_pins data_clock_mmcm/rfdc_clk] [get_bd_pins rf_clock_buffers/rfdc_clk_pll]
|
||||
connect_bd_net -net data_clock_mmcm_rfdc_clk_2x [get_bd_pins rfdc_clk_2x] [get_bd_pins axi_interconnect_rf/M02_ACLK] [get_bd_pins axi_interconnect_rf/M11_ACLK] [get_bd_pins reg_invert_iq_radio0/s_axi_aclk] [get_bd_pins reg_invert_iq_radio1/s_axi_aclk] [get_bd_pins rf_clock_buffers/rfdc_clk_2x] [get_bd_pins rf_reset_controller_0/RfClk2x] [get_bd_pins rf_reset_controller_1/RfClk2x]
|
||||
connect_bd_net -net data_clock_mmcm_rfdc_clk_2x1 [get_bd_pins data_clock_mmcm/rfdc_clk_2x] [get_bd_pins rf_clock_buffers/rfdc_clk_2x_pll]
|
||||
connect_bd_net -net data_clock_mmcm_rfdc_clk [get_bd_pins rfdc_clk] [get_bd_pins calibration_muxes/s_axi_aclk_0] [get_bd_pins capture_sysref/rfdc_clk] [get_bd_pins data_clock_mmcm/rfdc_clk] [get_bd_pins rf_data_converter/m0_axis_aclk] [get_bd_pins rf_data_converter/m2_axis_aclk] [get_bd_pins rf_data_converter/s0_axis_aclk] [get_bd_pins rf_data_converter/s1_axis_aclk] [get_bd_pins rf_reset_controller_0/RfClk] [get_bd_pins rf_reset_controller_1/RfClk]
|
||||
connect_bd_net -net data_clock_mmcm_rfdc_clk_2x1 [get_bd_pins rfdc_clk_2x] [get_bd_pins axi_interconnect_rf/M02_ACLK] [get_bd_pins axi_interconnect_rf/M11_ACLK] [get_bd_pins data_clock_mmcm/rfdc_clk_2x] [get_bd_pins reg_invert_iq_radio0/s_axi_aclk] [get_bd_pins reg_invert_iq_radio1/s_axi_aclk] [get_bd_pins rf_reset_controller_0/RfClk2x] [get_bd_pins rf_reset_controller_1/RfClk2x]
|
||||
connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_pins pll_ref_clk_out] [get_bd_pins capture_sysref/pll_ref_clk] [get_bd_pins data_clock_mmcm/pll_ref_clk_out] [get_bd_pins rf_reset_controller_0/PllRefClk] [get_bd_pins rf_reset_controller_1/PllRefClk]
|
||||
connect_bd_net -net enable_gated_clocks_clk40_1 [get_bd_pins enable_gated_clocks_clk40] [get_bd_pins clock_gates_0/rSafeToEnableGatedClks]
|
||||
connect_bd_net -net enable_rclk_0_1 [get_bd_pins enable_sysref_rclk] [get_bd_pins capture_sysref/enable_rclk]
|
||||
@@ -3628,13 +3557,13 @@ proc create_root_design { parentCell } {
|
||||
set rf_axi_status_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_axi_status_clk40 ]
|
||||
set rf_dsp_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_dsp_info_clk40 ]
|
||||
set rf_rfdc_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_rfdc_info_clk40 ]
|
||||
set rfdc_clk [ create_bd_port -dir O -from 0 -to 0 -type clk rfdc_clk ]
|
||||
set rfdc_clk [ create_bd_port -dir O -type clk rfdc_clk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {adc_tile224_ch0_dout_i:adc_tile224_ch1_dout_i:adc_tile224_ch1_dout_q:adc_tile224_ch0_dout_q:dac_tile228_ch0_din:dac_tile228_ch1_din:dac_tile229_ch0_din:dac_tile229_ch1_din:adc_tile226_ch0_dout_i:adc_tile226_ch0_dout_q:adc_tile226_ch1_dout_i:adc_tile226_ch1_dout_q} \
|
||||
CONFIG.ASSOCIATED_RESET {adc_tile224_axis_resetn_rclk:adc_tile226_axis_resetn_rclk:dac_tile228_axis_resetn_rclk:dac_tile229_axis_resetn_rclk} \
|
||||
CONFIG.FREQ_HZ {184320000} \
|
||||
] $rfdc_clk
|
||||
set rfdc_clk_2x [ create_bd_port -dir O -from 0 -to 0 -type clk rfdc_clk_2x ]
|
||||
set rfdc_clk_2x [ create_bd_port -dir O -type clk rfdc_clk_2x ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {368640000} \
|
||||
] $rfdc_clk_2x
|
||||
|
||||
@@ -1,16 +1,16 @@
|
||||
set script_loc [file normalize [info script]]
|
||||
set script_dir [file dirname $script_loc]
|
||||
|
||||
read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
|
||||
read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
|
||||
read_verilog -library work $script_dir/../../../regmap/x440/rfdc_mapping_regmap_utils.vh
|
||||
read_verilog -library work $script_dir/../../../rf/x440/x440_rfdc_tx_control_remap.v
|
||||
read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
|
||||
read_vhdl -library work $script_dir/../../../regmap/x440/PkgRFDC_REGS_REGMAP.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/x440/x440_rf_reset_controller.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/x440/x440_clock_gates.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer.v
|
||||
read_verilog -library work $script_dir/../../../../../lib/control/synchronizer_impl.v
|
||||
read_vhdl -library work $script_dir/../../../regmap/x440/PkgRFDC_REGS_REGMAP.vhd
|
||||
read_verilog -library work $script_dir/../../../regmap/x440/rfdc_mapping_regmap_utils.vh
|
||||
read_vhdl -library work $script_dir/../../../rf/common/axis_mux.vhd
|
||||
read_verilog -library work $script_dir/../../../rf/common/capture_sysref.v
|
||||
read_vhdl -library work $script_dir/../../../rf/common/gpio_to_axis_mux.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/rf_nco_reset.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/common/rf_reset.vhd
|
||||
read_verilog -library work $script_dir/../../../rf/common/sync_wrapper.v
|
||||
read_vhdl -library work $script_dir/../../../rf/x440/x440_clock_gates.vhd
|
||||
read_vhdl -library work $script_dir/../../../rf/x440/x440_rf_reset_controller.vhd
|
||||
read_verilog -library work $script_dir/../../../rf/x440/x440_rfdc_tx_control_remap.v
|
||||
|
||||
@@ -154,7 +154,6 @@ xilinx.com:ip:xlslice:1.0\
|
||||
xilinx.com:ip:axi_protocol_converter:2.1\
|
||||
xilinx.com:ip:axi_dma:7.1\
|
||||
xilinx.com:ip:smartconnect:1.0\
|
||||
xilinx.com:ip:util_ds_buf:2.2\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
@@ -215,98 +214,6 @@ if { $bCheckIPsPassed != 1 } {
|
||||
##################################################################
|
||||
|
||||
|
||||
# Hierarchical cell: rf_clock_buffers
|
||||
proc create_hier_cell_rf_clock_buffers { parentCell nameHier } {
|
||||
|
||||
variable script_folder
|
||||
|
||||
if { $parentCell eq "" || $nameHier eq "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_rf_clock_buffers() - Empty argument(s)!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
# Create cell and set as current instance
|
||||
set hier_obj [create_bd_cell -type hier $nameHier]
|
||||
current_bd_instance $hier_obj
|
||||
|
||||
# Create interface pins
|
||||
|
||||
# Create pins
|
||||
create_bd_pin -dir I -from 0 -to 0 radio0_rfdc_clk_2x_ce
|
||||
create_bd_pin -dir I -from 0 -to 0 -type clk radio0_rfdc_clk_2x_pll
|
||||
create_bd_pin -dir I -from 0 -to 0 radio0_rfdc_clk_ce
|
||||
create_bd_pin -dir I -from 0 -to 0 -type clk radio0_rfdc_clk_pll
|
||||
create_bd_pin -dir I -from 0 -to 0 radio1_rfdc_clk_2x_ce
|
||||
create_bd_pin -dir I -from 0 -to 0 -type clk radio1_rfdc_clk_2x_pll
|
||||
create_bd_pin -dir I -from 0 -to 0 radio1_rfdc_clk_ce
|
||||
create_bd_pin -dir I -from 0 -to 0 -type clk radio1_rfdc_clk_pll
|
||||
create_bd_pin -dir O -from 0 -to 0 rf0_clk_1x
|
||||
create_bd_pin -dir O -from 0 -to 0 rf0_clk_2x
|
||||
create_bd_pin -dir O -from 0 -to 0 rf1_clk_1x
|
||||
create_bd_pin -dir O -from 0 -to 0 rf1_clk_2x
|
||||
|
||||
# Create instance: rf0_clk_1x_buf, and set properties
|
||||
set rf0_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rf0_clk_1x_buf ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_BUF_TYPE {BUFGCE} \
|
||||
] $rf0_clk_1x_buf
|
||||
|
||||
# Create instance: rf0_clk_2x_buf, and set properties
|
||||
set rf0_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rf0_clk_2x_buf ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_BUF_TYPE {BUFGCE} \
|
||||
] $rf0_clk_2x_buf
|
||||
|
||||
# Create instance: rf1_clk_1x_buf, and set properties
|
||||
set rf1_clk_1x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rf1_clk_1x_buf ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_BUF_TYPE {BUFGCE} \
|
||||
] $rf1_clk_1x_buf
|
||||
|
||||
# Create instance: rf1_clk_2x_buf, and set properties
|
||||
set rf1_clk_2x_buf [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 rf1_clk_2x_buf ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.C_BUF_TYPE {BUFGCE} \
|
||||
] $rf1_clk_2x_buf
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net BUFGCE_I2_1 [get_bd_pins radio0_rfdc_clk_2x_pll] [get_bd_pins rf0_clk_2x_buf/BUFGCE_I]
|
||||
connect_bd_net -net radio0_rfdc_clk_2x_ce1_1 [get_bd_pins radio1_rfdc_clk_2x_ce] [get_bd_pins rf1_clk_2x_buf/BUFGCE_CE]
|
||||
connect_bd_net -net radio0_rfdc_clk_pll1_1 [get_bd_pins radio1_rfdc_clk_pll] [get_bd_pins rf1_clk_1x_buf/BUFGCE_I]
|
||||
connect_bd_net -net radio0_rfdc_clk_pll2_1 [get_bd_pins radio1_rfdc_clk_2x_pll] [get_bd_pins rf1_clk_2x_buf/BUFGCE_I]
|
||||
connect_bd_net -net radio1_rfdc_clk_ce [get_bd_pins radio1_rfdc_clk_ce] [get_bd_pins rf1_clk_1x_buf/BUFGCE_CE]
|
||||
connect_bd_net -net rf1_clk_1x_buf_BUFGCE_O [get_bd_pins rf1_clk_1x] [get_bd_pins rf1_clk_1x_buf/BUFGCE_O]
|
||||
connect_bd_net -net rf1_clk_2x_buf_BUFGCE_O [get_bd_pins rf1_clk_2x] [get_bd_pins rf1_clk_2x_buf/BUFGCE_O]
|
||||
connect_bd_net -net rfdc_clk_1 [get_bd_pins radio0_rfdc_clk_pll] [get_bd_pins rf0_clk_1x_buf/BUFGCE_I]
|
||||
connect_bd_net -net rfdc_clk_1x_buf_BUFGCE_O [get_bd_pins rf0_clk_1x] [get_bd_pins rf0_clk_1x_buf/BUFGCE_O]
|
||||
connect_bd_net -net rfdc_clk_2x_buf_BUFGCE_O [get_bd_pins rf0_clk_2x] [get_bd_pins rf0_clk_2x_buf/BUFGCE_O]
|
||||
connect_bd_net -net rfdc_clk_2x_ce_1 [get_bd_pins radio0_rfdc_clk_2x_ce] [get_bd_pins rf0_clk_2x_buf/BUFGCE_CE]
|
||||
connect_bd_net -net rfdc_clk_ce_1 [get_bd_pins radio0_rfdc_clk_ce] [get_bd_pins rf0_clk_1x_buf/BUFGCE_CE]
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
}
|
||||
|
||||
# Hierarchical cell: calibration_muxes
|
||||
proc create_hier_cell_calibration_muxes { parentCell nameHier } {
|
||||
|
||||
@@ -896,12 +803,12 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
create_bd_pin -dir O -type clk pll_ref_clk_out
|
||||
create_bd_pin -dir O -from 3 -to 0 radio0_invert_adc_iq_r0clk
|
||||
create_bd_pin -dir O -from 3 -to 0 radio0_invert_dac_iq_r0clk
|
||||
create_bd_pin -dir O -from 0 -to 0 radio0_rfdc_clk
|
||||
create_bd_pin -dir O -from 0 -to 0 radio0_rfdc_clk_2x
|
||||
create_bd_pin -dir O radio0_rfdc_clk
|
||||
create_bd_pin -dir O radio0_rfdc_clk_2x
|
||||
create_bd_pin -dir O -from 3 -to 0 radio1_invert_adc_iq_r1clk
|
||||
create_bd_pin -dir O -from 3 -to 0 radio1_invert_dac_iq_r1clk
|
||||
create_bd_pin -dir O -from 0 -to 0 radio1_rfdc_clk_1x
|
||||
create_bd_pin -dir O -from 0 -to 0 radio1_rfdc_clk_2x
|
||||
create_bd_pin -dir O radio1_rfdc_clk_1x
|
||||
create_bd_pin -dir O radio1_rfdc_clk_2x
|
||||
create_bd_pin -dir I -from 31 -to 0 rf_axi_status_sclk
|
||||
create_bd_pin -dir I -from 31 -to 0 rf_dsp_info_sclk
|
||||
create_bd_pin -dir I -from 31 -to 0 rf_rfdc_info_sclk
|
||||
@@ -945,7 +852,7 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
] [get_bd_pins /rfdc/capture_sysref/pll_ref_clk]
|
||||
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
CONFIG.PHASE {0} \
|
||||
CONFIG.CLK_DOMAIN {x440_ps_rfdc_bd_pll_ref_clk_in} \
|
||||
] [get_bd_pins /rfdc/capture_sysref/rfdc_clk]
|
||||
@@ -969,39 +876,39 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
set_property -dict [ list \
|
||||
CONFIG.AXI_DRP {true} \
|
||||
CONFIG.CLKIN1_JITTER_PS {156.25} \
|
||||
CONFIG.CLKOUT1_DRIVES {Buffer} \
|
||||
CONFIG.CLKOUT1_JITTER {130.541} \
|
||||
CONFIG.CLKOUT1_PHASE_ERROR {128.385} \
|
||||
CONFIG.CLKOUT1_DRIVES {BUFG} \
|
||||
CONFIG.CLKOUT1_JITTER {157.622} \
|
||||
CONFIG.CLKOUT1_PHASE_ERROR {114.796} \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {64.00} \
|
||||
CONFIG.CLKOUT2_DRIVES {Buffer} \
|
||||
CONFIG.CLKOUT2_JITTER {116.118} \
|
||||
CONFIG.CLKOUT2_PHASE_ERROR {128.385} \
|
||||
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {128.00} \
|
||||
CONFIG.CLKOUT2_DRIVES {BUFG} \
|
||||
CONFIG.CLKOUT2_JITTER {120.323} \
|
||||
CONFIG.CLKOUT2_PHASE_ERROR {114.796} \
|
||||
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {256.00} \
|
||||
CONFIG.CLKOUT2_USED {true} \
|
||||
CONFIG.CLKOUT3_DRIVES {Buffer} \
|
||||
CONFIG.CLKOUT3_JITTER {130.541} \
|
||||
CONFIG.CLKOUT3_PHASE_ERROR {128.385} \
|
||||
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {64.00} \
|
||||
CONFIG.CLKOUT3_DRIVES {BUFGCE} \
|
||||
CONFIG.CLKOUT3_JITTER {120.323} \
|
||||
CONFIG.CLKOUT3_PHASE_ERROR {114.796} \
|
||||
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {256.00} \
|
||||
CONFIG.CLKOUT3_USED {true} \
|
||||
CONFIG.CLKOUT4_DRIVES {Buffer} \
|
||||
CONFIG.CLKOUT4_JITTER {103.479} \
|
||||
CONFIG.CLKOUT4_PHASE_ERROR {128.385} \
|
||||
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {256.00} \
|
||||
CONFIG.CLKOUT4_DRIVES {BUFG} \
|
||||
CONFIG.CLKOUT4_JITTER {106.992} \
|
||||
CONFIG.CLKOUT4_PHASE_ERROR {114.796} \
|
||||
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {512.00} \
|
||||
CONFIG.CLKOUT4_USED {true} \
|
||||
CONFIG.CLKOUT5_DRIVES {Buffer} \
|
||||
CONFIG.CLKOUT5_JITTER {116.118} \
|
||||
CONFIG.CLKOUT5_PHASE_ERROR {128.385} \
|
||||
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {128.00} \
|
||||
CONFIG.CLKOUT5_DRIVES {BUFGCE} \
|
||||
CONFIG.CLKOUT5_JITTER {106.992} \
|
||||
CONFIG.CLKOUT5_PHASE_ERROR {114.796} \
|
||||
CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {512.00} \
|
||||
CONFIG.CLKOUT5_USED {true} \
|
||||
CONFIG.CLKOUT6_DRIVES {Buffer} \
|
||||
CONFIG.CLKOUT6_JITTER {130.541} \
|
||||
CONFIG.CLKOUT6_PHASE_ERROR {128.385} \
|
||||
CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {64.00} \
|
||||
CONFIG.CLKOUT6_DRIVES {BUFGCE} \
|
||||
CONFIG.CLKOUT6_JITTER {120.323} \
|
||||
CONFIG.CLKOUT6_PHASE_ERROR {114.796} \
|
||||
CONFIG.CLKOUT6_REQUESTED_OUT_FREQ {256.00} \
|
||||
CONFIG.CLKOUT6_USED {true} \
|
||||
CONFIG.CLKOUT7_DRIVES {Buffer} \
|
||||
CONFIG.CLKOUT7_JITTER {116.118} \
|
||||
CONFIG.CLKOUT7_PHASE_ERROR {128.385} \
|
||||
CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {128.00} \
|
||||
CONFIG.CLKOUT7_DRIVES {BUFGCE} \
|
||||
CONFIG.CLKOUT7_JITTER {106.992} \
|
||||
CONFIG.CLKOUT7_PHASE_ERROR {114.796} \
|
||||
CONFIG.CLKOUT7_REQUESTED_OUT_FREQ {512.00} \
|
||||
CONFIG.CLKOUT7_USED {true} \
|
||||
CONFIG.CLK_OUT1_PORT {pll_ref_clk_out} \
|
||||
CONFIG.CLK_OUT2_PORT {data_clk} \
|
||||
@@ -1012,16 +919,16 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
CONFIG.CLK_OUT7_PORT {r1_rfdc_clk_2x} \
|
||||
CONFIG.ENABLE_CLOCK_MONITOR {false} \
|
||||
CONFIG.FEEDBACK_SOURCE {FDBK_AUTO} \
|
||||
CONFIG.MMCM_CLKFBOUT_MULT_F {20.000} \
|
||||
CONFIG.MMCM_CLKFBOUT_MULT_F {16.000} \
|
||||
CONFIG.MMCM_CLKIN1_PERIOD {15.625} \
|
||||
CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
|
||||
CONFIG.MMCM_CLKOUT0_DIVIDE_F {20.000} \
|
||||
CONFIG.MMCM_CLKOUT1_DIVIDE {10} \
|
||||
CONFIG.MMCM_CLKOUT2_DIVIDE {20} \
|
||||
CONFIG.MMCM_CLKOUT3_DIVIDE {5} \
|
||||
CONFIG.MMCM_CLKOUT4_DIVIDE {10} \
|
||||
CONFIG.MMCM_CLKOUT5_DIVIDE {20} \
|
||||
CONFIG.MMCM_CLKOUT6_DIVIDE {10} \
|
||||
CONFIG.MMCM_CLKOUT0_DIVIDE_F {16.000} \
|
||||
CONFIG.MMCM_CLKOUT1_DIVIDE {4} \
|
||||
CONFIG.MMCM_CLKOUT2_DIVIDE {4} \
|
||||
CONFIG.MMCM_CLKOUT3_DIVIDE {2} \
|
||||
CONFIG.MMCM_CLKOUT4_DIVIDE {2} \
|
||||
CONFIG.MMCM_CLKOUT5_DIVIDE {4} \
|
||||
CONFIG.MMCM_CLKOUT6_DIVIDE {2} \
|
||||
CONFIG.MMCM_DIVCLK_DIVIDE {1} \
|
||||
CONFIG.NUM_OUT_CLKS {7} \
|
||||
CONFIG.PHASE_DUTY_CONFIG {false} \
|
||||
@@ -1109,9 +1016,6 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
CONFIG.C_IS_DUAL {1} \
|
||||
] $reg_rfdc_tile_mapping
|
||||
|
||||
# Create instance: rf_clock_buffers
|
||||
create_hier_cell_rf_clock_buffers $hier_obj rf_clock_buffers
|
||||
|
||||
# Create instance: rf_data_converter, and set properties
|
||||
set rf_data_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:usp_rf_data_converter:2.5 rf_data_converter ]
|
||||
set_property -dict [ list \
|
||||
@@ -1588,36 +1492,32 @@ proc create_hier_cell_rfdc { parentCell nameHier } {
|
||||
connect_bd_net -net capture_sysref_0_sysref_out_rclk [get_bd_pins sysref_out_r0clk] [get_bd_pins capture_sysref/sysref_out_rclk] [get_bd_pins rf_data_converter/user_sysref_adc] [get_bd_pins rf_data_converter/user_sysref_dac] [get_bd_pins rf_nco_reset_0/dSysref]
|
||||
connect_bd_net -net capture_sysref_sysref_out_pclk [get_bd_pins sysref_out_pclk] [get_bd_pins capture_sysref/sysref_out_pclk]
|
||||
connect_bd_net -net clk_in1_0_1 [get_bd_pins pll_ref_clk_in] [get_bd_pins data_clock_mmcm/clk_in1]
|
||||
connect_bd_net -net clock_gates_0_aEnableRf1Bufg2x [get_bd_pins clock_gates_0/aEnableRf1Bufg2x] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_2x_ce]
|
||||
connect_bd_net -net clock_gates_0_aEnableRf1Bufg2x [get_bd_pins clock_gates_0/aEnableRf1Bufg2x] [get_bd_pins data_clock_mmcm/r1_rfdc_clk_2x_ce]
|
||||
connect_bd_net -net clock_gates_0_cSoftwareStatus [get_bd_pins clock_gates_0/rSoftwareStatus] [get_bd_pins reg_clock_gate_control/gpio2_io_i]
|
||||
connect_bd_net -net clock_gates_0_rGatedBaseClksValid [get_bd_pins gated_base_clks_valid_clk40] [get_bd_pins clock_gates_0/rGatedBaseClksValid]
|
||||
connect_bd_net -net clock_gates_0_rPllLocked [get_bd_pins data_clock_locked] [get_bd_pins clock_gates_0/rPllLocked]
|
||||
connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRf0Bufg2x] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_2x_ce]
|
||||
connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRf0Bufg1x] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_ce]
|
||||
connect_bd_net -net clock_gates_0_rf2EnableBufg [get_bd_pins clock_gates_0/aEnableRf0Bufg2x] [get_bd_pins data_clock_mmcm/r0_rfdc_clk_2x_ce]
|
||||
connect_bd_net -net clock_gates_0_rfEnableBufg [get_bd_pins clock_gates_0/aEnableRf0Bufg1x] [get_bd_pins data_clock_mmcm/r0_rfdc_clk_ce]
|
||||
connect_bd_net -net dac_reset_pulse_r0clk_1 [get_bd_pins dac_reset_pulse_r0clk] [get_bd_pins rf_reset_controller_0/rDacResetPulse]
|
||||
connect_bd_net -net dac_reset_pulse_r1clk_1 [get_bd_pins dac_reset_pulse_r1clk] [get_bd_pins rf_reset_controller_1/rDacResetPulse]
|
||||
connect_bd_net -net data_clock_mmcm_data_clk [get_bd_pins data_clk] [get_bd_pins data_clock_mmcm/data_clk]
|
||||
connect_bd_net -net data_clock_mmcm_data_clk_2x [get_bd_pins data_clk_2x] [get_bd_pins data_clock_mmcm/data_clk_2x]
|
||||
connect_bd_net -net data_clock_mmcm_locked [get_bd_pins clock_gates_0/aPllLocked] [get_bd_pins data_clock_mmcm/locked]
|
||||
connect_bd_net -net data_clock_mmcm_r0_rfdc_clk [get_bd_pins data_clock_mmcm/r0_rfdc_clk] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_pll]
|
||||
connect_bd_net -net data_clock_mmcm_r0_rfdc_clk_2x [get_bd_pins data_clock_mmcm/r0_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/radio0_rfdc_clk_2x_pll]
|
||||
connect_bd_net -net data_clock_mmcm_r1_rfdc_clk [get_bd_pins data_clock_mmcm/r1_rfdc_clk] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_pll]
|
||||
connect_bd_net -net data_clock_mmcm_r1_rfdc_clk_2x [get_bd_pins data_clock_mmcm/r1_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_2x_pll]
|
||||
connect_bd_net -net data_clock_mmcm_rfdc_clk [get_bd_pins radio0_rfdc_clk] [get_bd_pins axi_interconnect_rf/M02_ACLK] [get_bd_pins calibration_muxes/s_axi_aclk_0] [get_bd_pins calibration_muxes/s_axi_aclk_1] [get_bd_pins capture_sysref/rfdc_clk] [get_bd_pins reg_invert_iq_radio0/s_axi_aclk] [get_bd_pins rf_clock_buffers/rf0_clk_1x] [get_bd_pins rf_data_converter/m0_axis_aclk] [get_bd_pins rf_data_converter/m1_axis_aclk] [get_bd_pins rf_data_converter/s0_axis_aclk] [get_bd_pins rf_nco_reset_0/DataClk] [get_bd_pins rf_reset_controller_0/RfClk]
|
||||
connect_bd_net -net data_clock_mmcm_rfdc_clk_2x [get_bd_pins radio0_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/rf0_clk_2x] [get_bd_pins rf_reset_controller_0/RfClk2x]
|
||||
connect_bd_net -net data_clock_mmcm_r0_rfdc_clk [get_bd_pins radio0_rfdc_clk] [get_bd_pins axi_interconnect_rf/M02_ACLK] [get_bd_pins calibration_muxes/s_axi_aclk_0] [get_bd_pins calibration_muxes/s_axi_aclk_1] [get_bd_pins capture_sysref/rfdc_clk] [get_bd_pins data_clock_mmcm/r0_rfdc_clk] [get_bd_pins reg_invert_iq_radio0/s_axi_aclk] [get_bd_pins rf_data_converter/m0_axis_aclk] [get_bd_pins rf_data_converter/m1_axis_aclk] [get_bd_pins rf_data_converter/s0_axis_aclk] [get_bd_pins rf_nco_reset_0/DataClk] [get_bd_pins rf_reset_controller_0/RfClk]
|
||||
connect_bd_net -net data_clock_mmcm_r0_rfdc_clk_2x [get_bd_pins radio0_rfdc_clk_2x] [get_bd_pins data_clock_mmcm/r0_rfdc_clk_2x] [get_bd_pins rf_reset_controller_0/RfClk2x]
|
||||
connect_bd_net -net data_clock_mmcm_r1_rfdc_clk [get_bd_pins radio1_rfdc_clk_1x] [get_bd_pins axi_interconnect_rf/M11_ACLK] [get_bd_pins data_clock_mmcm/r1_rfdc_clk] [get_bd_pins reg_invert_iq_radio1/s_axi_aclk] [get_bd_pins rf_data_converter/m2_axis_aclk] [get_bd_pins rf_data_converter/m3_axis_aclk] [get_bd_pins rf_data_converter/s1_axis_aclk] [get_bd_pins rf_reset_controller_1/RfClk]
|
||||
connect_bd_net -net data_clock_mmcm_r1_rfdc_clk_2x [get_bd_pins radio1_rfdc_clk_2x] [get_bd_pins data_clock_mmcm/r1_rfdc_clk_2x] [get_bd_pins rf_reset_controller_1/RfClk2x]
|
||||
connect_bd_net -net data_clock_mmcm_tdc_ref_clk [get_bd_pins pll_ref_clk_out] [get_bd_pins capture_sysref/pll_ref_clk] [get_bd_pins data_clock_mmcm/pll_ref_clk_out] [get_bd_pins rf_reset_controller_0/PllRefClk] [get_bd_pins rf_reset_controller_1/PllRefClk]
|
||||
connect_bd_net -net enable_gated_clocks_clk40_1 [get_bd_pins enable_gated_clocks_clk40] [get_bd_pins clock_gates_0/rSafeToEnableGatedClks]
|
||||
connect_bd_net -net enable_rclk_0_1 [get_bd_pins enable_sysref_r0clk] [get_bd_pins capture_sysref/enable_rclk]
|
||||
connect_bd_net -net gpio2_io_i_0_2 [get_bd_pins rf_dsp_info_sclk] [get_bd_pins reg_rf_axi_status/gpio2_io_i]
|
||||
connect_bd_net -net gpio_io_i_0_1 [get_bd_pins rf_axi_status_sclk] [get_bd_pins reg_rf_axi_status/gpio_io_i]
|
||||
connect_bd_net -net radio1_rfdc_clk_ce_1 [get_bd_pins clock_gates_0/aEnableRf1Bufg1x] [get_bd_pins rf_clock_buffers/radio1_rfdc_clk_ce]
|
||||
connect_bd_net -net radio1_rfdc_clk_ce_1 [get_bd_pins clock_gates_0/aEnableRf1Bufg1x] [get_bd_pins data_clock_mmcm/r1_rfdc_clk_ce]
|
||||
connect_bd_net -net reg_invert_iq_radio1_gpio_io_o [get_bd_pins reg_invert_iq_radio1/gpio_io_o] [get_bd_pins slice_iqswap_11_8_radio1/Din] [get_bd_pins slice_iqswap_3_0_radio1/Din]
|
||||
connect_bd_net -net reg_reset_mmcm_gpio_io_o [get_bd_pins axi_interconnect_rf/M01_ARESETN] [get_bd_pins clock_gates_0/rPllReset_n] [get_bd_pins data_clock_mmcm/s_axi_aresetn] [get_bd_pins reg_reset_mmcm/gpio_io_o]
|
||||
connect_bd_net -net reg_rf_reset_control1_gpio_io_o [get_bd_pins clock_gates_0/rSoftwareControl] [get_bd_pins reg_clock_gate_control/gpio_io_o]
|
||||
connect_bd_net -net reg_rf_reset_control_radio1_gpio_io_o [get_bd_pins reg_rf_reset_control_radio1/gpio_io_o] [get_bd_pins rf_reset_controller_1/cSoftwareControl]
|
||||
connect_bd_net -net reg_rf_resets_gpio_io_o [get_bd_pins reg_rf_reset_control_radio0/gpio_io_o] [get_bd_pins rf_reset_controller_0/cSoftwareControl]
|
||||
connect_bd_net -net rf_clock_buffers_rf1_clk_1x [get_bd_pins radio1_rfdc_clk_1x] [get_bd_pins axi_interconnect_rf/M11_ACLK] [get_bd_pins reg_invert_iq_radio1/s_axi_aclk] [get_bd_pins rf_clock_buffers/rf1_clk_1x] [get_bd_pins rf_data_converter/m2_axis_aclk] [get_bd_pins rf_data_converter/m3_axis_aclk] [get_bd_pins rf_data_converter/s1_axis_aclk] [get_bd_pins rf_reset_controller_1/RfClk]
|
||||
connect_bd_net -net rf_clock_buffers_rf1_clk_2x [get_bd_pins radio1_rfdc_clk_2x] [get_bd_pins rf_clock_buffers/rf1_clk_2x] [get_bd_pins rf_reset_controller_1/RfClk2x]
|
||||
connect_bd_net -net rf_data_converter_adc0_01_over_threshold1 [get_bd_pins ThresholdRegister/In0] [get_bd_pins rf_data_converter/adc0_01_over_threshold1]
|
||||
connect_bd_net -net rf_data_converter_adc0_01_over_threshold2 [get_bd_pins ThresholdRegister/In1] [get_bd_pins rf_data_converter/adc0_01_over_threshold2]
|
||||
connect_bd_net -net rf_data_converter_adc0_23_over_threshold1 [get_bd_pins ThresholdRegister/In2] [get_bd_pins rf_data_converter/adc0_23_over_threshold1]
|
||||
@@ -3441,96 +3341,96 @@ proc create_root_design { parentCell } {
|
||||
|
||||
set adc_tile224_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_i ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile224_ch0_dout_i
|
||||
|
||||
set adc_tile224_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch0_dout_q ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile224_ch0_dout_q
|
||||
|
||||
set adc_tile224_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch0_vin ]
|
||||
|
||||
set adc_tile224_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_i ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile224_ch1_dout_i
|
||||
|
||||
set adc_tile224_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile224_ch1_dout_q ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile224_ch1_dout_q
|
||||
|
||||
set adc_tile224_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile224_ch1_vin ]
|
||||
|
||||
set adc_tile225_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch0_dout_i ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile225_ch0_dout_i
|
||||
|
||||
set adc_tile225_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch0_dout_q ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile225_ch0_dout_q
|
||||
|
||||
set adc_tile225_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile225_ch0_vin ]
|
||||
|
||||
set adc_tile225_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch1_dout_i ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile225_ch1_dout_i
|
||||
|
||||
set adc_tile225_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile225_ch1_dout_q ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile225_ch1_dout_q
|
||||
|
||||
set adc_tile225_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile225_ch1_vin ]
|
||||
|
||||
set adc_tile226_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_i ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile226_ch0_dout_i
|
||||
|
||||
set adc_tile226_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch0_dout_q ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile226_ch0_dout_q
|
||||
|
||||
set adc_tile226_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch0_vin ]
|
||||
|
||||
set adc_tile226_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_i ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile226_ch1_dout_i
|
||||
|
||||
set adc_tile226_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile226_ch1_dout_q ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile226_ch1_dout_q
|
||||
|
||||
set adc_tile226_ch1_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile226_ch1_vin ]
|
||||
|
||||
set adc_tile227_ch0_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch0_dout_i ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile227_ch0_dout_i
|
||||
|
||||
set adc_tile227_ch0_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch0_dout_q ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile227_ch0_dout_q
|
||||
|
||||
set adc_tile227_ch0_vin [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 adc_tile227_ch0_vin ]
|
||||
|
||||
set adc_tile227_ch1_dout_i [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch1_dout_i ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $adc_tile227_ch1_dout_i
|
||||
|
||||
set adc_tile227_ch1_dout_q [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 adc_tile227_ch1_dout_q ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
CONFIG.PHASE {0.0} \
|
||||
] $adc_tile227_ch1_dout_q
|
||||
|
||||
@@ -3542,7 +3442,7 @@ proc create_root_design { parentCell } {
|
||||
|
||||
set dac_tile228_ch0_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch0_din ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {0} \
|
||||
CONFIG.HAS_TREADY {1} \
|
||||
@@ -3558,7 +3458,7 @@ proc create_root_design { parentCell } {
|
||||
|
||||
set dac_tile228_ch1_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch1_din ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {0} \
|
||||
CONFIG.HAS_TREADY {1} \
|
||||
@@ -3574,7 +3474,7 @@ proc create_root_design { parentCell } {
|
||||
|
||||
set dac_tile228_ch2_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch2_din ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {0} \
|
||||
CONFIG.HAS_TREADY {1} \
|
||||
@@ -3591,7 +3491,7 @@ proc create_root_design { parentCell } {
|
||||
|
||||
set dac_tile228_ch3_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile228_ch3_din ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {0} \
|
||||
CONFIG.HAS_TREADY {1} \
|
||||
@@ -3608,7 +3508,7 @@ proc create_root_design { parentCell } {
|
||||
|
||||
set dac_tile229_ch0_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch0_din ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {0} \
|
||||
CONFIG.HAS_TREADY {1} \
|
||||
@@ -3624,7 +3524,7 @@ proc create_root_design { parentCell } {
|
||||
|
||||
set dac_tile229_ch1_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch1_din ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {0} \
|
||||
CONFIG.HAS_TREADY {1} \
|
||||
@@ -3640,7 +3540,7 @@ proc create_root_design { parentCell } {
|
||||
|
||||
set dac_tile229_ch2_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch2_din ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {0} \
|
||||
CONFIG.HAS_TREADY {1} \
|
||||
@@ -3657,7 +3557,7 @@ proc create_root_design { parentCell } {
|
||||
|
||||
set dac_tile229_ch3_din [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 dac_tile229_ch3_din ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
CONFIG.HAS_TKEEP {0} \
|
||||
CONFIG.HAS_TLAST {0} \
|
||||
CONFIG.HAS_TREADY {1} \
|
||||
@@ -3918,11 +3818,11 @@ proc create_root_design { parentCell } {
|
||||
set dac_reset_pulse_r1clk [ create_bd_port -dir I dac_reset_pulse_r1clk ]
|
||||
set data_clk [ create_bd_port -dir O -type clk data_clk ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {128000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $data_clk
|
||||
set data_clk_2x [ create_bd_port -dir O -type clk data_clk_2x ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
CONFIG.FREQ_HZ {512000000} \
|
||||
] $data_clk_2x
|
||||
set data_clock_locked [ create_bd_port -dir O data_clock_locked ]
|
||||
set enable_gated_clocks_clk40 [ create_bd_port -dir I enable_gated_clocks_clk40 ]
|
||||
@@ -3960,20 +3860,20 @@ proc create_root_design { parentCell } {
|
||||
] $pll_ref_clk_out
|
||||
set radio0_invert_adc_iq_r0clk [ create_bd_port -dir O -from 3 -to 0 radio0_invert_adc_iq_r0clk ]
|
||||
set radio0_invert_dac_iq_r0clk [ create_bd_port -dir O -from 3 -to 0 radio0_invert_dac_iq_r0clk ]
|
||||
set radio0_rfdc_clk_1x [ create_bd_port -dir O -from 0 -to 0 -type clk radio0_rfdc_clk_1x ]
|
||||
set radio0_rfdc_clk_1x [ create_bd_port -dir O -type clk radio0_rfdc_clk_1x ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.ASSOCIATED_BUSIF {adc_tile224_ch0_dout_i:adc_tile224_ch1_dout_i:adc_tile224_ch1_dout_q:adc_tile224_ch0_dout_q:dac_tile228_ch0_din:dac_tile228_ch1_din:dac_tile229_ch0_din:dac_tile229_ch1_din:adc_tile226_ch0_dout_i:adc_tile226_ch0_dout_q:adc_tile226_ch1_dout_i:adc_tile226_ch1_dout_q} \
|
||||
CONFIG.ASSOCIATED_RESET {adc_tile224_axis_resetn_rclk:adc_tile226_axis_resetn_rclk:dac_tile228_axis_resetn_rclk:dac_tile229_axis_resetn_rclk} \
|
||||
CONFIG.FREQ_HZ {64000000} \
|
||||
CONFIG.FREQ_HZ {256000000} \
|
||||
] $radio0_rfdc_clk_1x
|
||||
set radio0_rfdc_clk_2x [ create_bd_port -dir O -from 0 -to 0 -type clk radio0_rfdc_clk_2x ]
|
||||
set radio0_rfdc_clk_2x [ create_bd_port -dir O -type clk radio0_rfdc_clk_2x ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.FREQ_HZ {128000000} \
|
||||
CONFIG.FREQ_HZ {512000000} \
|
||||
] $radio0_rfdc_clk_2x
|
||||
set radio1_invert_adc_iq_r1clk [ create_bd_port -dir O -from 3 -to 0 radio1_invert_adc_iq_r1clk ]
|
||||
set radio1_invert_dac_iq_r1clk [ create_bd_port -dir O -from 3 -to 0 radio1_invert_dac_iq_r1clk ]
|
||||
set radio1_rfdc_clk_1x [ create_bd_port -dir O -from 0 -to 0 radio1_rfdc_clk_1x ]
|
||||
set radio1_rfdc_clk_2x [ create_bd_port -dir O -from 0 -to 0 radio1_rfdc_clk_2x ]
|
||||
set radio1_rfdc_clk_1x [ create_bd_port -dir O radio1_rfdc_clk_1x ]
|
||||
set radio1_rfdc_clk_2x [ create_bd_port -dir O radio1_rfdc_clk_2x ]
|
||||
set rf_axi_status_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_axi_status_clk40 ]
|
||||
set rf_dsp_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_dsp_info_clk40 ]
|
||||
set rf_rfdc_info_clk40 [ create_bd_port -dir I -from 31 -to 0 rf_rfdc_info_clk40 ]
|
||||
|
||||
Reference in New Issue
Block a user