fpga: x400: refactor RFDC block diagrams and timing constraints

Original-commit: a7bce74be154de9a68d6bdf2f9a6651b480b6dfa

top/x400/constraints/timing/x440_clocks_400.xdc

@@ -1,21 +1,25 @@
 #
-# Copyright 2023 Ettus Research, a National Instruments Brand
+# Copyright 2024 Ettus Research, a National Instruments Brand
 #
 # SPDX-License-Identifier: LGPL-3.0-or-later
 #
 # Description:
-#   Clock definition constraints for X440 400 type images
+#   Clock definition constraints for X440 400 MHz BW type images
 #
 
-# Data clocks: Generated by the MMCM, used for data paths between the RFDC output
-# and RFNoC. Maximum supported master clock rate is 500 Msps @8SPC => 62.5 MHz.
-# Theoretical maximum converter rate is 4.096 GSps, so really, 512 Msps @ 8SPC => 64 MHz.
-set rfdc_data_clk_period 15.625
+# Data clocks: Generated by the MMCM, used for data paths between the RFDC output and RFNoC. 
+# The RFDC block diagram is set up for the maximum required clock frequencies (rfdc_clk_1x @ 256 MHz), 
+# which are used in the 1600 MHz bitfile.
+# This is not required for the 400 MHz bitfile, hence we multiply the output clock divider values by 4
+# to allow Vivado to auto-derive the correct clock periods. 
 
-create_clock -name rfdc_r0_clk -add \
-             -period $rfdc_data_clk_period \
-             [get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT2]
-create_clock -name rfdc_r1_clk -add  \
-             -period $rfdc_data_clk_period \
-             [get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT5]
+set data_clock_mmcm [get_cells -hierarchical -filter { PRIMITIVE_TYPE == CLOCK.PLL.MMCME4_ADV && NAME =~  "*data_clock_mmcm*" }]
 
+set_property -dict [ list \   
+   CLKOUT1_DIVIDE {16} \
+   CLKOUT2_DIVIDE {16} \
+   CLKOUT3_DIVIDE {8} \
+   CLKOUT4_DIVIDE {8} \
+   CLKOUT5_DIVIDE {16} \
+   CLKOUT6_DIVIDE {8} \
+] $data_clock_mmcm