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fpga: x400: refactor RFDC block diagrams and timing constraints

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Original-commit: a7bce74be154de9a68d6bdf2f9a6651b480b6dfa
This commit is contained in:
Friedrich Wenisch
2025-02-13 07:51:05 -06:00
committed by Wade Fife
parent f480008cf9
commit 3ed06cc861
12 changed files with 215 additions and 393 deletions
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top/x400/constraints/timing/x440.xdc
+17 -24
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@@ -40,33 +40,26 @@ set_multicycle_path -end -hold 7 -from [get_pins db_gpio_gen[*].db_gpio_interfac
# x440_ps_rfdc_bd
###############################################################################
# This property tells Vivado that we require these clocks to be well aligned.
# We have synchronous clock domain crossings between these clocks that can have
# This property tells Vivado that we require the clocks generated by the RFDC MMCM to be well
# aligned. We have synchronous clock domain crossings between these clocks that can have
# large hold violations after placement due to uneven clock loading.
set_property CLOCK_DELAY_GROUP DataClkGroup [get_nets -hier -filter {\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/data_clk_2x ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/pll_ref_clk_out ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio0_rfdc_clk ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio0_rfdc_clk_2x ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio1_rfdc_clk ||\
NAME=~*/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/radio1_rfdc_clk_2x \
}]
# The constraint CLOCK_DELAY_GROUP has to be applied on the clock nets.
# These nets are connected to the outputs of the clock buffers, which are driven by the MMCM.
# Search the nets begining from the MMCM outputs to find the clock buffers outputs.
set rfdc_mmcm [get_cells -hierarchical -filter { PRIMITIVE_TYPE == CLOCK.PLL.MMCME4_ADV && NAME =~ *rfdc/data_clock_mmcm* } ]
set mmcm_clkout_pins [get_pins -of_objects $rfdc_mmcm -regexp -filter {NAME =~ ".*CLKOUT[0-6]"}]
set mmcm_clkout_nets [get_nets -of_objects $mmcm_clkout_pins]
set clkbuf_in_pins [get_pins -leaf -of_objects $mmcm_clkout_nets -filter {DIRECTION == IN}]
set clkbuf_cells [get_cells -of_objects $clkbuf_in_pins]
set clkbuf_out_pins [get_pins -of_objects $clkbuf_cells -filter {DIRECTION == OUT}]
set clkbuf_out_nets [get_nets -of_objects $clkbuf_out_pins]
set_property CLOCK_DELAY_GROUP DataClkGroup $clkbuf_out_nets
# We treat rfdc_clk buffers as asynchronous, with knowledge that
# code clocked in this domain will be reset after this clocked is enabled. This
# will make timing easier to meet on these clock domains.
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc0Bufg1x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf0_clk_1x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc0Bufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf0_clk_2x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc1Bufg1x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf1_clk_1x_buf/*BUFGCE*/CE}]
set_false_path -from [get_pins -hierarchical -filter {NAME =~ */rfdc/clock_gates_0/*rEnableRfdc1Bufg2x*/C}] \
-to [get_pins -hierarchical -filter {NAME =~ */rfdc/rf_clock_buffers/rf1_clk_2x_buf/*BUFGCE*/CE}]
set_false_path -from [get_cells -hierarchical -regexp -filter {NAME =~ .*/rfdc/clock_gates_0/.*rEnableRfdc\dBufg.*_reg}]
###############################################################################
@@ -117,8 +110,8 @@ set_input_delay -clock pll_ref_clk -min $sysref_min_input_delay [get_ports {SYSR
# The output delays are chosen to allow a large time window of valid data for
# the MB CPLD logic.
set spi_min_out_delay -1.500
set spi_max_out_delay 9.500
set spi_min_out_delay 0.000
set spi_max_out_delay 11.000
# Set output constraints for all ports.
set spi_out_ports [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS0_n PL_CPLD_CS1_n}]