miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fpga: x400: refactor RFDC block diagrams and timing constraints

Browse Source 
Original-commit: a7bce74be154de9a68d6bdf2f9a6651b480b6dfa
This commit is contained in:
Friedrich Wenisch
2025-02-13 07:51:05 -06:00
committed by Wade Fife
parent f480008cf9
commit 3ed06cc861
12 changed files with 215 additions and 393 deletions
Download Patch File Download Diff File Expand all files Collapse all files
top/x400/Makefile.x4xx.inc
+2 -2
View File
@@ -110,9 +110,9 @@ ifneq (,$(findstring RF_BW=400,$(RFNOC_IMAGE_CORE_DEFS)))
MB_XDC += \
constraints/timing/x440_clocks_400.xdc
endif
ifneq (,$(findstring RF_BW=1600,$(RFNOC_IMAGE_CORE_DEFS)))
ifneq (,$(findstring RF_BW=200,$(RFNOC_IMAGE_CORE_DEFS)))
MB_XDC += \
constraints/timing/x440_clocks_1600.xdc
constraints/timing/x440_clocks_200.xdc
endif
MB_XDC += \
constraints/timing/x440_clocks.xdc