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b200: import original Kintex-7 clone port

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This commit is contained in:
miegl
2026-08-23 11:42:22 +02:00
parent 2f5b331f30
commit 3dc3446559
10 changed files with 114777 additions and 568 deletions
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top/b200/b200.v
+72 -25
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@@ -16,10 +16,10 @@ module b200 (
output cat_mosi,
output cat_sclk,
input fx3_ce,
output fx3_miso,
input fx3_mosi,
input fx3_sclk,
// input fx3_ce,
// output fx3_miso,
// input fx3_mosi,
// input fx3_sclk,
output pll_ce,
output pll_mosi,
@@ -58,8 +58,8 @@ module b200 (
input codec_main_clk_n,
// Debug Bus
output [31:0] debug,
output [1:0] debug_clk,
// output [31:0] debug,
// output [1:0] debug_clk,
// GPIF, FX3 Slave FIFO
output IFCLK, // pclk
@@ -79,10 +79,10 @@ module b200 (
input GPIF_CTL9, // global_reset
// GPS
input gps_lock,
output gps_rxd,
input gps_txd, // FPGA has pullup for unpopulated GPS
input gps_txd_nmea, // FPGA has pullup for unpopulated GPS
// input gps_lock,
// output gps_rxd,
// input gps_txd, // FPGA has pullup for unpopulated GPS
// input gps_txd_nmea, // FPGA has pullup for unpopulated GPS
// LEDS
output LED_RX1,
@@ -102,8 +102,8 @@ module b200 (
// Misc Hardware Control
output ref_sel,
input pll_lock,
input FPGA_CFG_CS, // Driven by FX3 gpio.
input AUX_PWR_ON, // Driven by FX3 gpio.
// input FPGA_CFG_CS, // Driven by FX3 gpio.
// input AUX_PWR_ON, // Driven by FX3 gpio.
// PPS
input PPS_IN_EXT,
@@ -124,9 +124,14 @@ module b200 (
output tx_enable2,
output rx_bandsel_a,
output rx_bandsel_b,
output rx_bandsel_c
output rx_bandsel_c,
output LED_STATUS,
output LED_CLK_G,
output LED_CLK_R
);
wire reset_global = GPIF_CTL9;
///////////////////////////////////////////////////////////////////////
@@ -136,9 +141,13 @@ module b200 (
wire locked;
b200_clk_gen gen_clks
(
.CLK_IN1_40_P(codec_main_clk_p), .CLK_IN1_40_N(codec_main_clk_n),
.CLK_OUT1_40_int(), .CLK_OUT2_100_gpif(gpif_clk), .CLK_OUT3_100_bus(),
.RESET(reset_global), .LOCKED(locked)
.clk_in1_p(codec_main_clk_p),
.clk_in1_n(codec_main_clk_n),
.CLK_OUT1_40_int(),
.CLK_OUT2_100_gpif(gpif_clk),
.CLK_OUT3_100_bus(),
.reset(reset_global),
.locked(locked)
);
// Bus Clock and GPIF Clock both same 100MHz clock.
@@ -165,8 +174,27 @@ module b200 (
wire [1:0] debug_clk_int;
//S6CLK2PIN S6CLK2PIN_dbg0 (.I(debug_clk_int[0]), .O(debug_clk[0]));
//S6CLK2PIN S6CLK2PIN_dbg1 (.I(debug_clk_int[1]), .O(debug_clk[1]));
assign debug_clk[1:0] = 2'b0;
S6CLK2PIN S6CLK2PIN_gpif (.I(gpif_clk), .O(IFCLK));
// assign debug_clk[1:0] = 2'b0;
// S6CLK2PIN S6CLK2PIN_gpif (.I(gpif_clk), .O(IFCLK));
///////////////////////////////////////////////////////////////////////
// drive output clocks
///////////////////////////////////////////////////////////////////////
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
)
ODDR_U
(
.Q(IFCLK), // 1-bit DDR output data
.C(gpif_clk), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D1(1'b1), // 1-bit data input (associated with C0)
.D2(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
///////////////////////////////////////////////////////////////////////
// Create sync reset signals
@@ -176,6 +204,19 @@ module b200 (
reset_sync bus_sync(.clk(bus_clk), .reset_in(!clocks_ready), .reset_out(bus_rst));
reset_sync radio_sync(.clk(radio_clk), .reset_in(!clocks_ready), .reset_out(radio_rst));
///////////////////////////////////////////////////////////////////////
// PPS Switch 1.GPS_PPS 2.EXT_PPS
///////////////////////////////////////////////////////////////////////
wire pps_ext_int;
pps_switch u_pps_switch (
.clk (gpif_clk),
.rst_n (!gpif_rst),
.gps_pps (PPS_IN_INT),
.ext_pps (PPS_IN_EXT),
.pps_out (pps_ext_int)
);
///////////////////////////////////////////////////////////////////////
// I/O
///////////////////////////////////////////////////////////////////////
@@ -185,11 +226,12 @@ module b200 (
b200_io b200_io_i0
(
.reset(reset),
.areset(reset_global),
.mimo(mimo),
// Baseband sample interface
.radio_clk(radio_clk),
// .radio_rst(radio_rst),
.rx_i0(rx_data0[31:20]),
.rx_q0(rx_data0[15:4]),
@@ -234,7 +276,7 @@ module b200 (
//The following signals are routed to the FX3 and were used by an obsolete
//bit-banging SPI engine.
// fx3_ce, fx3_sclk, fx3_mosi <Unused>
assign fx3_miso = 1'bZ; //Safe state because we cannot guarantee the
// assign fx3_miso = 1'bZ; //Safe state because we cannot guarantee the
//direction of this pin in the FX3
///////////////////////////////////////////////////////////////////////
@@ -294,10 +336,10 @@ module b200 (
.tx0(tx_data0), .tx1(tx_data1),
.fe0_gpio_out(radio0_gpio), .fe1_gpio_out(radio1_gpio),
.fp_gpio_in(fp_gpio_in), .fp_gpio_out(fp_gpio_out), .fp_gpio_ddr(fp_gpio_ddr),
.pps_int(PPS_IN_INT), .pps_ext(PPS_IN_EXT),
.rxd(gps_txd), .txd(gps_rxd),
.pps_int(pps_ext_int), .pps_ext(pps_ext_int),
// .rxd(gps_txd), .txd(gps_rxd),
.pps(LED_CLK_R),
.sclk(sclk), .sen(sen), .mosi(mosi), .miso(miso),
.rb_misc({31'b0, pll_lock}), .misc_outs(misc_outs),
@@ -360,6 +402,11 @@ module b200 (
///////////////////////////////////////////////////////////////////////
// Debug port
///////////////////////////////////////////////////////////////////////
assign debug = 0;
// assign debug = 0;
assign LED_STATUS = 'd1;
assign LED_CLK_G = 'd0;
endmodule // B200