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fpga: n3xx: Update synchronizer constraint

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Original-commit: ab4b0c6e0eacbc68df3f211ce27790b1cfbc002f
This commit is contained in:
Wade Fife
2021-09-13 13:20:37 -05:00
parent 63c358c082
commit 3c4c049943
1 changed files with 2 additions and 3 deletions
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top/n3xx/mb_timing.xdc
+2 -3
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@@ -106,6 +106,5 @@ set_max_delay -from $PORT_LIST 50.000
set_min_delay -from $PORT_LIST 0.000 set_min_delay -from $PORT_LIST 0.000
#****************************************************************************** #******************************************************************************
## Reset Sync False Path ## Synchronizer false paths
set_false_path -to [get_pins */synchronizer_false_path/stages[0].value_reg[0]/D] set_false_path -to [get_pins -hierarchical -filter {NAME =~ */synchronizer_false_path/stages[0].value_reg[0][*]/D}]
set_false_path -to [get_pins */synchronizer_false_path/stages[0].value_reg[0]/C]