fpga: rfnoc: Add Signal Generator RFNoC block

Original-commit: 1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4
2020-07-30 12:51:41 -05:00
parent 3e1e0be3bc
commit 2eb71626fb
12 changed files with 1925 additions and 18 deletions
@@ -40,7 +40,7 @@ module axi_setting_reg #(
  reg init;

  reg [WIDTH-1:0] o_tdata_int;
-  reg o_tlast_int, o_tvalid_int;
+  reg o_tlast_int, o_tvalid_int = VALID_AT_RESET;
  wire o_tready_int;

  always @(posedge clk) begin