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fpga: tools: remove temporary Xilinx directories for BD recreation

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During recreation of block diagrams any RTL modules will be kept in
hidden directories within the build directory. Updates of the RTL
sources might not be taken into account. Solution is to remove Xilinx's
hidden project directories before calling vivado.


Original-commit: f17a5113e228ac1bc5312193eb8f687e127184a3
This commit is contained in:
Max Köhler
2020-06-15 13:54:35 -05:00
committed by Wade Fife
parent d16d1e121c
commit 2a8ec5df90
1 changed files with 13 additions and 10 deletions
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tools/make/viv_ip_builder.mak
+6 -3
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@@ -29,7 +29,8 @@ BUILD_VIVADO_IP = \
export GEN_EXAMPLE=$(6); \ export GEN_EXAMPLE=$(6); \
export SYNTH_IP=$(SYNTH_IP); \ export SYNTH_IP=$(SYNTH_IP); \
echo "BUILDER: Staging IP in build directory..."; \ echo "BUILDER: Staging IP in build directory..."; \
rm -rf $(5)/$(1)/*; \ rm -rf $(5)/$(1); \
mkdir -p $(5)/$(1); \
$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \ $(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \
cp -rf $(4)/$(1)/* $(5)/$(1); \ cp -rf $(4)/$(1)/* $(5)/$(1); \
echo "BUILDER: Retargeting IP to part $(2)/$(3)..."; \ echo "BUILDER: Retargeting IP to part $(2)/$(3)..."; \
@@ -59,7 +60,8 @@ BUILD_VIVADO_BD = \
export BD_FILE=$(call RESOLVE_PATH,$(5)/$(1)/$(1).bd); \ export BD_FILE=$(call RESOLVE_PATH,$(5)/$(1)/$(1).bd); \
export PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \ export PART_NAME=`python $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(2)/$(3)`; \
echo "BUILDER: Staging BD in build directory..."; \ echo "BUILDER: Staging BD in build directory..."; \
rm $(5)/$(1)/* -rf; \ rm -rf $(5)/$(1); \
mkdir -p $(5)/$(1); \
$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \ $(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \
cp -rf $(4)/$(1)/* $(5)/$(1); \ cp -rf $(4)/$(1)/* $(5)/$(1); \
echo "BUILDER: Retargeting BD to part $(2)/$(3)..."; \ echo "BUILDER: Retargeting BD to part $(2)/$(3)..."; \
@@ -92,7 +94,8 @@ BUILD_VIVADO_BDTCL = \
export BD_IP_REPOS=$(call RESOLVE_PATH,$(6)); \ export BD_IP_REPOS=$(call RESOLVE_PATH,$(6)); \
export BD_HDL_SRCS=$(call RESOLVE_PATHS,$(7)); \ export BD_HDL_SRCS=$(call RESOLVE_PATHS,$(7)); \
echo "BUILDER: Staging BD Tcl in build directory..."; \ echo "BUILDER: Staging BD Tcl in build directory..."; \
rm $(5)/$(1)/* -rf; \ rm -rf $(5)/$(1); \
mkdir -p $(5)/$(1); \
$(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \ $(TOOLS_DIR)/scripts/shared-ip-loc-manage.sh --path=$(5)/$(1) reserve; \
cp -rf $(4)/$(1)/* $(5)/$(1); \ cp -rf $(4)/$(1)/* $(5)/$(1); \
echo "BUILDER: Retargeting BD to part $(2)/$(3)..."; \ echo "BUILDER: Retargeting BD to part $(2)/$(3)..."; \