fpga: lib: Add RegPort SystemVerilog interface

Original-commit: d628c136a0cca7dddc47711f86f52f2c9e2ca089
2022-08-29 17:01:45 -05:00
parent c09489b6b0
commit 2a74e8cd67
2 changed files with 97 additions and 0 deletions
@@ -63,4 +63,5 @@ axil_ctrlport_master.v\
 handshake.v\
 ctrlport_to_regport.v \
 glitch_free_mux.v \
+regport_if.sv \
 ))