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timing: bound asynchronous GPIF-radio crossings

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Replace broad GPIF/radio false paths with 10 ns datapath-only maximum delays between the 100 MHz GPIF clock and the generated SISO/MIMO radio clocks.

Preserve physical control of asynchronous CDC paths without overriding the more-specific XPM FIFO CDC constraints.
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miegl
2026-08-25 22:33:46 +02:00
parent e7b1ac41e0
commit 286cde0a8d
1 changed files with 21 additions and 0 deletions
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top/b200/b210.xdc
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@@ -210,6 +210,27 @@ set_clock_groups \
-group [get_clocks -include_generated_clocks {codec_data_clk_p_Gen}] \
-group [get_clocks -include_generated_clocks {rx_clk_mimo_bufr_Gen}]
# --------------------------------------------------------------------------
# GPIF <-> radio domains are asynchronous.
#
# Bound physical datapath delay without imposing an unrelated clock-phase
# relationship. More-specific XPM FIFO constraints remain in effect.
# --------------------------------------------------------------------------
set gpif_clk \
[get_clocks -of_objects \
[get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]]
set_max_delay 10.000 \
-datapath_only \
-from $gpif_clk \
-to [get_clocks {codec_data_clk_p_Gen rx_clk_mimo_bufr_Gen}]
set_max_delay 10.000 \
-datapath_only \
-from [get_clocks {codec_data_clk_p_Gen rx_clk_mimo_bufr_Gen}] \
-to $gpif_clk
set_false_path -from [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks codec_data_clk_p]
set_false_path -from [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins b200_io_i0/BUFR_inst/O]]
set_false_path -from [get_clocks codec_data_clk_p] -to [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]]