From 286cde0a8dbbacdc9146dbdc1a375cc15088934a Mon Sep 17 00:00:00 2001 From: Josef Miegl Date: Tue, 25 Aug 2026 22:33:46 +0200 Subject: [PATCH] timing: bound asynchronous GPIF-radio crossings Replace broad GPIF/radio false paths with 10 ns datapath-only maximum delays between the 100 MHz GPIF clock and the generated SISO/MIMO radio clocks. Preserve physical control of asynchronous CDC paths without overriding the more-specific XPM FIFO CDC constraints. --- top/b200/b210.xdc | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/top/b200/b210.xdc b/top/b200/b210.xdc index c078eee..d802891 100644 --- a/top/b200/b210.xdc +++ b/top/b200/b210.xdc @@ -210,6 +210,27 @@ set_clock_groups \ -group [get_clocks -include_generated_clocks {codec_data_clk_p_Gen}] \ -group [get_clocks -include_generated_clocks {rx_clk_mimo_bufr_Gen}] +# -------------------------------------------------------------------------- +# GPIF <-> radio domains are asynchronous. +# +# Bound physical datapath delay without imposing an unrelated clock-phase +# relationship. More-specific XPM FIFO constraints remain in effect. +# -------------------------------------------------------------------------- + +set gpif_clk \ + [get_clocks -of_objects \ + [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] + +set_max_delay 10.000 \ + -datapath_only \ + -from $gpif_clk \ + -to [get_clocks {codec_data_clk_p_Gen rx_clk_mimo_bufr_Gen}] + +set_max_delay 10.000 \ + -datapath_only \ + -from [get_clocks {codec_data_clk_p_Gen rx_clk_mimo_bufr_Gen}] \ + -to $gpif_clk + set_false_path -from [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks codec_data_clk_p] set_false_path -from [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins b200_io_i0/BUFR_inst/O]] set_false_path -from [get_clocks codec_data_clk_p] -to [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]]