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fpga: lib: Add read-only strategy for port B in 2-port RAM

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Original-commit: 69c549efab2fd536808f1ba032c278085217ba6d
This commit is contained in:
Javier Valenzuela
2022-06-28 16:33:05 -05:00
committed by Wade Fife
parent 287659ddeb
commit 27aae37722
2 changed files with 41 additions and 14 deletions
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lib/control/ram_2port.v
+1 -1
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@@ -54,7 +54,7 @@
module ram_2port #(
parameter DWIDTH = 32, // Width of the memory block
parameter AWIDTH = 9, // log2 of the depth of the memory block
parameter RW_MODE = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE}
parameter RW_MODE = "READ-FIRST", // Read-write mode {READ-FIRST, WRITE-FIRST, NO-CHANGE, B-READ-ONLY}
parameter RAM_TYPE = "AUTOMATIC", // Type of RAM to infer {AUTOMATIC, REG, LUTRAM, BRAM, URAM}
parameter OUT_REG = 0, // Instantiate an output register? (+1 cycle of read latency)
parameter INIT_FILE = "" // Optionally initialize memory with this file