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fpga: e31x: Update constraints to avoid timing issues

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Xilinx changed the way [all_registers -edge_triggered] is treated such
that set_max_delay constraints that use it can cause segmentation and
cause clocks to not be propagated to all endpoints. Changing to
[all_ffs] avoids this potential issue.


Original-commit: 55e422535292c29de00b80f15b0a49ca3fb94f26
This commit is contained in:
Wade Fife
2020-04-08 17:24:15 -05:00
parent ce701301d0
commit 2487e7bdf8
1 changed files with 6 additions and 6 deletions
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top/e31x/e31x_timing.xdc
+6 -6
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@@ -120,14 +120,14 @@ set_clock_groups -asynchronous \
# TCXO DAC SPI
# 12 MHz SPI clock rate
set_max_delay -datapath_only -from [all_registers -edge_triggered] -to [get_ports TCXO_DAC*] 40.000
set_min_delay -from [all_registers -edge_triggered] -to [get_ports TCXO_DAC*] 1.000
set_max_delay -datapath_only -from [all_ffs] -to [get_ports TCXO_DAC*] 40.000
set_min_delay -from [all_ffs] -to [get_ports TCXO_DAC*] 1.000
# User GPIO
set_max_delay -datapath_only -to [get_ports PL_GPIO*] -from [all_registers -edge_triggered] [expr 15.0]
set_min_delay -to [get_ports PL_GPIO*] -from [all_registers -edge_triggered] 5.0
set_max_delay -datapath_only -from [get_ports PL_GPIO*] -to [all_registers -edge_triggered] [expr 15.0]
set_min_delay -from [get_ports PL_GPIO*] -to [all_registers -edge_triggered] 5.0
set_max_delay -datapath_only -to [get_ports PL_GPIO*] -from [all_ffs] [expr 15.0]
set_min_delay -to [get_ports PL_GPIO*] -from [all_ffs] 5.0
set_max_delay -datapath_only -from [get_ports PL_GPIO*] -to [all_ffs] [expr 15.0]
set_min_delay -from [get_ports PL_GPIO*] -to [all_ffs] 5.0
# GPIO muxing
set_max_delay -from [get_pins e31x_core_inst/fp_gpio_src_reg_reg[*]/C] -to [get_clocks CAT_DATA_CLK] $cat_data_clk_period -datapath_only