fpga: lib: Add compat to Verilog transport adapter
Original-commit: e716c8c720718f69d39823b722f5e013df99a3d5
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@@ -76,21 +76,7 @@ module eth_interface #(
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// Registers
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// Registers
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//---------------------------------------------------------
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//---------------------------------------------------------
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// Allocate one full page for MAC
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`include "../xport_sv/eth_regs.vh"
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localparam [REG_AWIDTH-1:0] REG_MAC_LSB = BASE + 'h0000;
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localparam [REG_AWIDTH-1:0] REG_MAC_MSB = BASE + 'h0004;
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// Source IP address
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localparam [REG_AWIDTH-1:0] REG_IP = BASE + 'h1000;
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// Source UDP Port
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localparam [REG_AWIDTH-1:0] REG_UDP = BASE + 'h1004;
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// Registers for Internal/Bridge Network Mode in CPU
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_LSB = BASE + 'h1010;
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_MAC_MSB = BASE + 'h1014;
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_IP = BASE + 'h1018;
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_UDP = BASE + 'h101c;
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localparam [REG_AWIDTH-1:0] REG_BRIDGE_ENABLE = BASE + 'h1020;
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// MAC address for the dispatcher module.
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// MAC address for the dispatcher module.
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// This value is used to determine if the packet is meant
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// This value is used to determine if the packet is meant
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@@ -188,6 +174,17 @@ module eth_interface #(
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REG_BRIDGE_ENABLE:
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REG_BRIDGE_ENABLE:
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reg_rd_data <= {31'b0,bridge_en};
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reg_rd_data <= {31'b0,bridge_en};
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REG_XPORT_COMPAT:
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// Return compat of 0 to indicate this is the old transport adapter
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reg_rd_data <= 32'b0;
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REG_XPORT_INFO:
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// This TA has no advanced capabilities (e.g., raw UDP)
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reg_rd_data <= 32'b0;
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REG_XPORT_NODE_INST:
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reg_rd_data <= NODE_INST;
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default:
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default:
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reg_rd_resp <= 1'b0;
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reg_rd_resp <= 1'b0;
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endcase
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endcase
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@@ -201,7 +198,7 @@ module eth_interface #(
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// In AXI Stream, tkeep is the byte qualifier that indicates
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// In AXI Stream, tkeep is the byte qualifier that indicates
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// whether the content of the associated byte
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// whether the content of the associated byte
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// of TDATA is processed as part of the data stream.
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// of TDATA is processed as part of the data stream.
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// tuser as used in eth_switch is the numbier of valid bytes
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// tuser as used in eth_switch is the number of valid bytes
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eth_ipv4_chdr64_adapter #(
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eth_ipv4_chdr64_adapter #(
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.PROTOVER (PROTOVER),
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.PROTOVER (PROTOVER),
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