fpga: Update all RFNoC images
Original-commit: 002ff9698e09b94c396736613e493f79e9c56442
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
parent
b81ab96b12
commit
16c1235b30
@@ -1,5 +1,5 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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@@ -13,9 +13,9 @@
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// File generated on: 2021-05-03T08:51:09.232810
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// File generated on: 2022-03-29T22:54:31.355138
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// Source: n310_rfnoc_image_core.yml
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// Source SHA256: cc561a3de48fea9e224425413802738d125393f55f6dd46e196db8fdabe09284
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// Source SHA256: a15541b7fe850057f8190b2b9f645a4324be36615099db06c5cdcadfd8a634e1
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//
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`default_nettype none
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@@ -60,26 +60,26 @@ module rfnoc_image_core #(
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input wire [ 0:0] m_ctrlport_radio1_resp_ack,
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input wire [ 1:0] m_ctrlport_radio1_resp_status,
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input wire [ 31:0] m_ctrlport_radio1_resp_data,
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// time_keeper
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// time
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input wire [ 63:0] radio_time,
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// x300_radio0
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input wire [ 63:0] radio_rx_data_radio0,
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input wire [ 1:0] radio_rx_stb_radio0,
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output wire [ 1:0] radio_rx_running_radio0,
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output wire [ 63:0] radio_tx_data_radio0,
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input wire [ 1:0] radio_tx_stb_radio0,
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output wire [ 1:0] radio_tx_running_radio0,
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// x300_radio1
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input wire [ 63:0] radio_rx_data_radio1,
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input wire [ 1:0] radio_rx_stb_radio1,
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output wire [ 1:0] radio_rx_running_radio1,
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output wire [ 63:0] radio_tx_data_radio1,
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input wire [ 1:0] radio_tx_stb_radio1,
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output wire [ 1:0] radio_tx_running_radio1,
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// radio0
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input wire [ 255:0] radio_rx_data_radio0,
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input wire [ 7:0] radio_rx_stb_radio0,
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output wire [ 7:0] radio_rx_running_radio0,
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output wire [ 255:0] radio_tx_data_radio0,
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input wire [ 7:0] radio_tx_stb_radio0,
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output wire [ 7:0] radio_tx_running_radio0,
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// radio1
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input wire [ 255:0] radio_rx_data_radio1,
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input wire [ 7:0] radio_rx_stb_radio1,
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output wire [ 7:0] radio_rx_running_radio1,
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output wire [ 255:0] radio_tx_data_radio1,
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input wire [ 7:0] radio_tx_stb_radio1,
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output wire [ 7:0] radio_tx_running_radio1,
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// dram
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input wire [ 0:0] axi_rst,
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output wire [ 3:0] m_axi_awid,
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output wire [ 127:0] m_axi_awaddr,
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output wire [ 191:0] m_axi_awaddr,
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output wire [ 31:0] m_axi_awlen,
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output wire [ 11:0] m_axi_awsize,
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output wire [ 7:0] m_axi_awburst,
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@@ -91,8 +91,8 @@ module rfnoc_image_core #(
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output wire [ 3:0] m_axi_awuser,
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output wire [ 3:0] m_axi_awvalid,
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input wire [ 3:0] m_axi_awready,
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output wire [ 255:0] m_axi_wdata,
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output wire [ 31:0] m_axi_wstrb,
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output wire [2047:0] m_axi_wdata,
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output wire [ 255:0] m_axi_wstrb,
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output wire [ 3:0] m_axi_wlast,
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output wire [ 3:0] m_axi_wuser,
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output wire [ 3:0] m_axi_wvalid,
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@@ -103,7 +103,7 @@ module rfnoc_image_core #(
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input wire [ 3:0] m_axi_bvalid,
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output wire [ 3:0] m_axi_bready,
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output wire [ 3:0] m_axi_arid,
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output wire [ 127:0] m_axi_araddr,
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output wire [ 191:0] m_axi_araddr,
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output wire [ 31:0] m_axi_arlen,
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output wire [ 11:0] m_axi_arsize,
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output wire [ 7:0] m_axi_arburst,
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@@ -116,7 +116,7 @@ module rfnoc_image_core #(
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output wire [ 3:0] m_axi_arvalid,
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input wire [ 3:0] m_axi_arready,
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input wire [ 3:0] m_axi_rid,
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input wire [ 255:0] m_axi_rdata,
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input wire [2047:0] m_axi_rdata,
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input wire [ 7:0] m_axi_rresp,
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input wire [ 3:0] m_axi_rlast,
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input wire [ 3:0] m_axi_ruser,
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@@ -1026,7 +1026,7 @@ module rfnoc_image_core #(
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wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
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wire m_radio0_out_1_tready, m_radio0_out_0_tready;
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// ctrl_port
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// ctrlport
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wire [ 0:0] radio0_m_ctrlport_req_wr;
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wire [ 0:0] radio0_m_ctrlport_req_rd;
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wire [ 19:0] radio0_m_ctrlport_req_addr;
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@@ -1037,20 +1037,22 @@ module rfnoc_image_core #(
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wire [ 0:0] radio0_m_ctrlport_resp_ack;
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wire [ 1:0] radio0_m_ctrlport_resp_status;
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wire [ 31:0] radio0_m_ctrlport_resp_data;
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// time_keeper
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// time
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wire [ 63:0] radio0_radio_time;
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// x300_radio
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wire [ 63:0] radio0_radio_rx_data;
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wire [ 1:0] radio0_radio_rx_stb;
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wire [ 1:0] radio0_radio_rx_running;
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wire [ 63:0] radio0_radio_tx_data;
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wire [ 1:0] radio0_radio_tx_stb;
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wire [ 1:0] radio0_radio_tx_running;
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// radio
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wire [ 255:0] radio0_radio_rx_data;
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wire [ 7:0] radio0_radio_rx_stb;
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wire [ 7:0] radio0_radio_rx_running;
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wire [ 255:0] radio0_radio_tx_data;
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wire [ 7:0] radio0_radio_tx_stb;
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wire [ 7:0] radio0_radio_tx_running;
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rfnoc_block_radio #(
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.THIS_PORTID (4),
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.CHDR_W (CHDR_W),
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.NUM_PORTS (2),
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.NIPC (1),
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.ITEM_W (32),
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.MTU (MTU)
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) b_radio0_2 (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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@@ -1197,7 +1199,7 @@ module rfnoc_image_core #(
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wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
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wire m_radio1_out_1_tready, m_radio1_out_0_tready;
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// ctrl_port
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// ctrlport
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wire [ 0:0] radio1_m_ctrlport_req_wr;
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wire [ 0:0] radio1_m_ctrlport_req_rd;
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wire [ 19:0] radio1_m_ctrlport_req_addr;
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@@ -1208,20 +1210,22 @@ module rfnoc_image_core #(
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wire [ 0:0] radio1_m_ctrlport_resp_ack;
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wire [ 1:0] radio1_m_ctrlport_resp_status;
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wire [ 31:0] radio1_m_ctrlport_resp_data;
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// time_keeper
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// time
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wire [ 63:0] radio1_radio_time;
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// x300_radio
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wire [ 63:0] radio1_radio_rx_data;
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wire [ 1:0] radio1_radio_rx_stb;
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wire [ 1:0] radio1_radio_rx_running;
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wire [ 63:0] radio1_radio_tx_data;
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wire [ 1:0] radio1_radio_tx_stb;
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wire [ 1:0] radio1_radio_tx_running;
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// radio
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wire [ 255:0] radio1_radio_rx_data;
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wire [ 7:0] radio1_radio_rx_stb;
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wire [ 7:0] radio1_radio_rx_running;
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wire [ 255:0] radio1_radio_tx_data;
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wire [ 7:0] radio1_radio_tx_stb;
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wire [ 7:0] radio1_radio_tx_running;
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rfnoc_block_radio #(
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.THIS_PORTID (7),
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.CHDR_W (CHDR_W),
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.NUM_PORTS (2),
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.NIPC (1),
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.ITEM_W (32),
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.MTU (MTU)
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) b_radio1_5 (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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@@ -1281,7 +1285,7 @@ module rfnoc_image_core #(
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// axi_ram
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wire [ 0:0] replay0_axi_rst;
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wire [ 3:0] replay0_m_axi_awid;
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wire [ 127:0] replay0_m_axi_awaddr;
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wire [ 191:0] replay0_m_axi_awaddr;
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wire [ 31:0] replay0_m_axi_awlen;
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wire [ 11:0] replay0_m_axi_awsize;
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wire [ 7:0] replay0_m_axi_awburst;
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@@ -1293,8 +1297,8 @@ module rfnoc_image_core #(
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wire [ 3:0] replay0_m_axi_awuser;
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wire [ 3:0] replay0_m_axi_awvalid;
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wire [ 3:0] replay0_m_axi_awready;
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wire [ 255:0] replay0_m_axi_wdata;
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wire [ 31:0] replay0_m_axi_wstrb;
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wire [2047:0] replay0_m_axi_wdata;
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wire [ 255:0] replay0_m_axi_wstrb;
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wire [ 3:0] replay0_m_axi_wlast;
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wire [ 3:0] replay0_m_axi_wuser;
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wire [ 3:0] replay0_m_axi_wvalid;
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@@ -1305,7 +1309,7 @@ module rfnoc_image_core #(
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wire [ 3:0] replay0_m_axi_bvalid;
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wire [ 3:0] replay0_m_axi_bready;
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wire [ 3:0] replay0_m_axi_arid;
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wire [ 127:0] replay0_m_axi_araddr;
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wire [ 191:0] replay0_m_axi_araddr;
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wire [ 31:0] replay0_m_axi_arlen;
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wire [ 11:0] replay0_m_axi_arsize;
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wire [ 7:0] replay0_m_axi_arburst;
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@@ -1318,7 +1322,7 @@ module rfnoc_image_core #(
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wire [ 3:0] replay0_m_axi_arvalid;
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wire [ 3:0] replay0_m_axi_arready;
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wire [ 3:0] replay0_m_axi_rid;
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wire [ 255:0] replay0_m_axi_rdata;
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wire [2047:0] replay0_m_axi_rdata;
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wire [ 7:0] replay0_m_axi_rresp;
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wire [ 3:0] replay0_m_axi_rlast;
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wire [ 3:0] replay0_m_axi_ruser;
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@@ -1329,8 +1333,8 @@ module rfnoc_image_core #(
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.THIS_PORTID (8),
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.CHDR_W (CHDR_W),
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.NUM_PORTS (4),
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.MEM_ADDR_W (31),
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.MEM_DATA_W (64),
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.MEM_ADDR_W (31),
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.MTU (MTU)
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) b_replay0_6 (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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