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fpga: Update all RFNoC images

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Original-commit: 002ff9698e09b94c396736613e493f79e9c56442
This commit is contained in:
Wade Fife
2022-03-31 13:51:23 -07:00
committed by Aaron Rossetto
parent b81ab96b12
commit 16c1235b30
29 changed files with 508 additions and 468 deletions
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top/n3xx/n300_bist_image_core.v
+30 -26
View File
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-28T12:13:45.033343
// File generated on: 2022-03-29T22:54:29.701839
// Source: n300_bist_image_core.yml
// Source SHA256: 2e3de3488c19ed292d6d48c0591d1a39b04772f29b4f47a445fc4f8ab6475613
// Source SHA256: 6c4216a9a0a6064008b2aa7fc1c4c0d22820570c7c1275bab8fefaacd952f6b7
//
`default_nettype none
@@ -49,15 +49,15 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// time_keeper
// time
input wire [ 63:0] radio_time,
// x300_radio0
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// radio0
input wire [ 255:0] radio_rx_data_radio0,
input wire [ 7:0] radio_rx_stb_radio0,
output wire [ 7:0] radio_rx_running_radio0,
output wire [ 255:0] radio_tx_data_radio0,
input wire [ 7:0] radio_tx_stb_radio0,
output wire [ 7:0] radio_tx_running_radio0,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
@@ -590,7 +590,7 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -601,20 +601,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper
// time
wire [ 63:0] radio0_radio_time;
// x300_radio
wire [ 63:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [ 63:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
// radio
wire [ 255:0] radio0_radio_rx_data;
wire [ 7:0] radio0_radio_rx_stb;
wire [ 7:0] radio0_radio_rx_running;
wire [ 255:0] radio0_radio_tx_data;
wire [ 7:0] radio0_radio_tx_stb;
wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -727,6 +729,8 @@ module rfnoc_image_core #(
.FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
.MEM_CLK_RATE (303819444),
.IN_FIFO_SIZE (),
.OUT_FIFO_SIZE (),
.MTU (MTU)
) b_fifo0_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -880,13 +884,6 @@ module rfnoc_image_core #(
assign radio0_m_ctrlport_resp_status = m_ctrlport_radio0_resp_status;
assign radio0_m_ctrlport_resp_data = m_ctrlport_radio0_resp_data;
assign radio0_radio_rx_data = radio_rx_data_radio0;
assign radio0_radio_rx_stb = radio_rx_stb_radio0;
assign radio_rx_running_radio0 = radio0_radio_rx_running;
assign radio_tx_data_radio0 = radio0_radio_tx_data;
assign radio0_radio_tx_stb = radio_tx_stb_radio0;
assign radio_tx_running_radio0 = radio0_radio_tx_running;
assign fifo0_axi_rst = axi_rst;
assign m_axi_awid = fifo0_m_axi_awid;
assign m_axi_awaddr = fifo0_m_axi_awaddr;
@@ -933,6 +930,13 @@ module rfnoc_image_core #(
assign fifo0_m_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = fifo0_m_axi_rready;
assign radio0_radio_rx_data = radio_rx_data_radio0;
assign radio0_radio_rx_stb = radio_rx_stb_radio0;
assign radio_rx_running_radio0 = radio0_radio_rx_running;
assign radio_tx_data_radio0 = radio0_radio_tx_data;
assign radio0_radio_tx_stb = radio_tx_stb_radio0;
assign radio_tx_running_radio0 = radio0_radio_tx_running;
// Broadcaster/Listener Connections:
assign radio0_radio_time = radio_time;
top/n3xx/n300_bist_image_core.vh
+2 -2
View File
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-28T12:13:45.065455
// File generated on: 2022-03-29T22:54:29.736285
// Source: n300_bist_image_core.yml
// Source SHA256: 2e3de3488c19ed292d6d48c0591d1a39b04772f29b4f47a445fc4f8ab6475613
// Source SHA256: 6c4216a9a0a6064008b2aa7fc1c4c0d22820570c7c1275bab8fefaacd952f6b7
//
`define CHDR_WIDTH 64
top/n3xx/n300_rfnoc_image_core.v
+32 -30
View File
@@ -1,5 +1,5 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:08.459279
// File generated on: 2022-03-29T22:54:30.938217
// Source: n300_rfnoc_image_core.yml
// Source SHA256: 64f2b862b3e60cb0456befb88ea28825b6bba271ff4e86a24ab618932773a861
// Source SHA256: ff8842cde084161d27fda07e5835051fb4355b4579b933e944207a6e33031c3b
//
`default_nettype none
@@ -49,19 +49,19 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio0_resp_ack,
input wire [ 1:0] m_ctrlport_radio0_resp_status,
input wire [ 31:0] m_ctrlport_radio0_resp_data,
// time_keeper
// time
input wire [ 63:0] radio_time,
// x300_radio0
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// radio0
input wire [ 255:0] radio_rx_data_radio0,
input wire [ 7:0] radio_rx_stb_radio0,
output wire [ 7:0] radio_rx_running_radio0,
output wire [ 255:0] radio_tx_data_radio0,
input wire [ 7:0] radio_tx_stb_radio0,
output wire [ 7:0] radio_tx_running_radio0,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
output wire [ 127:0] m_axi_awaddr,
output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst,
@@ -73,8 +73,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready,
output wire [ 255:0] m_axi_wdata,
output wire [ 31:0] m_axi_wstrb,
output wire [2047:0] m_axi_wdata,
output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid,
@@ -85,7 +85,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid,
output wire [ 127:0] m_axi_araddr,
output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst,
@@ -98,7 +98,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid,
input wire [ 255:0] m_axi_rdata,
input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser,
@@ -688,7 +688,7 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -699,20 +699,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper
// time
wire [ 63:0] radio0_radio_time;
// x300_radio
wire [ 63:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [ 63:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
// radio
wire [ 255:0] radio0_radio_rx_data;
wire [ 7:0] radio0_radio_rx_stb;
wire [ 7:0] radio0_radio_rx_running;
wire [ 255:0] radio0_radio_tx_data;
wire [ 7:0] radio0_radio_tx_stb;
wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -772,7 +774,7 @@ module rfnoc_image_core #(
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire [ 3:0] replay0_m_axi_awid;
wire [ 127:0] replay0_m_axi_awaddr;
wire [ 191:0] replay0_m_axi_awaddr;
wire [ 31:0] replay0_m_axi_awlen;
wire [ 11:0] replay0_m_axi_awsize;
wire [ 7:0] replay0_m_axi_awburst;
@@ -784,8 +786,8 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_awuser;
wire [ 3:0] replay0_m_axi_awvalid;
wire [ 3:0] replay0_m_axi_awready;
wire [ 255:0] replay0_m_axi_wdata;
wire [ 31:0] replay0_m_axi_wstrb;
wire [2047:0] replay0_m_axi_wdata;
wire [ 255:0] replay0_m_axi_wstrb;
wire [ 3:0] replay0_m_axi_wlast;
wire [ 3:0] replay0_m_axi_wuser;
wire [ 3:0] replay0_m_axi_wvalid;
@@ -796,7 +798,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_bvalid;
wire [ 3:0] replay0_m_axi_bready;
wire [ 3:0] replay0_m_axi_arid;
wire [ 127:0] replay0_m_axi_araddr;
wire [ 191:0] replay0_m_axi_araddr;
wire [ 31:0] replay0_m_axi_arlen;
wire [ 11:0] replay0_m_axi_arsize;
wire [ 7:0] replay0_m_axi_arburst;
@@ -809,7 +811,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_arvalid;
wire [ 3:0] replay0_m_axi_arready;
wire [ 3:0] replay0_m_axi_rid;
wire [ 255:0] replay0_m_axi_rdata;
wire [2047:0] replay0_m_axi_rdata;
wire [ 7:0] replay0_m_axi_rresp;
wire [ 3:0] replay0_m_axi_rlast;
wire [ 3:0] replay0_m_axi_ruser;
top/n3xx/n300_rfnoc_image_core.vh
+3 -3
View File
@@ -1,5 +1,5 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:08.505495
// File generated on: 2022-03-29T22:54:30.972437
// Source: n300_rfnoc_image_core.yml
// Source SHA256: 64f2b862b3e60cb0456befb88ea28825b6bba271ff4e86a24ab618932773a861
// Source SHA256: ff8842cde084161d27fda07e5835051fb4355b4579b933e944207a6e33031c3b
//
`define CHDR_WIDTH 64
top/n3xx/n310_bist_image_core.v
+41 -35
View File
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-28T12:13:45.473664
// File generated on: 2022-03-29T22:54:30.114198
// Source: n310_bist_image_core.yml
// Source SHA256: 5aef8b31192d245541e1f27905e7ca42e645035f4582bca26ee760fd2f26c335
// Source SHA256: 3f293528e8ab71c93391297481f80833451770735ad8ce695190335ef4457fb4
//
`default_nettype none
@@ -60,22 +60,22 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time_keeper
// time
input wire [ 63:0] radio_time,
// x300_radio0
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// x300_radio1
input wire [ 63:0] radio_rx_data_radio1,
input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 1:0] radio_rx_running_radio1,
output wire [ 63:0] radio_tx_data_radio1,
input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 1:0] radio_tx_running_radio1,
// radio0
input wire [ 255:0] radio_rx_data_radio0,
input wire [ 7:0] radio_rx_stb_radio0,
output wire [ 7:0] radio_rx_running_radio0,
output wire [ 255:0] radio_tx_data_radio0,
input wire [ 7:0] radio_tx_stb_radio0,
output wire [ 7:0] radio_tx_running_radio0,
// radio1
input wire [ 255:0] radio_rx_data_radio1,
input wire [ 7:0] radio_rx_stb_radio1,
output wire [ 7:0] radio_rx_running_radio1,
output wire [ 255:0] radio_tx_data_radio1,
input wire [ 7:0] radio_tx_stb_radio1,
output wire [ 7:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
@@ -766,7 +766,7 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -777,20 +777,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper
// time
wire [ 63:0] radio0_radio_time;
// x300_radio
wire [ 63:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [ 63:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
// radio
wire [ 255:0] radio0_radio_rx_data;
wire [ 7:0] radio0_radio_rx_stb;
wire [ 7:0] radio0_radio_rx_running;
wire [ 255:0] radio0_radio_tx_data;
wire [ 7:0] radio0_radio_tx_stb;
wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -847,7 +849,7 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrl_port
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
@@ -858,20 +860,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time_keeper
// time
wire [ 63:0] radio1_radio_time;
// x300_radio
wire [ 63:0] radio1_radio_rx_data;
wire [ 1:0] radio1_radio_rx_stb;
wire [ 1:0] radio1_radio_rx_running;
wire [ 63:0] radio1_radio_tx_data;
wire [ 1:0] radio1_radio_tx_stb;
wire [ 1:0] radio1_radio_tx_running;
// radio
wire [ 255:0] radio1_radio_rx_data;
wire [ 7:0] radio1_radio_rx_stb;
wire [ 7:0] radio1_radio_rx_running;
wire [ 255:0] radio1_radio_tx_data;
wire [ 7:0] radio1_radio_tx_stb;
wire [ 7:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (3),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
) b_radio1_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -984,6 +988,8 @@ module rfnoc_image_core #(
.FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
.MEM_CLK_RATE (303819444),
.IN_FIFO_SIZE (),
.OUT_FIFO_SIZE (),
.MTU (MTU)
) b_fifo0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
top/n3xx/n310_bist_image_core.vh
+2 -2
View File
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-28T12:13:45.506549
// File generated on: 2022-03-29T22:54:30.148839
// Source: n310_bist_image_core.yml
// Source SHA256: 5aef8b31192d245541e1f27905e7ca42e645035f4582bca26ee760fd2f26c335
// Source SHA256: 3f293528e8ab71c93391297481f80833451770735ad8ce695190335ef4457fb4
//
`define CHDR_WIDTH 64
top/n3xx/n310_rfnoc_image_core.v
+51 -47
View File
@@ -1,5 +1,5 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:09.232810
// File generated on: 2022-03-29T22:54:31.355138
// Source: n310_rfnoc_image_core.yml
// Source SHA256: cc561a3de48fea9e224425413802738d125393f55f6dd46e196db8fdabe09284
// Source SHA256: a15541b7fe850057f8190b2b9f645a4324be36615099db06c5cdcadfd8a634e1
//
`default_nettype none
@@ -60,26 +60,26 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time_keeper
// time
input wire [ 63:0] radio_time,
// x300_radio0
input wire [ 63:0] radio_rx_data_radio0,
input wire [ 1:0] radio_rx_stb_radio0,
output wire [ 1:0] radio_rx_running_radio0,
output wire [ 63:0] radio_tx_data_radio0,
input wire [ 1:0] radio_tx_stb_radio0,
output wire [ 1:0] radio_tx_running_radio0,
// x300_radio1
input wire [ 63:0] radio_rx_data_radio1,
input wire [ 1:0] radio_rx_stb_radio1,
output wire [ 1:0] radio_rx_running_radio1,
output wire [ 63:0] radio_tx_data_radio1,
input wire [ 1:0] radio_tx_stb_radio1,
output wire [ 1:0] radio_tx_running_radio1,
// radio0
input wire [ 255:0] radio_rx_data_radio0,
input wire [ 7:0] radio_rx_stb_radio0,
output wire [ 7:0] radio_rx_running_radio0,
output wire [ 255:0] radio_tx_data_radio0,
input wire [ 7:0] radio_tx_stb_radio0,
output wire [ 7:0] radio_tx_running_radio0,
// radio1
input wire [ 255:0] radio_rx_data_radio1,
input wire [ 7:0] radio_rx_stb_radio1,
output wire [ 7:0] radio_rx_running_radio1,
output wire [ 255:0] radio_tx_data_radio1,
input wire [ 7:0] radio_tx_stb_radio1,
output wire [ 7:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
output wire [ 127:0] m_axi_awaddr,
output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst,
@@ -91,8 +91,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready,
output wire [ 255:0] m_axi_wdata,
output wire [ 31:0] m_axi_wstrb,
output wire [2047:0] m_axi_wdata,
output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid,
@@ -103,7 +103,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid,
output wire [ 127:0] m_axi_araddr,
output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst,
@@ -116,7 +116,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid,
input wire [ 255:0] m_axi_rdata,
input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser,
@@ -1026,7 +1026,7 @@ module rfnoc_image_core #(
wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
wire m_radio0_out_1_tready, m_radio0_out_0_tready;
// ctrl_port
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -1037,20 +1037,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper
// time
wire [ 63:0] radio0_radio_time;
// x300_radio
wire [ 63:0] radio0_radio_rx_data;
wire [ 1:0] radio0_radio_rx_stb;
wire [ 1:0] radio0_radio_rx_running;
wire [ 63:0] radio0_radio_tx_data;
wire [ 1:0] radio0_radio_tx_stb;
wire [ 1:0] radio0_radio_tx_running;
// radio
wire [ 255:0] radio0_radio_rx_data;
wire [ 7:0] radio0_radio_rx_stb;
wire [ 7:0] radio0_radio_rx_running;
wire [ 255:0] radio0_radio_tx_data;
wire [ 7:0] radio0_radio_tx_stb;
wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -1197,7 +1199,7 @@ module rfnoc_image_core #(
wire m_radio1_out_1_tvalid, m_radio1_out_0_tvalid;
wire m_radio1_out_1_tready, m_radio1_out_0_tready;
// ctrl_port
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
@@ -1208,20 +1210,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time_keeper
// time
wire [ 63:0] radio1_radio_time;
// x300_radio
wire [ 63:0] radio1_radio_rx_data;
wire [ 1:0] radio1_radio_rx_stb;
wire [ 1:0] radio1_radio_rx_running;
wire [ 63:0] radio1_radio_tx_data;
wire [ 1:0] radio1_radio_tx_stb;
wire [ 1:0] radio1_radio_tx_running;
// radio
wire [ 255:0] radio1_radio_rx_data;
wire [ 7:0] radio1_radio_rx_stb;
wire [ 7:0] radio1_radio_rx_running;
wire [ 255:0] radio1_radio_tx_data;
wire [ 7:0] radio1_radio_tx_stb;
wire [ 7:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (7),
.CHDR_W (CHDR_W),
.NUM_PORTS (2),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -1281,7 +1285,7 @@ module rfnoc_image_core #(
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire [ 3:0] replay0_m_axi_awid;
wire [ 127:0] replay0_m_axi_awaddr;
wire [ 191:0] replay0_m_axi_awaddr;
wire [ 31:0] replay0_m_axi_awlen;
wire [ 11:0] replay0_m_axi_awsize;
wire [ 7:0] replay0_m_axi_awburst;
@@ -1293,8 +1297,8 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_awuser;
wire [ 3:0] replay0_m_axi_awvalid;
wire [ 3:0] replay0_m_axi_awready;
wire [ 255:0] replay0_m_axi_wdata;
wire [ 31:0] replay0_m_axi_wstrb;
wire [2047:0] replay0_m_axi_wdata;
wire [ 255:0] replay0_m_axi_wstrb;
wire [ 3:0] replay0_m_axi_wlast;
wire [ 3:0] replay0_m_axi_wuser;
wire [ 3:0] replay0_m_axi_wvalid;
@@ -1305,7 +1309,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_bvalid;
wire [ 3:0] replay0_m_axi_bready;
wire [ 3:0] replay0_m_axi_arid;
wire [ 127:0] replay0_m_axi_araddr;
wire [ 191:0] replay0_m_axi_araddr;
wire [ 31:0] replay0_m_axi_arlen;
wire [ 11:0] replay0_m_axi_arsize;
wire [ 7:0] replay0_m_axi_arburst;
@@ -1318,7 +1322,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_arvalid;
wire [ 3:0] replay0_m_axi_arready;
wire [ 3:0] replay0_m_axi_rid;
wire [ 255:0] replay0_m_axi_rdata;
wire [2047:0] replay0_m_axi_rdata;
wire [ 7:0] replay0_m_axi_rresp;
wire [ 3:0] replay0_m_axi_rlast;
wire [ 3:0] replay0_m_axi_ruser;
@@ -1329,8 +1333,8 @@ module rfnoc_image_core #(
.THIS_PORTID (8),
.CHDR_W (CHDR_W),
.NUM_PORTS (4),
.MEM_ADDR_W (31),
.MEM_DATA_W (64),
.MEM_ADDR_W (31),
.MTU (MTU)
) b_replay0_6 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
top/n3xx/n310_rfnoc_image_core.vh
+3 -3
View File
@@ -1,5 +1,5 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:09.279594
// File generated on: 2022-03-29T22:54:31.389520
// Source: n310_rfnoc_image_core.yml
// Source SHA256: cc561a3de48fea9e224425413802738d125393f55f6dd46e196db8fdabe09284
// Source SHA256: a15541b7fe850057f8190b2b9f645a4324be36615099db06c5cdcadfd8a634e1
//
`define CHDR_WIDTH 64
top/n3xx/n320_bist_image_core.v
+55 -49
View File
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-28T12:13:45.909428
// File generated on: 2022-03-29T22:54:30.534235
// Source: n320_bist_image_core.yml
// Source SHA256: aca3751d49ba6f7564282ae55c6368b2cfa11abd1a8abd77af3f4d5cf498e67b
// Source SHA256: 85209582ce2582c5b4469cd57f17249332a777088bca62c20406409eaf3116ec
//
`default_nettype none
@@ -60,22 +60,22 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time_keeper
// time
input wire [ 63:0] radio_time,
// radio_ch0
input wire [ 31:0] radio_rx_data_radio0,
input wire [ 0:0] radio_rx_stb_radio0,
output wire [ 0:0] radio_rx_running_radio0,
output wire [ 31:0] radio_tx_data_radio0,
input wire [ 0:0] radio_tx_stb_radio0,
output wire [ 0:0] radio_tx_running_radio0,
// radio_ch1
input wire [ 31:0] radio_rx_data_radio1,
input wire [ 0:0] radio_rx_stb_radio1,
output wire [ 0:0] radio_rx_running_radio1,
output wire [ 31:0] radio_tx_data_radio1,
input wire [ 0:0] radio_tx_stb_radio1,
output wire [ 0:0] radio_tx_running_radio1,
// radio0
input wire [ 255:0] radio_rx_data_radio0,
input wire [ 7:0] radio_rx_stb_radio0,
output wire [ 7:0] radio_rx_running_radio0,
output wire [ 255:0] radio_tx_data_radio0,
input wire [ 7:0] radio_tx_stb_radio0,
output wire [ 7:0] radio_tx_running_radio0,
// radio1
input wire [ 255:0] radio_rx_data_radio1,
input wire [ 7:0] radio_rx_stb_radio1,
output wire [ 7:0] radio_rx_running_radio1,
output wire [ 255:0] radio_tx_data_radio1,
input wire [ 7:0] radio_tx_stb_radio1,
output wire [ 7:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
@@ -612,7 +612,7 @@ module rfnoc_image_core #(
wire m_radio0_out_0_tvalid;
wire m_radio0_out_0_tready;
// ctrl_port
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -623,20 +623,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper
// time
wire [ 63:0] radio0_radio_time;
// radio_iface
wire [ 31:0] radio0_radio_rx_data;
wire [ 0:0] radio0_radio_rx_stb;
wire [ 0:0] radio0_radio_rx_running;
wire [ 31:0] radio0_radio_tx_data;
wire [ 0:0] radio0_radio_tx_stb;
wire [ 0:0] radio0_radio_tx_running;
// radio
wire [ 255:0] radio0_radio_rx_data;
wire [ 7:0] radio0_radio_rx_stb;
wire [ 7:0] radio0_radio_rx_running;
wire [ 255:0] radio0_radio_tx_data;
wire [ 7:0] radio0_radio_tx_stb;
wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (2),
.CHDR_W (CHDR_W),
.NUM_PORTS (1),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
) b_radio0_0 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -693,7 +695,7 @@ module rfnoc_image_core #(
wire m_radio1_out_0_tvalid;
wire m_radio1_out_0_tready;
// ctrl_port
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
@@ -704,20 +706,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time_keeper
// time
wire [ 63:0] radio1_radio_time;
// radio_iface
wire [ 31:0] radio1_radio_rx_data;
wire [ 0:0] radio1_radio_rx_stb;
wire [ 0:0] radio1_radio_rx_running;
wire [ 31:0] radio1_radio_tx_data;
wire [ 0:0] radio1_radio_tx_stb;
wire [ 0:0] radio1_radio_tx_running;
// radio
wire [ 255:0] radio1_radio_rx_data;
wire [ 7:0] radio1_radio_rx_stb;
wire [ 7:0] radio1_radio_rx_running;
wire [ 255:0] radio1_radio_tx_data;
wire [ 7:0] radio1_radio_tx_stb;
wire [ 7:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (3),
.CHDR_W (CHDR_W),
.NUM_PORTS (1),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
) b_radio1_1 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -830,6 +834,8 @@ module rfnoc_image_core #(
.FIFO_ADDR_BASE ({31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}),
.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}),
.MEM_CLK_RATE (303819444),
.IN_FIFO_SIZE (),
.OUT_FIFO_SIZE (),
.MTU (MTU)
) b_fifo0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -995,20 +1001,6 @@ module rfnoc_image_core #(
assign radio1_m_ctrlport_resp_status = m_ctrlport_radio1_resp_status;
assign radio1_m_ctrlport_resp_data = m_ctrlport_radio1_resp_data;
assign radio0_radio_rx_data = radio_rx_data_radio0;
assign radio0_radio_rx_stb = radio_rx_stb_radio0;
assign radio_rx_running_radio0 = radio0_radio_rx_running;
assign radio_tx_data_radio0 = radio0_radio_tx_data;
assign radio0_radio_tx_stb = radio_tx_stb_radio0;
assign radio_tx_running_radio0 = radio0_radio_tx_running;
assign radio1_radio_rx_data = radio_rx_data_radio1;
assign radio1_radio_rx_stb = radio_rx_stb_radio1;
assign radio_rx_running_radio1 = radio1_radio_rx_running;
assign radio_tx_data_radio1 = radio1_radio_tx_data;
assign radio1_radio_tx_stb = radio_tx_stb_radio1;
assign radio_tx_running_radio1 = radio1_radio_tx_running;
assign fifo0_axi_rst = axi_rst;
assign m_axi_awid = fifo0_m_axi_awid;
assign m_axi_awaddr = fifo0_m_axi_awaddr;
@@ -1055,6 +1047,20 @@ module rfnoc_image_core #(
assign fifo0_m_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = fifo0_m_axi_rready;
assign radio0_radio_rx_data = radio_rx_data_radio0;
assign radio0_radio_rx_stb = radio_rx_stb_radio0;
assign radio_rx_running_radio0 = radio0_radio_rx_running;
assign radio_tx_data_radio0 = radio0_radio_tx_data;
assign radio0_radio_tx_stb = radio_tx_stb_radio0;
assign radio_tx_running_radio0 = radio0_radio_tx_running;
assign radio1_radio_rx_data = radio_rx_data_radio1;
assign radio1_radio_rx_stb = radio_rx_stb_radio1;
assign radio_rx_running_radio1 = radio1_radio_rx_running;
assign radio_tx_data_radio1 = radio1_radio_tx_data;
assign radio1_radio_tx_stb = radio_tx_stb_radio1;
assign radio_tx_running_radio1 = radio1_radio_tx_running;
// Broadcaster/Listener Connections:
assign radio0_radio_time = radio_time;
top/n3xx/n320_bist_image_core.vh
+2 -2
View File
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2022-03-28T12:13:45.942402
// File generated on: 2022-03-29T22:54:30.568990
// Source: n320_bist_image_core.yml
// Source SHA256: aca3751d49ba6f7564282ae55c6368b2cfa11abd1a8abd77af3f4d5cf498e67b
// Source SHA256: 85209582ce2582c5b4469cd57f17249332a777088bca62c20406409eaf3116ec
//
`define CHDR_WIDTH 64
top/n3xx/n320_rfnoc_image_core.v
+50 -46
View File
@@ -1,5 +1,5 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -13,9 +13,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:09.950905
// File generated on: 2022-03-29T22:54:31.762363
// Source: n320_rfnoc_image_core.yml
// Source SHA256: 3c3a33be8bc2e3b3a7268ba3e07001c6dc6c21af4c9027309a787ac8404e5e8f
// Source SHA256: da09e3fb9d6174f301388ddad69e378ce4505b9c9b7f1bc85075880566e98788
//
`default_nettype none
@@ -60,26 +60,26 @@ module rfnoc_image_core #(
input wire [ 0:0] m_ctrlport_radio1_resp_ack,
input wire [ 1:0] m_ctrlport_radio1_resp_status,
input wire [ 31:0] m_ctrlport_radio1_resp_data,
// time_keeper
// time
input wire [ 63:0] radio_time,
// radio_ch0
input wire [ 31:0] radio_rx_data_radio0,
input wire [ 0:0] radio_rx_stb_radio0,
output wire [ 0:0] radio_rx_running_radio0,
output wire [ 31:0] radio_tx_data_radio0,
input wire [ 0:0] radio_tx_stb_radio0,
output wire [ 0:0] radio_tx_running_radio0,
// radio_ch1
input wire [ 31:0] radio_rx_data_radio1,
input wire [ 0:0] radio_rx_stb_radio1,
output wire [ 0:0] radio_rx_running_radio1,
output wire [ 31:0] radio_tx_data_radio1,
input wire [ 0:0] radio_tx_stb_radio1,
output wire [ 0:0] radio_tx_running_radio1,
// radio0
input wire [ 255:0] radio_rx_data_radio0,
input wire [ 7:0] radio_rx_stb_radio0,
output wire [ 7:0] radio_rx_running_radio0,
output wire [ 255:0] radio_tx_data_radio0,
input wire [ 7:0] radio_tx_stb_radio0,
output wire [ 7:0] radio_tx_running_radio0,
// radio1
input wire [ 255:0] radio_rx_data_radio1,
input wire [ 7:0] radio_rx_stb_radio1,
output wire [ 7:0] radio_rx_running_radio1,
output wire [ 255:0] radio_tx_data_radio1,
input wire [ 7:0] radio_tx_stb_radio1,
output wire [ 7:0] radio_tx_running_radio1,
// dram
input wire [ 0:0] axi_rst,
output wire [ 3:0] m_axi_awid,
output wire [ 127:0] m_axi_awaddr,
output wire [ 191:0] m_axi_awaddr,
output wire [ 31:0] m_axi_awlen,
output wire [ 11:0] m_axi_awsize,
output wire [ 7:0] m_axi_awburst,
@@ -91,8 +91,8 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_awuser,
output wire [ 3:0] m_axi_awvalid,
input wire [ 3:0] m_axi_awready,
output wire [ 255:0] m_axi_wdata,
output wire [ 31:0] m_axi_wstrb,
output wire [2047:0] m_axi_wdata,
output wire [ 255:0] m_axi_wstrb,
output wire [ 3:0] m_axi_wlast,
output wire [ 3:0] m_axi_wuser,
output wire [ 3:0] m_axi_wvalid,
@@ -103,7 +103,7 @@ module rfnoc_image_core #(
input wire [ 3:0] m_axi_bvalid,
output wire [ 3:0] m_axi_bready,
output wire [ 3:0] m_axi_arid,
output wire [ 127:0] m_axi_araddr,
output wire [ 191:0] m_axi_araddr,
output wire [ 31:0] m_axi_arlen,
output wire [ 11:0] m_axi_arsize,
output wire [ 7:0] m_axi_arburst,
@@ -116,7 +116,7 @@ module rfnoc_image_core #(
output wire [ 3:0] m_axi_arvalid,
input wire [ 3:0] m_axi_arready,
input wire [ 3:0] m_axi_rid,
input wire [ 255:0] m_axi_rdata,
input wire [2047:0] m_axi_rdata,
input wire [ 7:0] m_axi_rresp,
input wire [ 3:0] m_axi_rlast,
input wire [ 3:0] m_axi_ruser,
@@ -718,7 +718,7 @@ module rfnoc_image_core #(
wire m_radio0_out_0_tvalid;
wire m_radio0_out_0_tready;
// ctrl_port
// ctrlport
wire [ 0:0] radio0_m_ctrlport_req_wr;
wire [ 0:0] radio0_m_ctrlport_req_rd;
wire [ 19:0] radio0_m_ctrlport_req_addr;
@@ -729,20 +729,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio0_m_ctrlport_resp_ack;
wire [ 1:0] radio0_m_ctrlport_resp_status;
wire [ 31:0] radio0_m_ctrlport_resp_data;
// time_keeper
// time
wire [ 63:0] radio0_radio_time;
// radio_iface
wire [ 31:0] radio0_radio_rx_data;
wire [ 0:0] radio0_radio_rx_stb;
wire [ 0:0] radio0_radio_rx_running;
wire [ 31:0] radio0_radio_tx_data;
wire [ 0:0] radio0_radio_tx_stb;
wire [ 0:0] radio0_radio_tx_running;
// radio
wire [ 255:0] radio0_radio_rx_data;
wire [ 7:0] radio0_radio_rx_stb;
wire [ 7:0] radio0_radio_rx_running;
wire [ 255:0] radio0_radio_tx_data;
wire [ 7:0] radio0_radio_tx_stb;
wire [ 7:0] radio0_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (4),
.CHDR_W (CHDR_W),
.NUM_PORTS (1),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
) b_radio0_2 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -889,7 +891,7 @@ module rfnoc_image_core #(
wire m_radio1_out_0_tvalid;
wire m_radio1_out_0_tready;
// ctrl_port
// ctrlport
wire [ 0:0] radio1_m_ctrlport_req_wr;
wire [ 0:0] radio1_m_ctrlport_req_rd;
wire [ 19:0] radio1_m_ctrlport_req_addr;
@@ -900,20 +902,22 @@ module rfnoc_image_core #(
wire [ 0:0] radio1_m_ctrlport_resp_ack;
wire [ 1:0] radio1_m_ctrlport_resp_status;
wire [ 31:0] radio1_m_ctrlport_resp_data;
// time_keeper
// time
wire [ 63:0] radio1_radio_time;
// radio_iface
wire [ 31:0] radio1_radio_rx_data;
wire [ 0:0] radio1_radio_rx_stb;
wire [ 0:0] radio1_radio_rx_running;
wire [ 31:0] radio1_radio_tx_data;
wire [ 0:0] radio1_radio_tx_stb;
wire [ 0:0] radio1_radio_tx_running;
// radio
wire [ 255:0] radio1_radio_rx_data;
wire [ 7:0] radio1_radio_rx_stb;
wire [ 7:0] radio1_radio_rx_running;
wire [ 255:0] radio1_radio_tx_data;
wire [ 7:0] radio1_radio_tx_stb;
wire [ 7:0] radio1_radio_tx_running;
rfnoc_block_radio #(
.THIS_PORTID (7),
.CHDR_W (CHDR_W),
.NUM_PORTS (1),
.NIPC (1),
.ITEM_W (32),
.MTU (MTU)
) b_radio1_5 (
.rfnoc_chdr_clk (rfnoc_chdr_clk),
@@ -973,7 +977,7 @@ module rfnoc_image_core #(
// axi_ram
wire [ 0:0] replay0_axi_rst;
wire [ 3:0] replay0_m_axi_awid;
wire [ 127:0] replay0_m_axi_awaddr;
wire [ 191:0] replay0_m_axi_awaddr;
wire [ 31:0] replay0_m_axi_awlen;
wire [ 11:0] replay0_m_axi_awsize;
wire [ 7:0] replay0_m_axi_awburst;
@@ -985,8 +989,8 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_awuser;
wire [ 3:0] replay0_m_axi_awvalid;
wire [ 3:0] replay0_m_axi_awready;
wire [ 255:0] replay0_m_axi_wdata;
wire [ 31:0] replay0_m_axi_wstrb;
wire [2047:0] replay0_m_axi_wdata;
wire [ 255:0] replay0_m_axi_wstrb;
wire [ 3:0] replay0_m_axi_wlast;
wire [ 3:0] replay0_m_axi_wuser;
wire [ 3:0] replay0_m_axi_wvalid;
@@ -997,7 +1001,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_bvalid;
wire [ 3:0] replay0_m_axi_bready;
wire [ 3:0] replay0_m_axi_arid;
wire [ 127:0] replay0_m_axi_araddr;
wire [ 191:0] replay0_m_axi_araddr;
wire [ 31:0] replay0_m_axi_arlen;
wire [ 11:0] replay0_m_axi_arsize;
wire [ 7:0] replay0_m_axi_arburst;
@@ -1010,7 +1014,7 @@ module rfnoc_image_core #(
wire [ 3:0] replay0_m_axi_arvalid;
wire [ 3:0] replay0_m_axi_arready;
wire [ 3:0] replay0_m_axi_rid;
wire [ 255:0] replay0_m_axi_rdata;
wire [2047:0] replay0_m_axi_rdata;
wire [ 7:0] replay0_m_axi_rresp;
wire [ 3:0] replay0_m_axi_rlast;
wire [ 3:0] replay0_m_axi_ruser;
top/n3xx/n320_rfnoc_image_core.vh
+3 -3
View File
@@ -1,5 +1,5 @@
//
// Copyright 2021 Ettus Research, A National Instruments Brand
// Copyright 2022 Ettus Research, A National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
@@ -12,9 +12,9 @@
// This file was automatically generated by the RFNoC image builder tool.
// Re-running that tool will overwrite this file!
//
// File generated on: 2021-05-03T08:51:09.997079
// File generated on: 2022-03-29T22:54:31.796221
// Source: n320_rfnoc_image_core.yml
// Source SHA256: 3c3a33be8bc2e3b3a7268ba3e07001c6dc6c21af4c9027309a787ac8404e5e8f
// Source SHA256: da09e3fb9d6174f301388ddad69e378ce4505b9c9b7f1bc85075880566e98788
//
`define CHDR_WIDTH 64