fpga: Update all RFNoC images
Original-commit: 002ff9698e09b94c396736613e493f79e9c56442
This commit is contained in:
Wade Fife
committed by
Aaron Rossetto
Aaron Rossetto
parent
b81ab96b12
commit
16c1235b30
@@ -1,5 +1,5 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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@@ -13,9 +13,9 @@
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// File generated on: 2021-05-03T08:51:10.699215
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// File generated on: 2022-03-29T22:54:33.413161
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// Source: e320_rfnoc_image_core.yml
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// Source SHA256: 8b38ab7ba86e214c213ab62a63b698739c0858fdf10fcc5b737f87a56fb04454
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// Source SHA256: ed6f477f04b43f41fc51cbc753947560d39edc7520864fb72959a7b856595f47
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//
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`default_nettype none
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@@ -38,7 +38,7 @@ module rfnoc_image_core #(
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// IO ports /////////////////////////
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// ctrl_port
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// ctrlport
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output wire [ 0:0] m_ctrlport_req_wr,
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output wire [ 0:0] m_ctrlport_req_rd,
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output wire [ 19:0] m_ctrlport_req_addr,
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@@ -49,19 +49,19 @@ module rfnoc_image_core #(
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input wire [ 0:0] m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [ 31:0] m_ctrlport_resp_data,
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// time_keeper
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// time
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input wire [ 63:0] radio_time,
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// x300_radio
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input wire [ 63:0] radio_rx_data,
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input wire [ 1:0] radio_rx_stb,
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output wire [ 1:0] radio_rx_running,
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output wire [ 63:0] radio_tx_data,
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input wire [ 1:0] radio_tx_stb,
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output wire [ 1:0] radio_tx_running,
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// radio
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input wire [ 255:0] radio_rx_data,
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input wire [ 7:0] radio_rx_stb,
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output wire [ 7:0] radio_rx_running,
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output wire [ 255:0] radio_tx_data,
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input wire [ 7:0] radio_tx_stb,
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output wire [ 7:0] radio_tx_running,
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// dram
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input wire [ 0:0] axi_rst,
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output wire [ 3:0] m_axi_awid,
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output wire [ 127:0] m_axi_awaddr,
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output wire [ 191:0] m_axi_awaddr,
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output wire [ 31:0] m_axi_awlen,
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output wire [ 11:0] m_axi_awsize,
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output wire [ 7:0] m_axi_awburst,
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@@ -73,8 +73,8 @@ module rfnoc_image_core #(
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output wire [ 3:0] m_axi_awuser,
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output wire [ 3:0] m_axi_awvalid,
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input wire [ 3:0] m_axi_awready,
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output wire [ 255:0] m_axi_wdata,
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output wire [ 31:0] m_axi_wstrb,
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output wire [2047:0] m_axi_wdata,
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output wire [ 255:0] m_axi_wstrb,
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output wire [ 3:0] m_axi_wlast,
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output wire [ 3:0] m_axi_wuser,
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output wire [ 3:0] m_axi_wvalid,
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@@ -85,7 +85,7 @@ module rfnoc_image_core #(
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input wire [ 3:0] m_axi_bvalid,
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output wire [ 3:0] m_axi_bready,
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output wire [ 3:0] m_axi_arid,
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output wire [ 127:0] m_axi_araddr,
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output wire [ 191:0] m_axi_araddr,
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output wire [ 31:0] m_axi_arlen,
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output wire [ 11:0] m_axi_arsize,
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output wire [ 7:0] m_axi_arburst,
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@@ -98,7 +98,7 @@ module rfnoc_image_core #(
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output wire [ 3:0] m_axi_arvalid,
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input wire [ 3:0] m_axi_arready,
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input wire [ 3:0] m_axi_rid,
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input wire [ 255:0] m_axi_rdata,
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input wire [2047:0] m_axi_rdata,
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input wire [ 7:0] m_axi_rresp,
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input wire [ 3:0] m_axi_rlast,
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input wire [ 3:0] m_axi_ruser,
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@@ -679,7 +679,7 @@ module rfnoc_image_core #(
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wire m_radio0_out_1_tvalid, m_radio0_out_0_tvalid;
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wire m_radio0_out_1_tready, m_radio0_out_0_tready;
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// ctrl_port
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// ctrlport
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wire [ 0:0] radio0_m_ctrlport_req_wr;
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wire [ 0:0] radio0_m_ctrlport_req_rd;
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wire [ 19:0] radio0_m_ctrlport_req_addr;
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@@ -690,20 +690,22 @@ module rfnoc_image_core #(
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wire [ 0:0] radio0_m_ctrlport_resp_ack;
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wire [ 1:0] radio0_m_ctrlport_resp_status;
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wire [ 31:0] radio0_m_ctrlport_resp_data;
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// time_keeper
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// time
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wire [ 63:0] radio0_radio_time;
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// x300_radio
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wire [ 63:0] radio0_radio_rx_data;
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wire [ 1:0] radio0_radio_rx_stb;
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wire [ 1:0] radio0_radio_rx_running;
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wire [ 63:0] radio0_radio_tx_data;
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wire [ 1:0] radio0_radio_tx_stb;
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wire [ 1:0] radio0_radio_tx_running;
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// radio
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wire [ 255:0] radio0_radio_rx_data;
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wire [ 7:0] radio0_radio_rx_stb;
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wire [ 7:0] radio0_radio_rx_running;
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wire [ 255:0] radio0_radio_tx_data;
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wire [ 7:0] radio0_radio_tx_stb;
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wire [ 7:0] radio0_radio_tx_running;
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rfnoc_block_radio #(
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.THIS_PORTID (4),
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.CHDR_W (CHDR_W),
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.NUM_PORTS (2),
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.NIPC (1),
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.ITEM_W (32),
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.MTU (MTU)
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) b_radio0_2 (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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@@ -763,7 +765,7 @@ module rfnoc_image_core #(
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// axi_ram
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wire [ 0:0] fifo0_axi_rst;
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wire [ 3:0] fifo0_m_axi_awid;
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wire [ 127:0] fifo0_m_axi_awaddr;
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wire [ 191:0] fifo0_m_axi_awaddr;
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wire [ 31:0] fifo0_m_axi_awlen;
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wire [ 11:0] fifo0_m_axi_awsize;
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wire [ 7:0] fifo0_m_axi_awburst;
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@@ -775,8 +777,8 @@ module rfnoc_image_core #(
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wire [ 3:0] fifo0_m_axi_awuser;
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wire [ 3:0] fifo0_m_axi_awvalid;
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wire [ 3:0] fifo0_m_axi_awready;
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wire [ 255:0] fifo0_m_axi_wdata;
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wire [ 31:0] fifo0_m_axi_wstrb;
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wire [2047:0] fifo0_m_axi_wdata;
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wire [ 255:0] fifo0_m_axi_wstrb;
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wire [ 3:0] fifo0_m_axi_wlast;
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wire [ 3:0] fifo0_m_axi_wuser;
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wire [ 3:0] fifo0_m_axi_wvalid;
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@@ -787,7 +789,7 @@ module rfnoc_image_core #(
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wire [ 3:0] fifo0_m_axi_bvalid;
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wire [ 3:0] fifo0_m_axi_bready;
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wire [ 3:0] fifo0_m_axi_arid;
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wire [ 127:0] fifo0_m_axi_araddr;
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wire [ 191:0] fifo0_m_axi_araddr;
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wire [ 31:0] fifo0_m_axi_arlen;
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wire [ 11:0] fifo0_m_axi_arsize;
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wire [ 7:0] fifo0_m_axi_arburst;
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@@ -800,7 +802,7 @@ module rfnoc_image_core #(
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wire [ 3:0] fifo0_m_axi_arvalid;
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wire [ 3:0] fifo0_m_axi_arready;
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wire [ 3:0] fifo0_m_axi_rid;
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wire [ 255:0] fifo0_m_axi_rdata;
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wire [2047:0] fifo0_m_axi_rdata;
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wire [ 7:0] fifo0_m_axi_rresp;
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wire [ 3:0] fifo0_m_axi_rlast;
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wire [ 3:0] fifo0_m_axi_ruser;
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@@ -810,12 +812,14 @@ module rfnoc_image_core #(
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rfnoc_block_axi_ram_fifo #(
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.THIS_PORTID (5),
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.CHDR_W (CHDR_W),
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.NUM_PORTS (2),
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.MEM_ADDR_W (31),
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.MEM_DATA_W (64),
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.MEM_CLK_RATE (300e6),
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.FIFO_ADDR_BASE ({31'h02000000, 31'h00000000}),
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.FIFO_ADDR_MASK ({31'h01FFFFFF, 31'h01FFFFFF}),
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.NUM_PORTS (2),
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.IN_FIFO_SIZE (),
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.OUT_FIFO_SIZE (),
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.MTU (MTU)
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) b_fifo0_3 (
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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@@ -983,13 +987,6 @@ module rfnoc_image_core #(
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assign radio0_m_ctrlport_resp_status = m_ctrlport_resp_status;
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assign radio0_m_ctrlport_resp_data = m_ctrlport_resp_data;
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assign radio0_radio_rx_data = radio_rx_data;
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assign radio0_radio_rx_stb = radio_rx_stb;
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assign radio_rx_running = radio0_radio_rx_running;
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assign radio_tx_data = radio0_radio_tx_data;
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assign radio0_radio_tx_stb = radio_tx_stb;
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assign radio_tx_running = radio0_radio_tx_running;
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assign fifo0_axi_rst = axi_rst;
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assign m_axi_awid = fifo0_m_axi_awid;
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assign m_axi_awaddr = fifo0_m_axi_awaddr;
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@@ -1036,6 +1033,13 @@ module rfnoc_image_core #(
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assign fifo0_m_axi_rvalid = m_axi_rvalid;
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assign m_axi_rready = fifo0_m_axi_rready;
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assign radio0_radio_rx_data = radio_rx_data;
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assign radio0_radio_rx_stb = radio_rx_stb;
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assign radio_rx_running = radio0_radio_rx_running;
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assign radio_tx_data = radio0_radio_tx_data;
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assign radio0_radio_tx_stb = radio_tx_stb;
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assign radio_tx_running = radio0_radio_tx_running;
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// Broadcaster/Listener Connections:
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assign radio0_radio_time = radio_time;
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@@ -1,5 +1,5 @@
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//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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@@ -12,9 +12,9 @@
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// This file was automatically generated by the RFNoC image builder tool.
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// Re-running that tool will overwrite this file!
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//
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// File generated on: 2021-05-03T08:51:10.746455
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// File generated on: 2022-03-29T22:54:33.447436
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// Source: e320_rfnoc_image_core.yml
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// Source SHA256: 8b38ab7ba86e214c213ab62a63b698739c0858fdf10fcc5b737f87a56fb04454
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// Source SHA256: ed6f477f04b43f41fc51cbc753947560d39edc7520864fb72959a7b856595f47
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//
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`define CHDR_WIDTH 64
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