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fpga: x400: Add makefiles for RF testbenches

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Original-commit: 319d8c6411f62a2150b21b38bfe5fd55366ee700
This commit is contained in:
Wade Fife
2021-06-17 08:16:59 -05:00
parent bdc67122b8
commit 162632e7c1
7 changed files with 212 additions and 3 deletions
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tools/utils/testbenches.excludes
+3 -3
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@@ -1,6 +1,5 @@
# This file contains all testbenches to exlcude from the filter # This file contains all testbenches to exlcude from the filter list discovered
# list discovered by run_testbenches.py # by run_testbenches.py with the Vivado simulator (xsim).
# NOTE: Lines containing "#" are treated as a comment
top/e31x/sim/dram_test top/e31x/sim/dram_test
top/n3xx/sim/arm_to_sfp_loopback top/n3xx/sim/arm_to_sfp_loopback
@@ -15,3 +14,4 @@ lib/axi4s_sv/axi4s_add_bytes_tb
lib/rfnoc/xport_sv/eth_interface_tb lib/rfnoc/xport_sv/eth_interface_tb
top/x400/sim/x4xx_qsfp_wrapper top/x400/sim/x4xx_qsfp_wrapper
top/x400/ip/eth_100g_bd/lbus_tb top/x400/ip/eth_100g_bd/lbus_tb
top/x400/rf/sim
top/x400/rf/100m/Makefile.srcs
+15
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@@ -0,0 +1,15 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
RF_100M_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/100m/, \
adc_3_1_clk_converter.vhd \
dac_1_3_clk_converter.vhd \
dac_2_1_clk_converter.vhd \
adc_gearbox_2x1.v \
ddc_saturate.vhd \
duc_saturate.vhd \
rf_core_100m.v \
))
top/x400/rf/200m/Makefile.srcs
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@@ -0,0 +1,11 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
RF_200M_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/200m/, \
rf_down_4to2.v \
rf_up_2to4.v \
rf_core_200m.v \
))
top/x400/rf/400m/Makefile.srcs
+17
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@@ -0,0 +1,17 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
RF_400M_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/400m/, \
adc_gearbox_2x4.vhd \
adc_gearbox_8x4.v \
dac_gearbox_12x8.vhd \
dac_gearbox_4x2.v \
dac_gearbox_6x12.vhd \
dac_gearbox_6x8.vhd \
ddc_400m_saturate.vhd \
duc_400m_saturate.vhd \
rf_core_400m.v \
))
top/x400/rf/common/Makefile.srcs
+18
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@@ -0,0 +1,18 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
RF_COMMON_SRCS = $(abspath $(addprefix $(BASE_DIR)/../top/x400/rf/common/, \
PkgRf.vhd \
axis_mux.vhd \
capture_sysref.v \
clock_gates.vhd \
gpio_to_axis_mux.vhd \
rf_nco_reset.vhd \
rf_reset.vhd \
rf_reset_controller.vhd \
scale_2x.vhd \
sync_wrapper.v \
))
top/x400/rf/testbench/Makefile
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@@ -0,0 +1,91 @@
#
# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
#-------------------------------------------------
# Top-of-Makefile
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir. Note:
# UHD_FPGA_DIR must be passed into this Makefile.
BASE_DIR = ../../..
# Include viv_sim_preample after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
#-------------------------------------------------
# Design Specific
#-------------------------------------------------
# Define part using PART_ID (<device>/<package>/<speedgrade>)
ARCH = zynquplusRFSOC
PART_ID = xczu28dr/ffvg1517/-1/e
# Include makefiles and sources for the DUT and its dependencies
include $(BASE_DIR)/../lib/fifo/Makefile.srcs
include $(BASE_DIR)/../lib/axi/Makefile.srcs
include $(BASE_DIR)/../lib/control/Makefile.srcs
DESIGN_SRCS += $(abspath \
$(FIFO_SRCS) \
$(AXI_SRCS) \
$(CONTROL_LIB_SRCS) \
)
include ../common/Makefile.srcs
include ../100m/Makefile.srcs
include ../200m/Makefile.srcs
include ../400m/Makefile.srcs
DESIGN_SRCS += $(abspath \
../../regmap/PkgRFDC_REGS_REGMAP.vhd \
$(RF_COMMON_SRCS) \
$(RF_100M_SRCS) \
$(RF_200M_SRCS) \
$(RF_400M_SRCS) \
)
#-------------------------------------------------
# IP Specific
#-------------------------------------------------
# If simulation contains IP, define the IP_DIR and point
# it to the base level IP directory
IP_DIR = $(BASE_DIR)/x400/ip
LIB_IP_DIR = $(BASE_DIR)/../lib/ip
# Include makefiles and sources for all IP components
# *after* defining the IP_DIR
#
# These TBs don't use any IP yet :)
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
include $(BASE_DIR)/../sim/general/Makefile.srcs
# Define only one top-level module
SIM_TOP = rf_all_tb
# Simulation runtime in microseconds
SIM_RUNTIME_US = 1000
SIM_SRCS = \
$(abspath tb_adc_gearbox_2x1.vhd ) \
$(abspath tb_adc_gearbox_2x4.vhd ) \
$(abspath tb_adc_gearbox_8x4.vhd ) \
$(abspath tb_capture_sysref.vhd ) \
$(abspath tb_dac_gearbox_12x8.vhd ) \
$(abspath tb_dac_gearbox_4x2.vhd ) \
$(abspath tb_dac_gearbox_6x12.vhd ) \
$(abspath tb_ddc_400m_saturate.vhd ) \
$(abspath tb_duc_400m_saturate.vhd ) \
$(abspath tb_rf_nco_reset.vhd ) \
$(abspath tb_rf_reset_controller.vhd) \
$(abspath rf_all_tb.sv ) \
#-------------------------------------------------
# Bottom-of-Makefile
#-------------------------------------------------
# Include all simulator specific makefiles here
# Each should define a unique target to simulate
# e.g. xsim, vsim, etc and a common "clean" target
include $(BASE_DIR)/../tools/make/viv_simulator.mak
top/x400/rf/testbench/rf_all_tb.sv
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//
// Copyright 2021 Ettus Research, a National Instruments Brand
//
// SPDX-License-Identifier: LGPL-3.0-or-later
//
// Module: rf_all_tb
//
// Description:
//
// Top-level testbench for X400 RF components. This instantiates all the RF
// testbenches.
//
module rf_all_tb;
`include "test_exec.svh"
import PkgTestExec::*;
tb_adc_gearbox_2x1 tb_adc_gearbox_2x1_i ();
tb_adc_gearbox_2x4 tb_adc_gearbox_2x4_i ();
tb_adc_gearbox_8x4 tb_adc_gearbox_8x4_i ();
tb_capture_sysref tb_capture_sysref_i ();
tb_dac_gearbox_12x8 tb_dac_gearbox_12x8_i ();
tb_dac_gearbox_4x2 tb_dac_gearbox_4x2_i ();
tb_dac_gearbox_6x12 tb_dac_gearbox_6x12_i ();
tb_ddc_400m_saturate tb_ddc_400m_saturate_i ();
tb_duc_400m_saturate tb_duc_400m_saturate_i ();
tb_rf_nco_reset tb_rf_nco_reset_i ();
tb_rf_reset_controller tb_rf_reset_controller_i ();
initial begin
test.start_tb("rf_all_tb", 1ms);
test.start_test("Run RF TBs");
forever begin
#100ns;
if (
tb_adc_gearbox_2x1_i.StopSim &&
tb_adc_gearbox_2x4_i.StopSim &&
tb_adc_gearbox_8x4_i.StopSim &&
tb_capture_sysref_i.StopSim &&
tb_dac_gearbox_12x8_i.StopSim &&
tb_dac_gearbox_4x2_i.StopSim &&
tb_dac_gearbox_6x12_i.StopSim &&
tb_ddc_400m_saturate_i.StopSim &&
tb_duc_400m_saturate_i.StopSim &&
tb_rf_nco_reset_i.StopSim &&
tb_rf_reset_controller_i.StopSim
) break;
end
test.end_test();
// If they all stop before the timeout, and there are no errors, then we
// assume everything passed.
test.end_tb();
end
endmodule : rf_all_tb