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fpga: x300: Change MIG arbitration to RD_PRI_REG

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Original-commit: 27ebd95d29ed457ef032604b034b8326da0a20aa
This commit is contained in:
Wade Fife
2022-11-08 08:20:48 -06:00
parent 729aa788af
commit 104ae54542
2 changed files with 2 additions and 2 deletions
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top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj
+1 -1
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@@ -152,7 +152,7 @@
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR> <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface> <PortInterface>AXI</PortInterface>
<AXIParameters> <AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM> <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH> <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH> <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH> <C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>
top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj
+1 -1
View File
@@ -152,7 +152,7 @@
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR> <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface> <PortInterface>AXI</PortInterface>
<AXIParameters> <AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM> <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH> <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH> <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH> <C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>