From 104ae54542b0bcd7ce836cfe93805f74f06756ed Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Tue, 1 Nov 2022 18:54:08 -0500
Subject: [PATCH] fpga: x300: Change MIG arbitration to RD_PRI_REG

Original-commit: 27ebd95d29ed457ef032604b034b8326da0a20aa
---
 top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj | 2 +-
 top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj b/top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj
index ed5c3dc..4e88a98 100644
--- a/top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj
+++ b/top/x300/ip/ddr3_32bit/mig_xc7k325tffg900-2.prj
@@ -152,7 +152,7 @@
         <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
         <PortInterface>AXI</PortInterface>
         <AXIParameters>
-            <C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM>
+            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
             <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
             <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
             <C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>
diff --git a/top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj b/top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj
index 00c7fa3..be3c93d 100644
--- a/top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj
+++ b/top/x300/ip/ddr3_32bit/mig_xc7k410tffg900-2.prj
@@ -152,7 +152,7 @@
         <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
         <PortInterface>AXI</PortInterface>
         <AXIParameters>
-            <C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM>
+            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
             <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
             <C0_S_AXI_DATA_WIDTH>256</C0_S_AXI_DATA_WIDTH>
             <C0_S_AXI_ID_WIDTH>1</C0_S_AXI_ID_WIDTH>