fpga: lib: Update simple_spi_core documentation

Original-commit: 65ba3dc518759804d14fa7b18cb374ccccb7a63c
2025-02-10 16:46:53 -06:00
parent 285f7b26a1
commit 0f431ebdd5
1 changed files with 4 additions and 4 deletions
@@ -25,8 +25,8 @@
 //
 // BASE+2 input data
 // Writing this register begins a spi transaction.
-// Bits are latched out from bit 0.
-// Therefore, load this register in reverse.
+// Bits are latched out starting from bit 31.
+// Therefore, data has to be MSB aligned for transmission.
 //
 // Readback
 // Bits are latched into bit 0.