From 0f431ebdd52a0fd80160d4076ec026f211a73f56 Mon Sep 17 00:00:00 2001 From: Markus Schill Date: Fri, 7 Feb 2025 18:04:29 +0100 Subject: [PATCH] fpga: lib: Update simple_spi_core documentation Original-commit: 65ba3dc518759804d14fa7b18cb374ccccb7a63c --- lib/control/simple_spi_core.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/control/simple_spi_core.v b/lib/control/simple_spi_core.v index dd94b1b..84e5073 100644 --- a/lib/control/simple_spi_core.v +++ b/lib/control/simple_spi_core.v @@ -25,8 +25,8 @@ // // BASE+2 input data // Writing this register begins a spi transaction. -// Bits are latched out from bit 0. -// Therefore, load this register in reverse. +// Bits are latched out starting from bit 31. +// Therefore, data has to be MSB aligned for transmission. // // Readback // Bits are latched into bit 0. @@ -122,7 +122,7 @@ module simple_spi_core // IJB. One pipeline stage to break critical path from register in I/O pads. reg [31:0] dataout_reg; wire [31:0] dataout_next = {dataout_reg[30:0], 1'b0}; - + always @(posedge clock) mosi <= dataout_reg[31]; @@ -133,7 +133,7 @@ module simple_spi_core miso_pipe2 <= miso; miso_pipe <= miso_pipe2; end - + reg [31:0] datain_reg; wire [31:0] datain_next = {datain_reg[30:0], miso_pipe}; assign readback = datain_reg;