fpga: lib: Add width agnostic version of Ethernet Interface
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run
at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.
eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.
eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.
Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
This commit is contained in:
Andrew Moch
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wave.do
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*.dcp
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*.rpt
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#
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# Copyright 2020 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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SYNTH_DUT = eth_ifc_synth_test
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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include $(BASE_DIR)/../lib/axi/Makefile.srcs
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include $(BASE_DIR)/../lib/axi4s_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs
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include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/xport/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/xport_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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BUILD_IP_DIR = $(abspath $(BASE_DIR)/x300/build-ip/xc7k410tffg900-2)
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IP_SRC = \
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$(abspath $(BUILD_IP_DIR)/fifo_short_2clk/fifo_short_2clk_sim_netlist.v)
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# Xilinx IP wants lots of libraries
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MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm
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MODELSIM_ARGS += glbl -t 1fs
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DESIGN_SRCS = $(abspath \
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eth_ifc_synth_test.sv \
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$(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(AXI_SRCS) \
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$(AXI4S_SV_SRCS) \
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$(XGE_INTERFACE_SRCS) \
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$(PACKET_PROC_SRCS) \
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$(RFNOC_UTIL_SRCS) \
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$(RFNOC_XPORT_SRCS) \
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$(RFNOC_XPORT_SV_SRCS) \
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$(RFNOC_XBAR_SRCS) \
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$(RFNOC_CORE_SRCS) \
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$(IP_SRC) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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TB_TOP_MODULE ?= eth_ifc_all_tb
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#TB_TOP_MODULE ?= eth_ifc_synth_test
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SIM_TOP = $(TB_TOP_MODULE)
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SIM_SRCS = \
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$(abspath eth_ifc_tb.sv) \
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$(abspath $(TB_TOP_MODULE).sv)
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# supressing the following worthless reminder.
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#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
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# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
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SVLOG_ARGS = -suppress 2583 -keep_delta
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VLOG_ARGS = -keep_delta
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_ifc_all_tb
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//
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// Description: Testbench for eth_ifc
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//
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module eth_ifc_all_tb #(
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/* no PARAM */
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)(
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/* no IO */
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);
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eth_ifc_tb #(.TEST_NAME("ORIGINAL"),.ENET_W(64),.CPU_W(64),.CHDR_W(64),.SV_ETH_IFC(0)) ORIGINAL ();
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eth_ifc_tb #(.TEST_NAME("64B"),.ENET_W(64),.CPU_W(64),.CHDR_W(64)) ETH64 ();
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eth_ifc_tb #(.TEST_NAME("512_64B"),.ENET_W(512),.CPU_W(64),.CHDR_W(64)) ETH512_CHDR64 ();
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eth_ifc_tb #(.TEST_NAME("512_128B"),.ENET_W(512),.CPU_W(64),.CHDR_W(128)) ETH512_CHDR128 ();
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eth_ifc_tb #(.TEST_NAME("512B"),.ENET_W(512),.CPU_W(64),.CHDR_W(512)) ETH512_CHDR512 ();
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endmodule
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//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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//
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// Module: eth_ifc_synth_test
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//
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// Description: Wrapper to test size of 64 bit version
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//
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// Parameters: -- get descriptions from eth_ipv4_interface
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// PROTOVER -
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// MTU - Max Packet Size
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// NODE_INST -
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// RT_TBL_SIZE -
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// REG_AWIDTH -
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// BASE -
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// EWIDTH - Ethernet Width
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// CWIDTH - CPU Width
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// VWIDTH - CHDR Width
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module eth_ifc_synth_test #(
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parameter [15:0] PROTOVER = {8'd1, 8'd0},
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parameter MTU = 10,
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parameter NODE_INST = 0,
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parameter RT_TBL_SIZE = 6,
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parameter REG_AWIDTH = 14,
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parameter BASE = 0,
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parameter EWIDTH = 512,
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parameter CWIDTH = 64,
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parameter VWIDTH = 128
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) (
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input logic bus_clk,
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input logic bus_rst,
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input logic [15:0] device_id,
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// Register port: Write port (domain: clk)
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input logic reg_wr_req,
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input logic [REG_AWIDTH-1:0] reg_wr_addr,
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input logic [31:0] reg_wr_data,
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// Register port: Read port (domain: clk)
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input logic reg_rd_req,
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input logic [REG_AWIDTH-1:0] reg_rd_addr,
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output logic reg_rd_resp,
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output logic [31:0] reg_rd_data,
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// Status ports (domain: clk)
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output logic [47:0] my_mac,
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output logic [31:0] my_ip,
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output logic [15:0] my_udp_chdr_port,
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// Ethernet ports
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output logic [EWIDTH-1:0] eth_tx_tdata,
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output logic [$clog2(EWIDTH/8):0] eth_tx_tuser,
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output logic eth_tx_tlast,
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output logic eth_tx_tvalid,
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input logic eth_tx_tready,
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input logic [EWIDTH-1:0] eth_rx_tdata,
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input logic [$clog2(EWIDTH/8):0] eth_rx_tuser,
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input logic eth_rx_tlast,
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input logic eth_rx_tvalid,
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output logic eth_rx_tready,
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// CHDR router interface
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output logic [VWIDTH-1:0] e2v_tdata,
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output logic e2v_tlast,
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output logic e2v_tvalid,
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input logic e2v_tready,
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input logic [VWIDTH-1:0] v2e_tdata,
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input logic v2e_tlast,
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input logic v2e_tvalid,
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output logic v2e_tready,
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// CPU
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output logic [CWIDTH-1:0] e2c_tdata,
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output logic [$clog2(CWIDTH/8):0] e2c_tuser,
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output logic e2c_tlast,
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output logic e2c_tvalid,
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input logic e2c_tready,
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input logic [CWIDTH-1:0] c2e_tdata,
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input logic [$clog2(CWIDTH/8):0] c2e_tuser,
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input logic c2e_tlast,
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input logic c2e_tvalid,
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output logic c2e_tready
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);
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localparam MAX_PACKET_BYTES = 2**16;
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localparam ENET_W=EWIDTH;
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localparam ENET_USER_W=$clog2(EWIDTH/8)+1;
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localparam CHDR_W=VWIDTH;
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localparam CHDR_USER_W=$clog2(VWIDTH/8)+1;
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localparam CPU_W=CWIDTH;
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localparam CPU_USER_W=$clog2(CWIDTH/8)+1;
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0),
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.MAX_PACKET_BYTES(MAX_PACKET_BYTES))
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eth_tx (bus_clk, bus_reset);
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AxiStreamIf #(.DATA_WIDTH(ENET_W),.USER_WIDTH(ENET_USER_W),.TKEEP(0),
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.MAX_PACKET_BYTES(MAX_PACKET_BYTES))
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eth_rx (bus_clk, bus_reset);
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AxiStreamIf #(.DATA_WIDTH(CHDR_W),.USER_WIDTH(CHDR_USER_W),.TKEEP(0),.TUSER(0))
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v2e (bus_clk, bus_reset);
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AxiStreamIf #(.DATA_WIDTH(CHDR_W),.USER_WIDTH(CHDR_USER_W),.TKEEP(0),.TUSER(0))
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e2v (bus_clk, bus_reset);
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AxiStreamIf #(.DATA_WIDTH(CPU_W),.USER_WIDTH(CPU_USER_W),.TKEEP(0))
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c2e (bus_clk, bus_reset);
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AxiStreamIf #(.DATA_WIDTH(CPU_W),.USER_WIDTH(CPU_USER_W),.TKEEP(0))
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e2c (bus_clk, bus_reset);
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assign eth_tx_tdata = eth_tx.tdata;
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assign eth_tx_tuser = eth_tx.tuser;
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assign eth_tx_tlast = eth_tx.tlast;
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assign eth_tx_tvalid = eth_tx.tvalid;
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assign eth_tx.tready = eth_tx_tready;
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assign eth_rx.tdata = eth_rx_tdata;
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assign eth_rx.tuser = eth_rx_tuser;
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assign eth_rx.tlast = eth_rx_tlast;
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assign eth_rx.tvalid = eth_rx_tvalid;
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assign eth_rx_tready = eth_rx.tready;
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assign e2v_tdata = e2v.tdata;
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assign e2v_tlast = e2v.tlast;
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assign e2v_tvalid = e2v.tvalid;
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assign e2v.tready = e2v_tready;
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assign v2e.tdata = v2e_tdata;
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assign v2e.tlast = v2e_tlast;
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assign v2e.tvalid = v2e_tvalid;
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assign v2e_tready = v2e.tready;
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assign e2c_tdata = e2c.tdata;
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assign e2c_tuser = e2c.tuser;
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assign e2c_tlast = e2c.tlast;
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assign e2c_tvalid = e2c.tvalid;
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assign e2c.tready = e2c_tready;
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assign c2e.tdata = c2e_tdata;
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assign c2e.tuser = c2e_tuser;
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assign c2e.tlast = c2e_tlast;
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assign c2e.tvalid = c2e_tvalid;
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assign c2e_tready = c2e.tready;
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eth_ipv4_interface #(
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.PROTOVER(PROTOVER), .MTU(MTU), .NODE_INST(NODE_INST),
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.REG_AWIDTH(REG_AWIDTH), .RT_TBL_SIZE(RT_TBL_SIZE),
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.BASE(BASE),
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.DROP_UNKNOWN_MAC(0),
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.DROP_MIN_PACKET(0),
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.PREAMBLE_BYTES(0),
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.ADD_SOF(0),
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.SYNC(0),
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.ENET_W(EWIDTH),.CPU_W(CWIDTH),.CHDR_W(VWIDTH)
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) eth_interface (
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.* );
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endmodule
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